2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Jason Ekstrand (jason@jlekstrand.net)
32 * This file implements an out-of-SSA pass as described in "Revisiting
33 * Out-of-SSA Translation for Correctness, Code Quality, and Efficiency" by
37 struct from_ssa_state
{
41 struct hash_table
*merge_node_table
;
43 nir_function_impl
*impl
;
46 /* Returns true if a dominates b */
48 ssa_def_dominates(nir_ssa_def
*a
, nir_ssa_def
*b
)
50 if (a
->live_index
== 0) {
51 /* SSA undefs always dominate */
53 } else if (b
->live_index
< a
->live_index
) {
55 } else if (a
->parent_instr
->block
== b
->parent_instr
->block
) {
56 return a
->live_index
<= b
->live_index
;
58 return nir_block_dominates(a
->parent_instr
->block
,
59 b
->parent_instr
->block
);
64 /* The following data structure, which I have named merge_set is a way of
65 * representing a set registers of non-interfering registers. This is
66 * based on the concept of a "dominence forest" presented in "Fast Copy
67 * Coalescing and Live-Range Identification" by Budimlic et. al. but the
68 * implementation concept is taken from "Revisiting Out-of-SSA Translation
69 * for Correctness, Code Quality, and Efficiency" by Boissinot et. al..
71 * Each SSA definition is associated with a merge_node and the association
72 * is represented by a combination of a hash table and the "def" parameter
73 * in the merge_node structure. The merge_set stores a linked list of
74 * merge_node's in dominence order of the ssa definitions. (Since the
75 * liveness analysis pass indexes the SSA values in dominence order for us,
76 * this is an easy thing to keep up.) It is assumed that no pair of the
77 * nodes in a given set interfere. Merging two sets or checking for
78 * interference can be done in a single linear-time merge-sort walk of the
84 struct exec_node node
;
85 struct merge_set
*set
;
89 typedef struct merge_set
{
90 struct exec_list nodes
;
97 merge_set_dump(merge_set
*set
, FILE *fp
)
99 nir_ssa_def
*dom
[set
->size
];
102 foreach_list_typed(merge_node
, node
, node
, &set
->nodes
) {
103 while (dom_idx
>= 0 && !ssa_def_dominates(dom
[dom_idx
], node
->def
))
106 for (int i
= 0; i
<= dom_idx
; i
++)
110 fprintf(fp
, "ssa_%d /* %s */\n", node
->def
->index
, node
->def
->name
);
112 fprintf(fp
, "ssa_%d\n", node
->def
->index
);
114 dom
[++dom_idx
] = node
->def
;
120 get_merge_node(nir_ssa_def
*def
, struct from_ssa_state
*state
)
122 struct hash_entry
*entry
=
123 _mesa_hash_table_search(state
->merge_node_table
, def
);
127 merge_set
*set
= ralloc(state
->dead_ctx
, merge_set
);
128 exec_list_make_empty(&set
->nodes
);
132 merge_node
*node
= ralloc(state
->dead_ctx
, merge_node
);
135 exec_list_push_head(&set
->nodes
, &node
->node
);
137 _mesa_hash_table_insert(state
->merge_node_table
, def
, node
);
143 merge_nodes_interfere(merge_node
*a
, merge_node
*b
)
145 return nir_ssa_defs_interfere(a
->def
, b
->def
);
148 /* Merges b into a */
150 merge_merge_sets(merge_set
*a
, merge_set
*b
)
152 struct exec_node
*an
= exec_list_get_head(&a
->nodes
);
153 struct exec_node
*bn
= exec_list_get_head(&b
->nodes
);
154 while (!exec_node_is_tail_sentinel(bn
)) {
155 merge_node
*a_node
= exec_node_data(merge_node
, an
, node
);
156 merge_node
*b_node
= exec_node_data(merge_node
, bn
, node
);
158 if (exec_node_is_tail_sentinel(an
) ||
159 a_node
->def
->live_index
> b_node
->def
->live_index
) {
160 struct exec_node
*next
= bn
->next
;
161 exec_node_remove(bn
);
162 exec_node_insert_node_before(an
, bn
);
163 exec_node_data(merge_node
, bn
, node
)->set
= a
;
176 /* Checks for any interference between two merge sets
178 * This is an implementation of Algorithm 2 in "Revisiting Out-of-SSA
179 * Translation for Correctness, Code Quality, and Efficiency" by
183 merge_sets_interfere(merge_set
*a
, merge_set
*b
)
185 NIR_VLA(merge_node
*, dom
, a
->size
+ b
->size
);
188 struct exec_node
*an
= exec_list_get_head(&a
->nodes
);
189 struct exec_node
*bn
= exec_list_get_head(&b
->nodes
);
190 while (!exec_node_is_tail_sentinel(an
) ||
191 !exec_node_is_tail_sentinel(bn
)) {
194 if (exec_node_is_tail_sentinel(an
)) {
195 current
= exec_node_data(merge_node
, bn
, node
);
197 } else if (exec_node_is_tail_sentinel(bn
)) {
198 current
= exec_node_data(merge_node
, an
, node
);
201 merge_node
*a_node
= exec_node_data(merge_node
, an
, node
);
202 merge_node
*b_node
= exec_node_data(merge_node
, bn
, node
);
204 if (a_node
->def
->live_index
<= b_node
->def
->live_index
) {
213 while (dom_idx
>= 0 &&
214 !ssa_def_dominates(dom
[dom_idx
]->def
, current
->def
))
217 if (dom_idx
>= 0 && merge_nodes_interfere(current
, dom
[dom_idx
]))
220 dom
[++dom_idx
] = current
;
227 add_parallel_copy_to_end_of_block(nir_block
*block
, void *void_state
)
229 struct from_ssa_state
*state
= void_state
;
231 bool need_end_copy
= false;
232 if (block
->successors
[0]) {
233 nir_instr
*instr
= nir_block_first_instr(block
->successors
[0]);
234 if (instr
&& instr
->type
== nir_instr_type_phi
)
235 need_end_copy
= true;
238 if (block
->successors
[1]) {
239 nir_instr
*instr
= nir_block_first_instr(block
->successors
[1]);
240 if (instr
&& instr
->type
== nir_instr_type_phi
)
241 need_end_copy
= true;
245 /* If one of our successors has at least one phi node, we need to
246 * create a parallel copy at the end of the block but before the jump
249 nir_parallel_copy_instr
*pcopy
=
250 nir_parallel_copy_instr_create(state
->dead_ctx
);
252 nir_instr_insert(nir_after_block_before_jump(block
), &pcopy
->instr
);
258 static nir_parallel_copy_instr
*
259 get_parallel_copy_at_end_of_block(nir_block
*block
)
261 nir_instr
*last_instr
= nir_block_last_instr(block
);
262 if (last_instr
== NULL
)
265 /* The last instruction may be a jump in which case the parallel copy is
268 if (last_instr
->type
== nir_instr_type_jump
)
269 last_instr
= nir_instr_prev(last_instr
);
271 if (last_instr
&& last_instr
->type
== nir_instr_type_parallel_copy
)
272 return nir_instr_as_parallel_copy(last_instr
);
277 /** Isolate phi nodes with parallel copies
279 * In order to solve the dependency problems with the sources and
280 * destinations of phi nodes, we first isolate them by adding parallel
281 * copies to the beginnings and ends of basic blocks. For every block with
282 * phi nodes, we add a parallel copy immediately following the last phi
283 * node that copies the destinations of all of the phi nodes to new SSA
284 * values. We also add a parallel copy to the end of every block that has
285 * a successor with phi nodes that, for each phi node in each successor,
286 * copies the corresponding sorce of the phi node and adjust the phi to
287 * used the destination of the parallel copy.
289 * In SSA form, each value has exactly one definition. What this does is
290 * ensure that each value used in a phi also has exactly one use. The
291 * destinations of phis are only used by the parallel copy immediately
292 * following the phi nodes and. Thanks to the parallel copy at the end of
293 * the predecessor block, the sources of phi nodes are are the only use of
294 * that value. This allows us to immediately assign all the sources and
295 * destinations of any given phi node to the same register without worrying
296 * about interference at all. We do coalescing to get rid of the parallel
297 * copies where possible.
299 * Before this pass can be run, we have to iterate over the blocks with
300 * add_parallel_copy_to_end_of_block to ensure that the parallel copies at
301 * the ends of blocks exist. We can create the ones at the beginnings as
302 * we go, but the ones at the ends of blocks need to be created ahead of
303 * time because of potential back-edges in the CFG.
306 isolate_phi_nodes_block(nir_block
*block
, void *void_state
)
308 struct from_ssa_state
*state
= void_state
;
310 nir_instr
*last_phi_instr
= NULL
;
311 nir_foreach_instr(block
, instr
) {
312 /* Phi nodes only ever come at the start of a block */
313 if (instr
->type
!= nir_instr_type_phi
)
316 last_phi_instr
= instr
;
319 /* If we don't have any phi's, then there's nothing for us to do. */
320 if (last_phi_instr
== NULL
)
323 /* If we have phi nodes, we need to create a parallel copy at the
324 * start of this block but after the phi nodes.
326 nir_parallel_copy_instr
*block_pcopy
=
327 nir_parallel_copy_instr_create(state
->dead_ctx
);
328 nir_instr_insert_after(last_phi_instr
, &block_pcopy
->instr
);
330 nir_foreach_instr(block
, instr
) {
331 /* Phi nodes only ever come at the start of a block */
332 if (instr
->type
!= nir_instr_type_phi
)
335 nir_phi_instr
*phi
= nir_instr_as_phi(instr
);
336 assert(phi
->dest
.is_ssa
);
337 nir_foreach_phi_src(phi
, src
) {
338 nir_parallel_copy_instr
*pcopy
=
339 get_parallel_copy_at_end_of_block(src
->pred
);
342 nir_parallel_copy_entry
*entry
= rzalloc(state
->dead_ctx
,
343 nir_parallel_copy_entry
);
344 nir_ssa_dest_init(&pcopy
->instr
, &entry
->dest
,
345 phi
->dest
.ssa
.num_components
,
346 phi
->dest
.ssa
.bit_size
, src
->src
.ssa
->name
);
347 exec_list_push_tail(&pcopy
->entries
, &entry
->node
);
349 assert(src
->src
.is_ssa
);
350 nir_instr_rewrite_src(&pcopy
->instr
, &entry
->src
, src
->src
);
352 nir_instr_rewrite_src(&phi
->instr
, &src
->src
,
353 nir_src_for_ssa(&entry
->dest
.ssa
));
356 nir_parallel_copy_entry
*entry
= rzalloc(state
->dead_ctx
,
357 nir_parallel_copy_entry
);
358 nir_ssa_dest_init(&block_pcopy
->instr
, &entry
->dest
,
359 phi
->dest
.ssa
.num_components
, phi
->dest
.ssa
.bit_size
,
361 exec_list_push_tail(&block_pcopy
->entries
, &entry
->node
);
363 nir_ssa_def_rewrite_uses(&phi
->dest
.ssa
,
364 nir_src_for_ssa(&entry
->dest
.ssa
));
366 nir_instr_rewrite_src(&block_pcopy
->instr
, &entry
->src
,
367 nir_src_for_ssa(&phi
->dest
.ssa
));
374 coalesce_phi_nodes_block(nir_block
*block
, void *void_state
)
376 struct from_ssa_state
*state
= void_state
;
378 nir_foreach_instr(block
, instr
) {
379 /* Phi nodes only ever come at the start of a block */
380 if (instr
->type
!= nir_instr_type_phi
)
383 nir_phi_instr
*phi
= nir_instr_as_phi(instr
);
385 assert(phi
->dest
.is_ssa
);
386 merge_node
*dest_node
= get_merge_node(&phi
->dest
.ssa
, state
);
388 nir_foreach_phi_src(phi
, src
) {
389 assert(src
->src
.is_ssa
);
390 merge_node
*src_node
= get_merge_node(src
->src
.ssa
, state
);
391 if (src_node
->set
!= dest_node
->set
)
392 merge_merge_sets(dest_node
->set
, src_node
->set
);
400 aggressive_coalesce_parallel_copy(nir_parallel_copy_instr
*pcopy
,
401 struct from_ssa_state
*state
)
403 nir_foreach_parallel_copy_entry(pcopy
, entry
) {
404 if (!entry
->src
.is_ssa
)
407 /* Since load_const instructions are SSA only, we can't replace their
408 * destinations with registers and, therefore, can't coalesce them.
410 if (entry
->src
.ssa
->parent_instr
->type
== nir_instr_type_load_const
)
413 /* Don't try and coalesce these */
414 if (entry
->dest
.ssa
.num_components
!= entry
->src
.ssa
->num_components
)
417 merge_node
*src_node
= get_merge_node(entry
->src
.ssa
, state
);
418 merge_node
*dest_node
= get_merge_node(&entry
->dest
.ssa
, state
);
420 if (src_node
->set
== dest_node
->set
)
423 if (!merge_sets_interfere(src_node
->set
, dest_node
->set
))
424 merge_merge_sets(src_node
->set
, dest_node
->set
);
429 aggressive_coalesce_block(nir_block
*block
, void *void_state
)
431 struct from_ssa_state
*state
= void_state
;
433 nir_parallel_copy_instr
*start_pcopy
= NULL
;
434 nir_foreach_instr(block
, instr
) {
435 /* Phi nodes only ever come at the start of a block */
436 if (instr
->type
!= nir_instr_type_phi
) {
437 if (instr
->type
!= nir_instr_type_parallel_copy
)
438 break; /* The parallel copy must be right after the phis */
440 start_pcopy
= nir_instr_as_parallel_copy(instr
);
442 aggressive_coalesce_parallel_copy(start_pcopy
, state
);
448 nir_parallel_copy_instr
*end_pcopy
=
449 get_parallel_copy_at_end_of_block(block
);
451 if (end_pcopy
&& end_pcopy
!= start_pcopy
)
452 aggressive_coalesce_parallel_copy(end_pcopy
, state
);
458 rewrite_ssa_def(nir_ssa_def
*def
, void *void_state
)
460 struct from_ssa_state
*state
= void_state
;
463 struct hash_entry
*entry
=
464 _mesa_hash_table_search(state
->merge_node_table
, def
);
466 /* In this case, we're part of a phi web. Use the web's register. */
467 merge_node
*node
= (merge_node
*)entry
->data
;
469 /* If it doesn't have a register yet, create one. Note that all of
470 * the things in the merge set should be the same so it doesn't
471 * matter which node's definition we use.
473 if (node
->set
->reg
== NULL
) {
474 node
->set
->reg
= nir_local_reg_create(state
->impl
);
475 node
->set
->reg
->name
= def
->name
;
476 node
->set
->reg
->num_components
= def
->num_components
;
477 node
->set
->reg
->num_array_elems
= 0;
480 reg
= node
->set
->reg
;
482 if (state
->phi_webs_only
)
485 /* We leave load_const SSA values alone. They act as immediates to
486 * the backend. If it got coalesced into a phi, that's ok.
488 if (def
->parent_instr
->type
== nir_instr_type_load_const
)
491 reg
= nir_local_reg_create(state
->impl
);
492 reg
->name
= def
->name
;
493 reg
->num_components
= def
->num_components
;
494 reg
->num_array_elems
= 0;
497 nir_ssa_def_rewrite_uses(def
, nir_src_for_reg(reg
));
498 assert(list_empty(&def
->uses
) && list_empty(&def
->if_uses
));
500 if (def
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
501 /* If it's an ssa_undef instruction, remove it since we know we just got
502 * rid of all its uses.
504 nir_instr
*parent_instr
= def
->parent_instr
;
505 nir_instr_remove(parent_instr
);
506 ralloc_steal(state
->dead_ctx
, parent_instr
);
510 assert(def
->parent_instr
->type
!= nir_instr_type_load_const
);
512 /* At this point we know a priori that this SSA def is part of a
513 * nir_dest. We can use exec_node_data to get the dest pointer.
515 nir_dest
*dest
= exec_node_data(nir_dest
, def
, ssa
);
517 nir_instr_rewrite_dest(state
->instr
, dest
, nir_dest_for_reg(reg
));
522 /* Resolves ssa definitions to registers. While we're at it, we also
526 resolve_registers_block(nir_block
*block
, void *void_state
)
528 struct from_ssa_state
*state
= void_state
;
530 nir_foreach_instr_safe(block
, instr
) {
531 state
->instr
= instr
;
532 nir_foreach_ssa_def(instr
, rewrite_ssa_def
, state
);
534 if (instr
->type
== nir_instr_type_phi
) {
535 nir_instr_remove(instr
);
536 ralloc_steal(state
->dead_ctx
, instr
);
545 emit_copy(nir_parallel_copy_instr
*pcopy
, nir_src src
, nir_src dest_src
,
548 assert(!dest_src
.is_ssa
&&
549 dest_src
.reg
.indirect
== NULL
&&
550 dest_src
.reg
.base_offset
== 0);
553 assert(src
.ssa
->num_components
>= dest_src
.reg
.reg
->num_components
);
555 assert(src
.reg
.reg
->num_components
>= dest_src
.reg
.reg
->num_components
);
557 nir_alu_instr
*mov
= nir_alu_instr_create(mem_ctx
, nir_op_imov
);
558 nir_src_copy(&mov
->src
[0].src
, &src
, mov
);
559 mov
->dest
.dest
= nir_dest_for_reg(dest_src
.reg
.reg
);
560 mov
->dest
.write_mask
= (1 << dest_src
.reg
.reg
->num_components
) - 1;
562 nir_instr_insert_before(&pcopy
->instr
, &mov
->instr
);
565 /* Resolves a single parallel copy operation into a sequence of mov's
567 * This is based on Algorithm 1 from "Revisiting Out-of-SSA Translation for
568 * Correctness, Code Quality, and Efficiency" by Boissinot et. al..
569 * However, I never got the algorithm to work as written, so this version
570 * is slightly modified.
572 * The algorithm works by playing this little shell game with the values.
573 * We start by recording where every source value is and which source value
574 * each destination value should receive. We then grab any copy whose
575 * destination is "empty", i.e. not used as a source, and do the following:
576 * - Find where its source value currently lives
577 * - Emit the move instruction
578 * - Set the location of the source value to the destination
579 * - Mark the location containing the source value
580 * - Mark the destination as no longer needing to be copied
582 * When we run out of "empty" destinations, we have a cycle and so we
583 * create a temporary register, copy to that register, and mark the value
584 * we copied as living in that temporary. Now, the cycle is broken, so we
585 * can continue with the above steps.
588 resolve_parallel_copy(nir_parallel_copy_instr
*pcopy
,
589 struct from_ssa_state
*state
)
591 unsigned num_copies
= 0;
592 nir_foreach_parallel_copy_entry(pcopy
, entry
) {
593 /* Sources may be SSA */
594 if (!entry
->src
.is_ssa
&& entry
->src
.reg
.reg
== entry
->dest
.reg
.reg
)
600 if (num_copies
== 0) {
601 /* Hooray, we don't need any copies! */
602 nir_instr_remove(&pcopy
->instr
);
606 /* The register/source corresponding to the given index */
607 NIR_VLA_ZERO(nir_src
, values
, num_copies
* 2);
609 /* The current location of a given piece of data. We will use -1 for "null" */
610 NIR_VLA_FILL(int, loc
, num_copies
* 2, -1);
612 /* The piece of data that the given piece of data is to be copied from. We will use -1 for "null" */
613 NIR_VLA_FILL(int, pred
, num_copies
* 2, -1);
615 /* The destinations we have yet to properly fill */
616 NIR_VLA(int, to_do
, num_copies
* 2);
619 /* Now we set everything up:
620 * - All values get assigned a temporary index
621 * - Current locations are set from sources
622 * - Predicessors are recorded from sources and destinations
625 nir_foreach_parallel_copy_entry(pcopy
, entry
) {
626 /* Sources may be SSA */
627 if (!entry
->src
.is_ssa
&& entry
->src
.reg
.reg
== entry
->dest
.reg
.reg
)
631 for (int i
= 0; i
< num_vals
; ++i
) {
632 if (nir_srcs_equal(values
[i
], entry
->src
))
636 src_idx
= num_vals
++;
637 values
[src_idx
] = entry
->src
;
640 nir_src dest_src
= nir_src_for_reg(entry
->dest
.reg
.reg
);
643 for (int i
= 0; i
< num_vals
; ++i
) {
644 if (nir_srcs_equal(values
[i
], dest_src
)) {
645 /* Each destination of a parallel copy instruction should be
646 * unique. A destination may get used as a source, so we still
647 * have to walk the list. However, the predecessor should not,
648 * at this point, be set yet, so we should have -1 here.
650 assert(pred
[i
] == -1);
655 dest_idx
= num_vals
++;
656 values
[dest_idx
] = dest_src
;
659 loc
[src_idx
] = src_idx
;
660 pred
[dest_idx
] = src_idx
;
662 to_do
[++to_do_idx
] = dest_idx
;
665 /* Currently empty destinations we can go ahead and fill */
666 NIR_VLA(int, ready
, num_copies
* 2);
669 /* Mark the ones that are ready for copying. We know an index is a
670 * destination if it has a predecessor and it's ready for copying if
671 * it's not marked as containing data.
673 for (int i
= 0; i
< num_vals
; i
++) {
674 if (pred
[i
] != -1 && loc
[i
] == -1)
675 ready
[++ready_idx
] = i
;
678 while (to_do_idx
>= 0) {
679 while (ready_idx
>= 0) {
680 int b
= ready
[ready_idx
--];
682 emit_copy(pcopy
, values
[loc
[a
]], values
[b
], state
->mem_ctx
);
684 /* If any other copies want a they can find it at b */
687 /* b has been filled, mark it as not needing to be copied */
690 /* If a needs to be filled, it's ready for copying now */
692 ready
[++ready_idx
] = a
;
694 int b
= to_do
[to_do_idx
--];
698 /* If we got here, then we don't have any more trivial copies that we
699 * can do. We have to break a cycle, so we create a new temporary
700 * register for that purpose. Normally, if going out of SSA after
701 * register allocation, you would want to avoid creating temporary
702 * registers. However, we are going out of SSA before register
703 * allocation, so we would rather not create extra register
704 * dependencies for the backend to deal with. If it wants, the
705 * backend can coalesce the (possibly multiple) temporaries.
707 assert(num_vals
< num_copies
* 2);
708 nir_register
*reg
= nir_local_reg_create(state
->impl
);
709 reg
->name
= "copy_temp";
710 reg
->num_array_elems
= 0;
711 if (values
[b
].is_ssa
)
712 reg
->num_components
= values
[b
].ssa
->num_components
;
714 reg
->num_components
= values
[b
].reg
.reg
->num_components
;
715 values
[num_vals
].is_ssa
= false;
716 values
[num_vals
].reg
.reg
= reg
;
718 emit_copy(pcopy
, values
[b
], values
[num_vals
], state
->mem_ctx
);
720 ready
[++ready_idx
] = b
;
724 nir_instr_remove(&pcopy
->instr
);
727 /* Resolves the parallel copies in a block. Each block can have at most
728 * two: One at the beginning, right after all the phi noces, and one at
729 * the end (or right before the final jump if it exists).
732 resolve_parallel_copies_block(nir_block
*block
, void *void_state
)
734 struct from_ssa_state
*state
= void_state
;
736 /* At this point, we have removed all of the phi nodes. If a parallel
737 * copy existed right after the phi nodes in this block, it is now the
740 nir_instr
*first_instr
= nir_block_first_instr(block
);
741 if (first_instr
== NULL
)
742 return true; /* Empty, nothing to do. */
744 if (first_instr
->type
== nir_instr_type_parallel_copy
) {
745 nir_parallel_copy_instr
*pcopy
= nir_instr_as_parallel_copy(first_instr
);
747 resolve_parallel_copy(pcopy
, state
);
750 /* It's possible that the above code already cleaned up the end parallel
751 * copy. However, doing so removed it form the instructions list so we
752 * won't find it here. Therefore, it's safe to go ahead and just look
753 * for one and clean it up if it exists.
755 nir_parallel_copy_instr
*end_pcopy
=
756 get_parallel_copy_at_end_of_block(block
);
758 resolve_parallel_copy(end_pcopy
, state
);
764 nir_convert_from_ssa_impl(nir_function_impl
*impl
, bool phi_webs_only
)
766 struct from_ssa_state state
;
768 state
.mem_ctx
= ralloc_parent(impl
);
769 state
.dead_ctx
= ralloc_context(NULL
);
771 state
.phi_webs_only
= phi_webs_only
;
772 state
.merge_node_table
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
773 _mesa_key_pointer_equal
);
775 nir_foreach_block(impl
, add_parallel_copy_to_end_of_block
, &state
);
776 nir_foreach_block(impl
, isolate_phi_nodes_block
, &state
);
778 /* Mark metadata as dirty before we ask for liveness analysis */
779 nir_metadata_preserve(impl
, nir_metadata_block_index
|
780 nir_metadata_dominance
);
782 nir_metadata_require(impl
, nir_metadata_live_ssa_defs
|
783 nir_metadata_dominance
);
785 nir_foreach_block(impl
, coalesce_phi_nodes_block
, &state
);
786 nir_foreach_block(impl
, aggressive_coalesce_block
, &state
);
788 nir_foreach_block(impl
, resolve_registers_block
, &state
);
790 nir_foreach_block(impl
, resolve_parallel_copies_block
, &state
);
792 nir_metadata_preserve(impl
, nir_metadata_block_index
|
793 nir_metadata_dominance
);
795 /* Clean up dead instructions and the hash tables */
796 _mesa_hash_table_destroy(state
.merge_node_table
, NULL
);
797 ralloc_free(state
.dead_ctx
);
801 nir_convert_from_ssa(nir_shader
*shader
, bool phi_webs_only
)
803 nir_foreach_function(shader
, function
) {
805 nir_convert_from_ssa_impl(function
->impl
, phi_webs_only
);