src/compiler/nir/nir_gather_info.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "nir.h"
  25 #include "main/menums.h"
  26
  27 static void
  28 set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len,
  29             bool is_output_read)
  30 {
  31    for (int i = 0; i < len; i++) {
  32       assert(var->data.location != -1);
  33
  34       int idx = var->data.location + offset + i;
  35       bool is_patch_generic = var->data.patch &&
  36                               idx != VARYING_SLOT_TESS_LEVEL_INNER &&
  37                               idx != VARYING_SLOT_TESS_LEVEL_OUTER &&
  38                               idx != VARYING_SLOT_BOUNDING_BOX0 &&
  39                               idx != VARYING_SLOT_BOUNDING_BOX1;
  40       uint64_t bitfield;
  41
  42       if (is_patch_generic) {
  43          assert(idx >= VARYING_SLOT_PATCH0 && idx < VARYING_SLOT_TESS_MAX);
  44          bitfield = BITFIELD64_BIT(idx - VARYING_SLOT_PATCH0);
  45       }
  46       else {
  47          assert(idx < VARYING_SLOT_MAX);
  48          bitfield = BITFIELD64_BIT(idx);
  49       }
  50
  51       if (var->data.mode == nir_var_shader_in) {
  52          if (is_patch_generic)
  53             shader->info.patch_inputs_read |= bitfield;
  54          else
  55             shader->info.inputs_read |= bitfield;
  56
  57          if (shader->info.stage == MESA_SHADER_FRAGMENT) {
  58             shader->info.fs.uses_sample_qualifier |= var->data.sample;
  59          }
  60       } else {
  61          assert(var->data.mode == nir_var_shader_out);
  62          if (is_output_read) {
  63             if (is_patch_generic) {
  64                shader->info.patch_outputs_read |= bitfield;
  65             } else {
  66                shader->info.outputs_read |= bitfield;
  67             }
  68          } else {
  69             if (is_patch_generic) {
  70                shader->info.patch_outputs_written |= bitfield;
  71             } else if (!var->data.read_only) {
  72                shader->info.outputs_written |= bitfield;
  73             }
  74          }
  75
  76
  77          if (var->data.fb_fetch_output)
  78             shader->info.outputs_read |= bitfield;
  79       }
  80    }
  81 }
  82
  83 /**
  84  * Mark an entire variable as used.  Caller must ensure that the variable
  85  * represents a shader input or output.
  86  */
  87 static void
  88 mark_whole_variable(nir_shader *shader, nir_variable *var, bool is_output_read)
  89 {
  90    const struct glsl_type *type = var->type;
  91
  92    if (nir_is_per_vertex_io(var, shader->info.stage)) {
  93       assert(glsl_type_is_array(type));
  94       type = glsl_get_array_element(type);
  95    }
  96
  97    const unsigned slots =
  98       var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
  99                         : glsl_count_attribute_slots(type, false);
 100
 101    set_io_mask(shader, var, 0, slots, is_output_read);
 102 }
 103
 104 static unsigned
 105 get_io_offset(nir_deref_instr *deref, bool is_vertex_input, bool per_vertex)
 106 {
 107    unsigned offset = 0;
 108
 109    for (nir_deref_instr *d = deref; d; d = nir_deref_instr_parent(d)) {
 110       if (d->deref_type == nir_deref_type_array) {
 111          if (per_vertex && nir_deref_instr_parent(d)->deref_type == nir_deref_type_var)
 112             break;
 113
 114          if (!nir_src_is_const(d->arr.index))
 115             return -1;
 116
 117          offset += glsl_count_attribute_slots(d->type, is_vertex_input) *
 118                    nir_src_as_uint(d->arr.index);
 119       }
 120       /* TODO: we can get the offset for structs here see nir_lower_io() */
 121    }
 122
 123    return offset;
 124 }
 125
 126 /**
 127  * Try to mark a portion of the given varying as used.  Caller must ensure
 128  * that the variable represents a shader input or output.
 129  *
 130  * If the index can't be interpreted as a constant, or some other problem
 131  * occurs, then nothing will be marked and false will be returned.
 132  */
 133 static bool
 134 try_mask_partial_io(nir_shader *shader, nir_variable *var,
 135                     nir_deref_instr *deref, bool is_output_read)
 136 {
 137    const struct glsl_type *type = var->type;
 138    bool per_vertex = nir_is_per_vertex_io(var, shader->info.stage);
 139
 140    if (per_vertex) {
 141       assert(glsl_type_is_array(type));
 142       type = glsl_get_array_element(type);
 143    }
 144
 145    /* The code below only handles:
 146     *
 147     * - Indexing into matrices
 148     * - Indexing into arrays of (arrays, matrices, vectors, or scalars)
 149     *
 150     * For now, we just give up if we see varying structs and arrays of structs
 151     * here marking the entire variable as used.
 152     */
 153    if (!(glsl_type_is_matrix(type) ||
 154          (glsl_type_is_array(type) && !var->data.compact &&
 155           (glsl_type_is_numeric(glsl_without_array(type)) ||
 156            glsl_type_is_boolean(glsl_without_array(type)))))) {
 157
 158       /* If we don't know how to handle this case, give up and let the
 159        * caller mark the whole variable as used.
 160        */
 161       return false;
 162    }
 163
 164    unsigned offset = get_io_offset(deref, false, per_vertex);
 165    if (offset == -1)
 166       return false;
 167
 168    unsigned num_elems;
 169    unsigned elem_width = 1;
 170    unsigned mat_cols = 1;
 171    if (glsl_type_is_array(type)) {
 172       num_elems = glsl_get_aoa_size(type);
 173       if (glsl_type_is_matrix(glsl_without_array(type)))
 174          mat_cols = glsl_get_matrix_columns(glsl_without_array(type));
 175    } else {
 176       num_elems = glsl_get_matrix_columns(type);
 177    }
 178
 179    /* double element width for double types that takes two slots */
 180    if (glsl_type_is_dual_slot(glsl_without_array(type)))
 181       elem_width *= 2;
 182
 183    if (offset >= num_elems * elem_width * mat_cols) {
 184       /* Constant index outside the bounds of the matrix/array.  This could
 185        * arise as a result of constant folding of a legal GLSL program.
 186        *
 187        * Even though the spec says that indexing outside the bounds of a
 188        * matrix/array results in undefined behaviour, we don't want to pass
 189        * out-of-range values to set_io_mask() (since this could result in
 190        * slots that don't exist being marked as used), so just let the caller
 191        * mark the whole variable as used.
 192        */
 193       return false;
 194    }
 195
 196    set_io_mask(shader, var, offset, elem_width, is_output_read);
 197    return true;
 198 }
 199
 200 static void
 201 gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
 202                       void *dead_ctx)
 203 {
 204    switch (instr->intrinsic) {
 205    case nir_intrinsic_demote:
 206    case nir_intrinsic_demote_if:
 207       shader->info.fs.uses_demote = true;
 208    /* fallthrough: quads with helper lanes only might be discarded entirely */
 209    case nir_intrinsic_discard:
 210    case nir_intrinsic_discard_if:
 211       assert(shader->info.stage == MESA_SHADER_FRAGMENT);
 212       shader->info.fs.uses_discard = true;
 213       break;
 214
 215    case nir_intrinsic_interp_deref_at_centroid:
 216    case nir_intrinsic_interp_deref_at_sample:
 217    case nir_intrinsic_interp_deref_at_offset:
 218    case nir_intrinsic_interp_deref_at_vertex:
 219    case nir_intrinsic_load_deref:
 220    case nir_intrinsic_store_deref:{
 221       nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
 222       if (deref->mode == nir_var_shader_in ||
 223           deref->mode == nir_var_shader_out) {
 224          nir_variable *var = nir_deref_instr_get_variable(deref);
 225          bool is_output_read = false;
 226          if (var->data.mode == nir_var_shader_out &&
 227              instr->intrinsic == nir_intrinsic_load_deref)
 228             is_output_read = true;
 229
 230          if (!try_mask_partial_io(shader, var, deref, is_output_read))
 231             mark_whole_variable(shader, var, is_output_read);
 232
 233          /* We need to track which input_reads bits correspond to a
 234           * dvec3/dvec4 input attribute */
 235          if (shader->info.stage == MESA_SHADER_VERTEX &&
 236              var->data.mode == nir_var_shader_in &&
 237              glsl_type_is_dual_slot(glsl_without_array(var->type))) {
 238             for (unsigned i = 0; i < glsl_count_attribute_slots(var->type, false); i++) {
 239                int idx = var->data.location + i;
 240                shader->info.vs.double_inputs |= BITFIELD64_BIT(idx);
 241             }
 242          }
 243       }
 244       break;
 245    }
 246
 247    case nir_intrinsic_load_draw_id:
 248    case nir_intrinsic_load_frag_coord:
 249    case nir_intrinsic_load_point_coord:
 250    case nir_intrinsic_load_front_face:
 251    case nir_intrinsic_load_vertex_id:
 252    case nir_intrinsic_load_vertex_id_zero_base:
 253    case nir_intrinsic_load_base_vertex:
 254    case nir_intrinsic_load_first_vertex:
 255    case nir_intrinsic_load_is_indexed_draw:
 256    case nir_intrinsic_load_base_instance:
 257    case nir_intrinsic_load_instance_id:
 258    case nir_intrinsic_load_sample_id:
 259    case nir_intrinsic_load_sample_pos:
 260    case nir_intrinsic_load_sample_mask_in:
 261    case nir_intrinsic_load_primitive_id:
 262    case nir_intrinsic_load_invocation_id:
 263    case nir_intrinsic_load_local_invocation_id:
 264    case nir_intrinsic_load_local_invocation_index:
 265    case nir_intrinsic_load_work_group_id:
 266    case nir_intrinsic_load_num_work_groups:
 267    case nir_intrinsic_load_tess_coord:
 268    case nir_intrinsic_load_tess_level_outer:
 269    case nir_intrinsic_load_tess_level_inner:
 270    case nir_intrinsic_load_patch_vertices_in:
 271       shader->info.system_values_read |=
 272          (1ull << nir_system_value_from_intrinsic(instr->intrinsic));
 273       break;
 274
 275    case nir_intrinsic_quad_broadcast:
 276    case nir_intrinsic_quad_swap_horizontal:
 277    case nir_intrinsic_quad_swap_vertical:
 278    case nir_intrinsic_quad_swap_diagonal:
 279       if (shader->info.stage == MESA_SHADER_FRAGMENT)
 280          shader->info.fs.needs_helper_invocations = true;
 281       break;
 282
 283    case nir_intrinsic_end_primitive:
 284    case nir_intrinsic_end_primitive_with_counter:
 285       assert(shader->info.stage == MESA_SHADER_GEOMETRY);
 286       shader->info.gs.uses_end_primitive = 1;
 287       /* fall through */
 288
 289    case nir_intrinsic_emit_vertex:
 290    case nir_intrinsic_emit_vertex_with_counter:
 291       if (nir_intrinsic_stream_id(instr) > 0)
 292          shader->info.gs.uses_streams = true;
 293
 294       break;
 295
 296    case nir_intrinsic_bindless_image_atomic_add:
 297    case nir_intrinsic_bindless_image_atomic_and:
 298    case nir_intrinsic_bindless_image_atomic_comp_swap:
 299    case nir_intrinsic_bindless_image_atomic_dec_wrap:
 300    case nir_intrinsic_bindless_image_atomic_exchange:
 301    case nir_intrinsic_bindless_image_atomic_fadd:
 302    case nir_intrinsic_bindless_image_atomic_imax:
 303    case nir_intrinsic_bindless_image_atomic_imin:
 304    case nir_intrinsic_bindless_image_atomic_inc_wrap:
 305    case nir_intrinsic_bindless_image_atomic_or:
 306    case nir_intrinsic_bindless_image_atomic_umax:
 307    case nir_intrinsic_bindless_image_atomic_umin:
 308    case nir_intrinsic_bindless_image_atomic_xor:
 309    case nir_intrinsic_bindless_image_store:
 310    case nir_intrinsic_bindless_image_store_raw_intel:
 311    case nir_intrinsic_global_atomic_add:
 312    case nir_intrinsic_global_atomic_and:
 313    case nir_intrinsic_global_atomic_comp_swap:
 314    case nir_intrinsic_global_atomic_exchange:
 315    case nir_intrinsic_global_atomic_fadd:
 316    case nir_intrinsic_global_atomic_fcomp_swap:
 317    case nir_intrinsic_global_atomic_fmax:
 318    case nir_intrinsic_global_atomic_fmin:
 319    case nir_intrinsic_global_atomic_imax:
 320    case nir_intrinsic_global_atomic_imin:
 321    case nir_intrinsic_global_atomic_or:
 322    case nir_intrinsic_global_atomic_umax:
 323    case nir_intrinsic_global_atomic_umin:
 324    case nir_intrinsic_global_atomic_xor:
 325    case nir_intrinsic_image_atomic_add:
 326    case nir_intrinsic_image_atomic_and:
 327    case nir_intrinsic_image_atomic_comp_swap:
 328    case nir_intrinsic_image_atomic_dec_wrap:
 329    case nir_intrinsic_image_atomic_exchange:
 330    case nir_intrinsic_image_atomic_fadd:
 331    case nir_intrinsic_image_atomic_imax:
 332    case nir_intrinsic_image_atomic_imin:
 333    case nir_intrinsic_image_atomic_inc_wrap:
 334    case nir_intrinsic_image_atomic_or:
 335    case nir_intrinsic_image_atomic_umax:
 336    case nir_intrinsic_image_atomic_umin:
 337    case nir_intrinsic_image_atomic_xor:
 338    case nir_intrinsic_image_deref_atomic_add:
 339    case nir_intrinsic_image_deref_atomic_and:
 340    case nir_intrinsic_image_deref_atomic_comp_swap:
 341    case nir_intrinsic_image_deref_atomic_dec_wrap:
 342    case nir_intrinsic_image_deref_atomic_exchange:
 343    case nir_intrinsic_image_deref_atomic_fadd:
 344    case nir_intrinsic_image_deref_atomic_imax:
 345    case nir_intrinsic_image_deref_atomic_imin:
 346    case nir_intrinsic_image_deref_atomic_inc_wrap:
 347    case nir_intrinsic_image_deref_atomic_or:
 348    case nir_intrinsic_image_deref_atomic_umax:
 349    case nir_intrinsic_image_deref_atomic_umin:
 350    case nir_intrinsic_image_deref_atomic_xor:
 351    case nir_intrinsic_image_deref_store:
 352    case nir_intrinsic_image_deref_store_raw_intel:
 353    case nir_intrinsic_image_store:
 354    case nir_intrinsic_image_store_raw_intel:
 355    case nir_intrinsic_ssbo_atomic_add:
 356    case nir_intrinsic_ssbo_atomic_add_ir3:
 357    case nir_intrinsic_ssbo_atomic_and:
 358    case nir_intrinsic_ssbo_atomic_and_ir3:
 359    case nir_intrinsic_ssbo_atomic_comp_swap:
 360    case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
 361    case nir_intrinsic_ssbo_atomic_exchange:
 362    case nir_intrinsic_ssbo_atomic_exchange_ir3:
 363    case nir_intrinsic_ssbo_atomic_fadd:
 364    case nir_intrinsic_ssbo_atomic_fcomp_swap:
 365    case nir_intrinsic_ssbo_atomic_fmax:
 366    case nir_intrinsic_ssbo_atomic_fmin:
 367    case nir_intrinsic_ssbo_atomic_imax:
 368    case nir_intrinsic_ssbo_atomic_imax_ir3:
 369    case nir_intrinsic_ssbo_atomic_imin:
 370    case nir_intrinsic_ssbo_atomic_imin_ir3:
 371    case nir_intrinsic_ssbo_atomic_or:
 372    case nir_intrinsic_ssbo_atomic_or_ir3:
 373    case nir_intrinsic_ssbo_atomic_umax:
 374    case nir_intrinsic_ssbo_atomic_umax_ir3:
 375    case nir_intrinsic_ssbo_atomic_umin:
 376    case nir_intrinsic_ssbo_atomic_umin_ir3:
 377    case nir_intrinsic_ssbo_atomic_xor:
 378    case nir_intrinsic_ssbo_atomic_xor_ir3:
 379    case nir_intrinsic_store_global:
 380    case nir_intrinsic_store_global_ir3:
 381    case nir_intrinsic_store_ssbo:
 382    case nir_intrinsic_store_ssbo_ir3:
 383       /* Only set this for globally visible memory, not scratch and not
 384        * shared.
 385        */
 386       shader->info.writes_memory = true;
 387       break;
 388
 389    default:
 390       break;
 391    }
 392 }
 393
 394 static void
 395 gather_tex_info(nir_tex_instr *instr, nir_shader *shader)
 396 {
 397    if (shader->info.stage == MESA_SHADER_FRAGMENT &&
 398        nir_tex_instr_has_implicit_derivative(instr))
 399       shader->info.fs.needs_helper_invocations = true;
 400
 401    switch (instr->op) {
 402    case nir_texop_tg4:
 403       shader->info.uses_texture_gather = true;
 404       break;
 405    default:
 406       break;
 407    }
 408 }
 409
 410 static void
 411 gather_alu_info(nir_alu_instr *instr, nir_shader *shader)
 412 {
 413    switch (instr->op) {
 414    case nir_op_fddx:
 415    case nir_op_fddy:
 416       shader->info.uses_fddx_fddy = true;
 417       /* Fall through */
 418    case nir_op_fddx_fine:
 419    case nir_op_fddy_fine:
 420    case nir_op_fddx_coarse:
 421    case nir_op_fddy_coarse:
 422       if (shader->info.stage == MESA_SHADER_FRAGMENT)
 423          shader->info.fs.needs_helper_invocations = true;
 424       break;
 425    default:
 426       break;
 427    }
 428
 429    shader->info.uses_64bit |= instr->dest.dest.ssa.bit_size == 64;
 430    unsigned num_srcs = nir_op_infos[instr->op].num_inputs;
 431    for (unsigned i = 0; i < num_srcs; i++) {
 432       shader->info.uses_64bit |= nir_src_bit_size(instr->src[i].src) == 64;
 433    }
 434 }
 435
 436 static void
 437 gather_info_block(nir_block *block, nir_shader *shader, void *dead_ctx)
 438 {
 439    nir_foreach_instr(instr, block) {
 440       switch (instr->type) {
 441       case nir_instr_type_alu:
 442          gather_alu_info(nir_instr_as_alu(instr), shader);
 443          break;
 444       case nir_instr_type_intrinsic:
 445          gather_intrinsic_info(nir_instr_as_intrinsic(instr), shader, dead_ctx);
 446          break;
 447       case nir_instr_type_tex:
 448          gather_tex_info(nir_instr_as_tex(instr), shader);
 449          break;
 450       case nir_instr_type_call:
 451          assert(!"nir_shader_gather_info only works if functions are inlined");
 452          break;
 453       default:
 454          break;
 455       }
 456    }
 457 }
 458
 459 void
 460 nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
 461 {
 462    shader->info.num_textures = 0;
 463    shader->info.num_images = 0;
 464    shader->info.last_msaa_image = -1;
 465    nir_foreach_variable(var, &shader->uniforms) {
 466       /* Bindless textures and images don't use non-bindless slots. */
 467       if (var->data.bindless)
 468          continue;
 469
 470       shader->info.num_textures += glsl_type_get_sampler_count(var->type);
 471       shader->info.num_images += glsl_type_get_image_count(var->type);
 472
 473       /* Assuming image slots don't have holes (e.g. OpenGL) */
 474       if (glsl_type_is_image(var->type) &&
 475           glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_MS)
 476          shader->info.last_msaa_image = shader->info.num_images - 1;
 477    }
 478
 479    shader->info.inputs_read = 0;
 480    shader->info.outputs_written = 0;
 481    shader->info.outputs_read = 0;
 482    shader->info.patch_outputs_read = 0;
 483    shader->info.patch_inputs_read = 0;
 484    shader->info.patch_outputs_written = 0;
 485    shader->info.system_values_read = 0;
 486    if (shader->info.stage == MESA_SHADER_VERTEX) {
 487       shader->info.vs.double_inputs = 0;
 488    }
 489    if (shader->info.stage == MESA_SHADER_FRAGMENT) {
 490       shader->info.fs.uses_sample_qualifier = false;
 491       shader->info.fs.uses_discard = false;
 492       shader->info.fs.uses_demote = false;
 493       shader->info.fs.needs_helper_invocations = false;
 494    }
 495    shader->info.writes_memory = shader->info.has_transform_feedback_varyings;
 496
 497    void *dead_ctx = ralloc_context(NULL);
 498    nir_foreach_block(block, entrypoint) {
 499       gather_info_block(block, shader, dead_ctx);
 500    }
 501    ralloc_free(dead_ctx);
 502 }