Merge remote-tracking branch 'public/master' into vulkan
[mesa.git] / src / compiler / nir / nir_gather_info.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "nir.h"
25
26 static void
27 gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader)
28 {
29 switch (instr->intrinsic) {
30 case nir_intrinsic_discard:
31 assert(shader->stage == MESA_SHADER_FRAGMENT);
32 shader->info.fs.uses_discard = true;
33 break;
34
35 case nir_intrinsic_load_front_face:
36 case nir_intrinsic_load_vertex_id:
37 case nir_intrinsic_load_vertex_id_zero_base:
38 case nir_intrinsic_load_base_vertex:
39 case nir_intrinsic_load_instance_id:
40 case nir_intrinsic_load_sample_id:
41 case nir_intrinsic_load_sample_pos:
42 case nir_intrinsic_load_sample_mask_in:
43 case nir_intrinsic_load_primitive_id:
44 case nir_intrinsic_load_invocation_id:
45 case nir_intrinsic_load_local_invocation_id:
46 case nir_intrinsic_load_work_group_id:
47 case nir_intrinsic_load_num_work_groups:
48 shader->info.system_values_read |=
49 (1 << nir_system_value_from_intrinsic(instr->intrinsic));
50 break;
51
52 case nir_intrinsic_end_primitive:
53 case nir_intrinsic_end_primitive_with_counter:
54 assert(shader->stage == MESA_SHADER_GEOMETRY);
55 shader->info.gs.uses_end_primitive = 1;
56 break;
57
58 default:
59 break;
60 }
61 }
62
63 static void
64 gather_tex_info(nir_tex_instr *instr, nir_shader *shader)
65 {
66 if (instr->op == nir_texop_tg4)
67 shader->info.uses_texture_gather = true;
68 }
69
70 static bool
71 gather_info_block(nir_block *block, void *shader)
72 {
73 nir_foreach_instr(block, instr) {
74 switch (instr->type) {
75 case nir_instr_type_intrinsic:
76 gather_intrinsic_info(nir_instr_as_intrinsic(instr), shader);
77 break;
78 case nir_instr_type_tex:
79 gather_tex_info(nir_instr_as_tex(instr), shader);
80 break;
81 case nir_instr_type_call:
82 assert(!"nir_shader_gather_info only works if functions are inlined");
83 break;
84 default:
85 break;
86 }
87 }
88
89 return true;
90 }
91
92 /**
93 * Returns the bits in the inputs_read, outputs_written, or
94 * system_values_read bitfield corresponding to this variable.
95 */
96 static inline uint64_t
97 get_io_mask(nir_variable *var, gl_shader_stage stage)
98 {
99 assert(var->data.mode == nir_var_shader_in ||
100 var->data.mode == nir_var_shader_out ||
101 var->data.mode == nir_var_system_value);
102 assert(var->data.location >= 0);
103
104 const struct glsl_type *var_type = var->type;
105 if (stage == MESA_SHADER_GEOMETRY && var->data.mode == nir_var_shader_in) {
106 /* Most geometry shader inputs are per-vertex arrays */
107 if (var->data.location >= VARYING_SLOT_VAR0)
108 assert(glsl_type_is_array(var_type));
109
110 if (glsl_type_is_array(var_type))
111 var_type = glsl_get_array_element(var_type);
112 }
113
114 bool is_vertex_input = (var->data.mode == nir_var_shader_in &&
115 stage == MESA_SHADER_VERTEX);
116 unsigned slots = glsl_count_attribute_slots(var_type, is_vertex_input);
117 return ((1ull << slots) - 1) << var->data.location;
118 }
119
120 void
121 nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
122 {
123 /* This pass does not yet support tessellation shaders */
124 assert(shader->stage == MESA_SHADER_VERTEX ||
125 shader->stage == MESA_SHADER_GEOMETRY ||
126 shader->stage == MESA_SHADER_FRAGMENT ||
127 shader->stage == MESA_SHADER_COMPUTE);
128
129 shader->info.inputs_read = 0;
130 foreach_list_typed(nir_variable, var, node, &shader->inputs)
131 shader->info.inputs_read |= get_io_mask(var, shader->stage);
132
133 /* TODO: Some day we may need to add stream support to NIR */
134 shader->info.outputs_written = 0;
135 foreach_list_typed(nir_variable, var, node, &shader->outputs)
136 shader->info.outputs_written |= get_io_mask(var, shader->stage);
137
138 shader->info.system_values_read = 0;
139 foreach_list_typed(nir_variable, var, node, &shader->system_values)
140 shader->info.system_values_read |= get_io_mask(var, shader->stage);
141
142 shader->info.num_textures = 0;
143 shader->info.num_images = 0;
144 nir_foreach_variable(var, &shader->uniforms) {
145 const struct glsl_type *type = var->type;
146 unsigned count = 1;
147 if (glsl_type_is_array(type)) {
148 count = glsl_get_length(type);
149 type = glsl_get_array_element(type);
150 }
151
152 if (glsl_type_is_image(type)) {
153 shader->info.num_images += count;
154 } else if (glsl_type_is_sampler(type)) {
155 shader->info.num_textures += count;
156 }
157 }
158
159 nir_foreach_block(entrypoint, gather_info_block, shader);
160 }