2 * Copyright © 2014 Connor Abbott
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "nir_instr_set.h"
27 #define HASH(hash, data) _mesa_fnv32_1a_accumulate((hash), (data))
30 hash_src(uint32_t hash
, const nir_src
*src
)
33 hash
= HASH(hash
, src
->ssa
);
38 hash_alu_src(uint32_t hash
, const nir_alu_src
*src
, unsigned num_components
)
40 hash
= HASH(hash
, src
->abs
);
41 hash
= HASH(hash
, src
->negate
);
43 for (unsigned i
= 0; i
< num_components
; i
++)
44 hash
= HASH(hash
, src
->swizzle
[i
]);
46 hash
= hash_src(hash
, &src
->src
);
51 hash_alu(uint32_t hash
, const nir_alu_instr
*instr
)
53 hash
= HASH(hash
, instr
->op
);
54 hash
= HASH(hash
, instr
->dest
.dest
.ssa
.num_components
);
55 hash
= HASH(hash
, instr
->dest
.dest
.ssa
.bit_size
);
56 /* We explicitly don't hash instr->dest.dest.exact */
58 if (nir_op_infos
[instr
->op
].algebraic_properties
& NIR_OP_IS_COMMUTATIVE
) {
59 assert(nir_op_infos
[instr
->op
].num_inputs
== 2);
60 uint32_t hash0
= hash_alu_src(hash
, &instr
->src
[0],
61 nir_ssa_alu_instr_src_components(instr
, 0));
62 uint32_t hash1
= hash_alu_src(hash
, &instr
->src
[1],
63 nir_ssa_alu_instr_src_components(instr
, 1));
64 /* For commutative operations, we need some commutative way of
65 * combining the hashes. One option would be to XOR them but that
66 * means that anything with two identical sources will hash to 0 and
67 * that's common enough we probably don't want the guaranteed
68 * collision. Either addition or multiplication will also work.
72 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
73 hash
= hash_alu_src(hash
, &instr
->src
[i
],
74 nir_ssa_alu_instr_src_components(instr
, i
));
82 hash_deref(uint32_t hash
, const nir_deref_instr
*instr
)
84 hash
= HASH(hash
, instr
->deref_type
);
85 hash
= HASH(hash
, instr
->mode
);
86 hash
= HASH(hash
, instr
->type
);
88 if (instr
->deref_type
== nir_deref_type_var
)
89 return HASH(hash
, instr
->var
);
91 hash
= hash_src(hash
, &instr
->parent
);
93 switch (instr
->deref_type
) {
94 case nir_deref_type_struct
:
95 hash
= HASH(hash
, instr
->strct
.index
);
98 case nir_deref_type_array
:
99 hash
= hash_src(hash
, &instr
->arr
.index
);
102 case nir_deref_type_var
:
103 case nir_deref_type_array_wildcard
:
104 case nir_deref_type_cast
:
109 unreachable("Invalid instruction deref type");
116 hash_load_const(uint32_t hash
, const nir_load_const_instr
*instr
)
118 hash
= HASH(hash
, instr
->def
.num_components
);
120 unsigned size
= instr
->def
.num_components
* (instr
->def
.bit_size
/ 8);
121 hash
= _mesa_fnv32_1a_accumulate_block(hash
, instr
->value
.f32
, size
);
127 cmp_phi_src(const void *data1
, const void *data2
)
129 nir_phi_src
*src1
= *(nir_phi_src
**)data1
;
130 nir_phi_src
*src2
= *(nir_phi_src
**)data2
;
131 return src1
->pred
- src2
->pred
;
135 hash_phi(uint32_t hash
, const nir_phi_instr
*instr
)
137 hash
= HASH(hash
, instr
->instr
.block
);
139 /* sort sources by predecessor, since the order shouldn't matter */
140 unsigned num_preds
= instr
->instr
.block
->predecessors
->entries
;
141 NIR_VLA(nir_phi_src
*, srcs
, num_preds
);
143 nir_foreach_phi_src(src
, instr
) {
147 qsort(srcs
, num_preds
, sizeof(nir_phi_src
*), cmp_phi_src
);
149 for (i
= 0; i
< num_preds
; i
++) {
150 hash
= hash_src(hash
, &srcs
[i
]->src
);
151 hash
= HASH(hash
, srcs
[i
]->pred
);
158 hash_intrinsic(uint32_t hash
, const nir_intrinsic_instr
*instr
)
160 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
161 hash
= HASH(hash
, instr
->intrinsic
);
163 if (info
->has_dest
) {
164 hash
= HASH(hash
, instr
->dest
.ssa
.num_components
);
165 hash
= HASH(hash
, instr
->dest
.ssa
.bit_size
);
168 hash
= _mesa_fnv32_1a_accumulate_block(hash
, instr
->const_index
,
170 * sizeof(instr
->const_index
[0]));
175 hash_tex(uint32_t hash
, const nir_tex_instr
*instr
)
177 hash
= HASH(hash
, instr
->op
);
178 hash
= HASH(hash
, instr
->num_srcs
);
180 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
181 hash
= HASH(hash
, instr
->src
[i
].src_type
);
182 hash
= hash_src(hash
, &instr
->src
[i
].src
);
185 hash
= HASH(hash
, instr
->coord_components
);
186 hash
= HASH(hash
, instr
->sampler_dim
);
187 hash
= HASH(hash
, instr
->is_array
);
188 hash
= HASH(hash
, instr
->is_shadow
);
189 hash
= HASH(hash
, instr
->is_new_style_shadow
);
190 unsigned component
= instr
->component
;
191 hash
= HASH(hash
, component
);
192 hash
= HASH(hash
, instr
->texture_index
);
193 hash
= HASH(hash
, instr
->texture_array_size
);
194 hash
= HASH(hash
, instr
->sampler_index
);
199 /* Computes a hash of an instruction for use in a hash table. Note that this
200 * will only work for instructions where instr_can_rewrite() returns true, and
201 * it should return identical hashes for two instructions that are the same
202 * according nir_instrs_equal().
206 hash_instr(const void *data
)
208 const nir_instr
*instr
= data
;
209 uint32_t hash
= _mesa_fnv32_1a_offset_bias
;
211 switch (instr
->type
) {
212 case nir_instr_type_alu
:
213 hash
= hash_alu(hash
, nir_instr_as_alu(instr
));
215 case nir_instr_type_deref
:
216 hash
= hash_deref(hash
, nir_instr_as_deref(instr
));
218 case nir_instr_type_load_const
:
219 hash
= hash_load_const(hash
, nir_instr_as_load_const(instr
));
221 case nir_instr_type_phi
:
222 hash
= hash_phi(hash
, nir_instr_as_phi(instr
));
224 case nir_instr_type_intrinsic
:
225 hash
= hash_intrinsic(hash
, nir_instr_as_intrinsic(instr
));
227 case nir_instr_type_tex
:
228 hash
= hash_tex(hash
, nir_instr_as_tex(instr
));
231 unreachable("Invalid instruction type");
238 nir_srcs_equal(nir_src src1
, nir_src src2
)
242 return src1
.ssa
== src2
.ssa
;
250 if ((src1
.reg
.indirect
== NULL
) != (src2
.reg
.indirect
== NULL
))
253 if (src1
.reg
.indirect
) {
254 if (!nir_srcs_equal(*src1
.reg
.indirect
, *src2
.reg
.indirect
))
258 return src1
.reg
.reg
== src2
.reg
.reg
&&
259 src1
.reg
.base_offset
== src2
.reg
.base_offset
;
265 nir_alu_srcs_equal(const nir_alu_instr
*alu1
, const nir_alu_instr
*alu2
,
266 unsigned src1
, unsigned src2
)
268 if (alu1
->src
[src1
].abs
!= alu2
->src
[src2
].abs
||
269 alu1
->src
[src1
].negate
!= alu2
->src
[src2
].negate
)
272 for (unsigned i
= 0; i
< nir_ssa_alu_instr_src_components(alu1
, src1
); i
++) {
273 if (alu1
->src
[src1
].swizzle
[i
] != alu2
->src
[src2
].swizzle
[i
])
277 return nir_srcs_equal(alu1
->src
[src1
].src
, alu2
->src
[src2
].src
);
280 /* Returns "true" if two instructions are equal. Note that this will only
281 * work for the subset of instructions defined by instr_can_rewrite(). Also,
282 * it should only return "true" for instructions that hash_instr() will return
283 * the same hash for (ignoring collisions, of course).
287 nir_instrs_equal(const nir_instr
*instr1
, const nir_instr
*instr2
)
289 if (instr1
->type
!= instr2
->type
)
292 switch (instr1
->type
) {
293 case nir_instr_type_alu
: {
294 nir_alu_instr
*alu1
= nir_instr_as_alu(instr1
);
295 nir_alu_instr
*alu2
= nir_instr_as_alu(instr2
);
297 if (alu1
->op
!= alu2
->op
)
300 /* TODO: We can probably acutally do something more inteligent such
301 * as allowing different numbers and taking a maximum or something
303 if (alu1
->dest
.dest
.ssa
.num_components
!= alu2
->dest
.dest
.ssa
.num_components
)
306 if (alu1
->dest
.dest
.ssa
.bit_size
!= alu2
->dest
.dest
.ssa
.bit_size
)
309 /* We explicitly don't hash instr->dest.dest.exact */
311 if (nir_op_infos
[alu1
->op
].algebraic_properties
& NIR_OP_IS_COMMUTATIVE
) {
312 assert(nir_op_infos
[alu1
->op
].num_inputs
== 2);
313 return (nir_alu_srcs_equal(alu1
, alu2
, 0, 0) &&
314 nir_alu_srcs_equal(alu1
, alu2
, 1, 1)) ||
315 (nir_alu_srcs_equal(alu1
, alu2
, 0, 1) &&
316 nir_alu_srcs_equal(alu1
, alu2
, 1, 0));
318 for (unsigned i
= 0; i
< nir_op_infos
[alu1
->op
].num_inputs
; i
++) {
319 if (!nir_alu_srcs_equal(alu1
, alu2
, i
, i
))
325 case nir_instr_type_deref
: {
326 nir_deref_instr
*deref1
= nir_instr_as_deref(instr1
);
327 nir_deref_instr
*deref2
= nir_instr_as_deref(instr2
);
329 if (deref1
->deref_type
!= deref2
->deref_type
||
330 deref1
->mode
!= deref2
->mode
||
331 deref1
->type
!= deref2
->type
)
334 if (deref1
->deref_type
== nir_deref_type_var
)
335 return deref1
->var
== deref2
->var
;
337 if (!nir_srcs_equal(deref1
->parent
, deref2
->parent
))
340 switch (deref1
->deref_type
) {
341 case nir_deref_type_struct
:
342 if (deref1
->strct
.index
!= deref2
->strct
.index
)
346 case nir_deref_type_array
:
347 if (!nir_srcs_equal(deref1
->arr
.index
, deref2
->arr
.index
))
351 case nir_deref_type_var
:
352 case nir_deref_type_array_wildcard
:
353 case nir_deref_type_cast
:
358 unreachable("Invalid instruction deref type");
362 case nir_instr_type_tex
: {
363 nir_tex_instr
*tex1
= nir_instr_as_tex(instr1
);
364 nir_tex_instr
*tex2
= nir_instr_as_tex(instr2
);
366 if (tex1
->op
!= tex2
->op
)
369 if (tex1
->num_srcs
!= tex2
->num_srcs
)
371 for (unsigned i
= 0; i
< tex1
->num_srcs
; i
++) {
372 if (tex1
->src
[i
].src_type
!= tex2
->src
[i
].src_type
||
373 !nir_srcs_equal(tex1
->src
[i
].src
, tex2
->src
[i
].src
)) {
378 if (tex1
->coord_components
!= tex2
->coord_components
||
379 tex1
->sampler_dim
!= tex2
->sampler_dim
||
380 tex1
->is_array
!= tex2
->is_array
||
381 tex1
->is_shadow
!= tex2
->is_shadow
||
382 tex1
->is_new_style_shadow
!= tex2
->is_new_style_shadow
||
383 tex1
->component
!= tex2
->component
||
384 tex1
->texture_index
!= tex2
->texture_index
||
385 tex1
->texture_array_size
!= tex2
->texture_array_size
||
386 tex1
->sampler_index
!= tex2
->sampler_index
) {
392 case nir_instr_type_load_const
: {
393 nir_load_const_instr
*load1
= nir_instr_as_load_const(instr1
);
394 nir_load_const_instr
*load2
= nir_instr_as_load_const(instr2
);
396 if (load1
->def
.num_components
!= load2
->def
.num_components
)
399 if (load1
->def
.bit_size
!= load2
->def
.bit_size
)
402 return memcmp(load1
->value
.f32
, load2
->value
.f32
,
403 load1
->def
.num_components
* (load1
->def
.bit_size
/ 8u)) == 0;
405 case nir_instr_type_phi
: {
406 nir_phi_instr
*phi1
= nir_instr_as_phi(instr1
);
407 nir_phi_instr
*phi2
= nir_instr_as_phi(instr2
);
409 if (phi1
->instr
.block
!= phi2
->instr
.block
)
412 nir_foreach_phi_src(src1
, phi1
) {
413 nir_foreach_phi_src(src2
, phi2
) {
414 if (src1
->pred
== src2
->pred
) {
415 if (!nir_srcs_equal(src1
->src
, src2
->src
))
425 case nir_instr_type_intrinsic
: {
426 nir_intrinsic_instr
*intrinsic1
= nir_instr_as_intrinsic(instr1
);
427 nir_intrinsic_instr
*intrinsic2
= nir_instr_as_intrinsic(instr2
);
428 const nir_intrinsic_info
*info
=
429 &nir_intrinsic_infos
[intrinsic1
->intrinsic
];
431 if (intrinsic1
->intrinsic
!= intrinsic2
->intrinsic
||
432 intrinsic1
->num_components
!= intrinsic2
->num_components
)
435 if (info
->has_dest
&& intrinsic1
->dest
.ssa
.num_components
!=
436 intrinsic2
->dest
.ssa
.num_components
)
439 if (info
->has_dest
&& intrinsic1
->dest
.ssa
.bit_size
!=
440 intrinsic2
->dest
.ssa
.bit_size
)
443 for (unsigned i
= 0; i
< info
->num_srcs
; i
++) {
444 if (!nir_srcs_equal(intrinsic1
->src
[i
], intrinsic2
->src
[i
]))
448 for (unsigned i
= 0; i
< info
->num_indices
; i
++) {
449 if (intrinsic1
->const_index
[i
] != intrinsic2
->const_index
[i
])
455 case nir_instr_type_call
:
456 case nir_instr_type_jump
:
457 case nir_instr_type_ssa_undef
:
458 case nir_instr_type_parallel_copy
:
460 unreachable("Invalid instruction type");
463 unreachable("All cases in the above switch should return");
467 src_is_ssa(nir_src
*src
, void *data
)
474 dest_is_ssa(nir_dest
*dest
, void *data
)
480 /* This function determines if uses of an instruction can safely be rewritten
481 * to use another identical instruction instead. Note that this function must
482 * be kept in sync with hash_instr() and nir_instrs_equal() -- only
483 * instructions that pass this test will be handed on to those functions, and
484 * conversely they must handle everything that this function returns true for.
488 instr_can_rewrite(nir_instr
*instr
)
490 /* We only handle SSA. */
491 if (!nir_foreach_dest(instr
, dest_is_ssa
, NULL
) ||
492 !nir_foreach_src(instr
, src_is_ssa
, NULL
))
495 switch (instr
->type
) {
496 case nir_instr_type_alu
:
497 case nir_instr_type_deref
:
498 case nir_instr_type_tex
:
499 case nir_instr_type_load_const
:
500 case nir_instr_type_phi
:
502 case nir_instr_type_intrinsic
: {
503 const nir_intrinsic_info
*info
=
504 &nir_intrinsic_infos
[nir_instr_as_intrinsic(instr
)->intrinsic
];
505 return (info
->flags
& NIR_INTRINSIC_CAN_ELIMINATE
) &&
506 (info
->flags
& NIR_INTRINSIC_CAN_REORDER
);
508 case nir_instr_type_call
:
509 case nir_instr_type_jump
:
510 case nir_instr_type_ssa_undef
:
512 case nir_instr_type_parallel_copy
:
514 unreachable("Invalid instruction type");
521 nir_instr_get_dest_ssa_def(nir_instr
*instr
)
523 switch (instr
->type
) {
524 case nir_instr_type_alu
:
525 assert(nir_instr_as_alu(instr
)->dest
.dest
.is_ssa
);
526 return &nir_instr_as_alu(instr
)->dest
.dest
.ssa
;
527 case nir_instr_type_deref
:
528 assert(nir_instr_as_deref(instr
)->dest
.is_ssa
);
529 return &nir_instr_as_deref(instr
)->dest
.ssa
;
530 case nir_instr_type_load_const
:
531 return &nir_instr_as_load_const(instr
)->def
;
532 case nir_instr_type_phi
:
533 assert(nir_instr_as_phi(instr
)->dest
.is_ssa
);
534 return &nir_instr_as_phi(instr
)->dest
.ssa
;
535 case nir_instr_type_intrinsic
:
536 assert(nir_instr_as_intrinsic(instr
)->dest
.is_ssa
);
537 return &nir_instr_as_intrinsic(instr
)->dest
.ssa
;
538 case nir_instr_type_tex
:
539 assert(nir_instr_as_tex(instr
)->dest
.is_ssa
);
540 return &nir_instr_as_tex(instr
)->dest
.ssa
;
542 unreachable("We never ask for any of these");
547 cmp_func(const void *data1
, const void *data2
)
549 return nir_instrs_equal(data1
, data2
);
553 nir_instr_set_create(void *mem_ctx
)
555 return _mesa_set_create(mem_ctx
, hash_instr
, cmp_func
);
559 nir_instr_set_destroy(struct set
*instr_set
)
561 _mesa_set_destroy(instr_set
, NULL
);
565 nir_instr_set_add_or_rewrite(struct set
*instr_set
, nir_instr
*instr
)
567 if (!instr_can_rewrite(instr
))
570 struct set_entry
*entry
= _mesa_set_search(instr_set
, instr
);
572 nir_ssa_def
*def
= nir_instr_get_dest_ssa_def(instr
);
573 nir_instr
*match
= (nir_instr
*) entry
->key
;
574 nir_ssa_def
*new_def
= nir_instr_get_dest_ssa_def(match
);
576 /* It's safe to replace an exact instruction with an inexact one as
577 * long as we make it exact. If we got here, the two instructions are
578 * exactly identical in every other way so, once we've set the exact
579 * bit, they are the same.
581 if (instr
->type
== nir_instr_type_alu
&& nir_instr_as_alu(instr
)->exact
)
582 nir_instr_as_alu(match
)->exact
= true;
584 nir_ssa_def_rewrite_uses(def
, nir_src_for_ssa(new_def
));
588 _mesa_set_add(instr_set
, instr
);
593 nir_instr_set_remove(struct set
*instr_set
, nir_instr
*instr
)
595 if (!instr_can_rewrite(instr
))
598 struct set_entry
*entry
= _mesa_set_search(instr_set
, instr
);
600 _mesa_set_remove(instr_set
, entry
);