src/compiler/nir/nir_instr_set.c

   1 /*
   2  * Copyright © 2014 Connor Abbott
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "nir_instr_set.h"
  25 #include "nir_vla.h"
  26 #include "util/half_float.h"
  27
  28 #define HASH(hash, data) _mesa_fnv32_1a_accumulate((hash), (data))
  29
  30 static uint32_t
  31 hash_src(uint32_t hash, const nir_src *src)
  32 {
  33    assert(src->is_ssa);
  34    hash = HASH(hash, src->ssa);
  35    return hash;
  36 }
  37
  38 static uint32_t
  39 hash_alu_src(uint32_t hash, const nir_alu_src *src, unsigned num_components)
  40 {
  41    hash = HASH(hash, src->abs);
  42    hash = HASH(hash, src->negate);
  43
  44    for (unsigned i = 0; i < num_components; i++)
  45       hash = HASH(hash, src->swizzle[i]);
  46
  47    hash = hash_src(hash, &src->src);
  48    return hash;
  49 }
  50
  51 static uint32_t
  52 hash_alu(uint32_t hash, const nir_alu_instr *instr)
  53 {
  54    hash = HASH(hash, instr->op);
  55
  56    /* We explicitly don't hash instr->exact. */
  57    uint8_t flags = instr->no_signed_wrap |
  58                    instr->no_unsigned_wrap << 1;
  59    hash = HASH(hash, flags);
  60
  61    hash = HASH(hash, instr->dest.dest.ssa.num_components);
  62    hash = HASH(hash, instr->dest.dest.ssa.bit_size);
  63
  64    if (nir_op_infos[instr->op].algebraic_properties & NIR_OP_IS_2SRC_COMMUTATIVE) {
  65       assert(nir_op_infos[instr->op].num_inputs >= 2);
  66
  67       uint32_t hash0 = hash_alu_src(hash, &instr->src[0],
  68                                     nir_ssa_alu_instr_src_components(instr, 0));
  69       uint32_t hash1 = hash_alu_src(hash, &instr->src[1],
  70                                     nir_ssa_alu_instr_src_components(instr, 1));
  71       /* For commutative operations, we need some commutative way of
  72        * combining the hashes.  One option would be to XOR them but that
  73        * means that anything with two identical sources will hash to 0 and
  74        * that's common enough we probably don't want the guaranteed
  75        * collision.  Either addition or multiplication will also work.
  76        */
  77       hash = hash0 * hash1;
  78
  79       for (unsigned i = 2; i < nir_op_infos[instr->op].num_inputs; i++) {
  80          hash = hash_alu_src(hash, &instr->src[i],
  81                              nir_ssa_alu_instr_src_components(instr, i));
  82       }
  83    } else {
  84       for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
  85          hash = hash_alu_src(hash, &instr->src[i],
  86                              nir_ssa_alu_instr_src_components(instr, i));
  87       }
  88    }
  89
  90    return hash;
  91 }
  92
  93 static uint32_t
  94 hash_deref(uint32_t hash, const nir_deref_instr *instr)
  95 {
  96    hash = HASH(hash, instr->deref_type);
  97    hash = HASH(hash, instr->mode);
  98    hash = HASH(hash, instr->type);
  99
 100    if (instr->deref_type == nir_deref_type_var)
 101       return HASH(hash, instr->var);
 102
 103    hash = hash_src(hash, &instr->parent);
 104
 105    switch (instr->deref_type) {
 106    case nir_deref_type_struct:
 107       hash = HASH(hash, instr->strct.index);
 108       break;
 109
 110    case nir_deref_type_array:
 111    case nir_deref_type_ptr_as_array:
 112       hash = hash_src(hash, &instr->arr.index);
 113       break;
 114
 115    case nir_deref_type_cast:
 116       hash = HASH(hash, instr->cast.ptr_stride);
 117       break;
 118
 119    case nir_deref_type_var:
 120    case nir_deref_type_array_wildcard:
 121       /* Nothing to do */
 122       break;
 123
 124    default:
 125       unreachable("Invalid instruction deref type");
 126    }
 127
 128    return hash;
 129 }
 130
 131 static uint32_t
 132 hash_load_const(uint32_t hash, const nir_load_const_instr *instr)
 133 {
 134    hash = HASH(hash, instr->def.num_components);
 135
 136    if (instr->def.bit_size == 1) {
 137       for (unsigned i = 0; i < instr->def.num_components; i++) {
 138          uint8_t b = instr->value[i].b;
 139          hash = HASH(hash, b);
 140       }
 141    } else {
 142       unsigned size = instr->def.num_components * sizeof(*instr->value);
 143       hash = _mesa_fnv32_1a_accumulate_block(hash, instr->value, size);
 144    }
 145
 146    return hash;
 147 }
 148
 149 static int
 150 cmp_phi_src(const void *data1, const void *data2)
 151 {
 152    nir_phi_src *src1 = *(nir_phi_src **)data1;
 153    nir_phi_src *src2 = *(nir_phi_src **)data2;
 154    return src1->pred - src2->pred;
 155 }
 156
 157 static uint32_t
 158 hash_phi(uint32_t hash, const nir_phi_instr *instr)
 159 {
 160    hash = HASH(hash, instr->instr.block);
 161
 162    /* sort sources by predecessor, since the order shouldn't matter */
 163    unsigned num_preds = instr->instr.block->predecessors->entries;
 164    NIR_VLA(nir_phi_src *, srcs, num_preds);
 165    unsigned i = 0;
 166    nir_foreach_phi_src(src, instr) {
 167       srcs[i++] = src;
 168    }
 169
 170    qsort(srcs, num_preds, sizeof(nir_phi_src *), cmp_phi_src);
 171
 172    for (i = 0; i < num_preds; i++) {
 173       hash = hash_src(hash, &srcs[i]->src);
 174       hash = HASH(hash, srcs[i]->pred);
 175    }
 176
 177    return hash;
 178 }
 179
 180 static uint32_t
 181 hash_intrinsic(uint32_t hash, const nir_intrinsic_instr *instr)
 182 {
 183    const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
 184    hash = HASH(hash, instr->intrinsic);
 185
 186    if (info->has_dest) {
 187       hash = HASH(hash, instr->dest.ssa.num_components);
 188       hash = HASH(hash, instr->dest.ssa.bit_size);
 189    }
 190
 191    hash = _mesa_fnv32_1a_accumulate_block(hash, instr->const_index,
 192                                           info->num_indices
 193                                              * sizeof(instr->const_index[0]));
 194    return hash;
 195 }
 196
 197 static uint32_t
 198 hash_tex(uint32_t hash, const nir_tex_instr *instr)
 199 {
 200    hash = HASH(hash, instr->op);
 201    hash = HASH(hash, instr->num_srcs);
 202
 203    for (unsigned i = 0; i < instr->num_srcs; i++) {
 204       hash = HASH(hash, instr->src[i].src_type);
 205       hash = hash_src(hash, &instr->src[i].src);
 206    }
 207
 208    hash = HASH(hash, instr->coord_components);
 209    hash = HASH(hash, instr->sampler_dim);
 210    hash = HASH(hash, instr->is_array);
 211    hash = HASH(hash, instr->is_shadow);
 212    hash = HASH(hash, instr->is_new_style_shadow);
 213    unsigned component = instr->component;
 214    hash = HASH(hash, component);
 215    for (unsigned i = 0; i < 4; ++i)
 216       for (unsigned j = 0; j < 2; ++j)
 217          hash = HASH(hash, instr->tg4_offsets[i][j]);
 218    hash = HASH(hash, instr->texture_index);
 219    hash = HASH(hash, instr->texture_array_size);
 220    hash = HASH(hash, instr->sampler_index);
 221
 222    return hash;
 223 }
 224
 225 /* Computes a hash of an instruction for use in a hash table. Note that this
 226  * will only work for instructions where instr_can_rewrite() returns true, and
 227  * it should return identical hashes for two instructions that are the same
 228  * according nir_instrs_equal().
 229  */
 230
 231 static uint32_t
 232 hash_instr(const void *data)
 233 {
 234    const nir_instr *instr = data;
 235    uint32_t hash = _mesa_fnv32_1a_offset_bias;
 236
 237    switch (instr->type) {
 238    case nir_instr_type_alu:
 239       hash = hash_alu(hash, nir_instr_as_alu(instr));
 240       break;
 241    case nir_instr_type_deref:
 242       hash = hash_deref(hash, nir_instr_as_deref(instr));
 243       break;
 244    case nir_instr_type_load_const:
 245       hash = hash_load_const(hash, nir_instr_as_load_const(instr));
 246       break;
 247    case nir_instr_type_phi:
 248       hash = hash_phi(hash, nir_instr_as_phi(instr));
 249       break;
 250    case nir_instr_type_intrinsic:
 251       hash = hash_intrinsic(hash, nir_instr_as_intrinsic(instr));
 252       break;
 253    case nir_instr_type_tex:
 254       hash = hash_tex(hash, nir_instr_as_tex(instr));
 255       break;
 256    default:
 257       unreachable("Invalid instruction type");
 258    }
 259
 260    return hash;
 261 }
 262
 263 bool
 264 nir_srcs_equal(nir_src src1, nir_src src2)
 265 {
 266    if (src1.is_ssa) {
 267       if (src2.is_ssa) {
 268          return src1.ssa == src2.ssa;
 269       } else {
 270          return false;
 271       }
 272    } else {
 273       if (src2.is_ssa) {
 274          return false;
 275       } else {
 276          if ((src1.reg.indirect == NULL) != (src2.reg.indirect == NULL))
 277             return false;
 278
 279          if (src1.reg.indirect) {
 280             if (!nir_srcs_equal(*src1.reg.indirect, *src2.reg.indirect))
 281                return false;
 282          }
 283
 284          return src1.reg.reg == src2.reg.reg &&
 285                 src1.reg.base_offset == src2.reg.base_offset;
 286       }
 287    }
 288 }
 289
 290 /**
 291  * If the \p s is an SSA value that was generated by a negation instruction,
 292  * that instruction is returned as a \c nir_alu_instr.  Otherwise \c NULL is
 293  * returned.
 294  */
 295 static nir_alu_instr *
 296 get_neg_instr(nir_src s)
 297 {
 298    nir_alu_instr *alu = nir_src_as_alu_instr(s);
 299
 300    return alu != NULL && (alu->op == nir_op_fneg || alu->op == nir_op_ineg)
 301           ? alu : NULL;
 302 }
 303
 304 bool
 305 nir_const_value_negative_equal(nir_const_value c1,
 306                                nir_const_value c2,
 307                                nir_alu_type full_type)
 308 {
 309    assert(nir_alu_type_get_base_type(full_type) != nir_type_invalid);
 310    assert(nir_alu_type_get_type_size(full_type) != 0);
 311
 312    switch (full_type) {
 313    case nir_type_float16:
 314       return _mesa_half_to_float(c1.u16) == -_mesa_half_to_float(c2.u16);
 315
 316    case nir_type_float32:
 317       return c1.f32 == -c2.f32;
 318
 319    case nir_type_float64:
 320       return c1.f64 == -c2.f64;
 321
 322    case nir_type_int8:
 323    case nir_type_uint8:
 324       return c1.i8 == -c2.i8;
 325
 326    case nir_type_int16:
 327    case nir_type_uint16:
 328       return c1.i16 == -c2.i16;
 329
 330    case nir_type_int32:
 331    case nir_type_uint32:
 332       return c1.i32 == -c2.i32;
 333
 334    case nir_type_int64:
 335    case nir_type_uint64:
 336       return c1.i64 == -c2.i64;
 337
 338    default:
 339       break;
 340    }
 341
 342    return false;
 343 }
 344
 345 /**
 346  * Shallow compare of ALU srcs to determine if one is the negation of the other
 347  *
 348  * This function detects cases where \p alu1 is a constant and \p alu2 is a
 349  * constant that is its negation.  It will also detect cases where \p alu2 is
 350  * an SSA value that is a \c nir_op_fneg applied to \p alu1 (and vice versa).
 351  *
 352  * This function does not detect the general case when \p alu1 and \p alu2 are
 353  * SSA values that are the negations of each other (e.g., \p alu1 represents
 354  * (a * b) and \p alu2 represents (-a * b)).
 355  */
 356 bool
 357 nir_alu_srcs_negative_equal(const nir_alu_instr *alu1,
 358                             const nir_alu_instr *alu2,
 359                             unsigned src1, unsigned src2)
 360 {
 361    if (alu1->src[src1].abs != alu2->src[src2].abs)
 362       return false;
 363
 364    bool parity = alu1->src[src1].negate != alu2->src[src2].negate;
 365
 366    /* Handling load_const instructions is tricky. */
 367
 368    const nir_const_value *const const1 =
 369       nir_src_as_const_value(alu1->src[src1].src);
 370
 371    if (const1 != NULL) {
 372       /* Assume that constant folding will eliminate source mods and unary
 373        * ops.
 374        */
 375       if (parity)
 376          return false;
 377
 378       const nir_const_value *const const2 =
 379          nir_src_as_const_value(alu2->src[src2].src);
 380
 381       if (const2 == NULL)
 382          return false;
 383
 384       if (nir_src_bit_size(alu1->src[src1].src) !=
 385           nir_src_bit_size(alu2->src[src2].src))
 386          return false;
 387
 388       /* FINISHME: Apply the swizzle? */
 389       const unsigned components = nir_ssa_alu_instr_src_components(alu1, src1);
 390       const nir_alu_type full_type = nir_op_infos[alu1->op].input_types[src1] |
 391                                      nir_src_bit_size(alu1->src[src1].src);
 392       for (unsigned i = 0; i < components; i++) {
 393          if (!nir_const_value_negative_equal(const1[i], const2[i], full_type))
 394             return false;
 395       }
 396
 397       return true;
 398    }
 399
 400    uint8_t alu1_swizzle[4] = {0};
 401    nir_src alu1_actual_src;
 402    nir_alu_instr *neg1 = get_neg_instr(alu1->src[src1].src);
 403
 404    if (neg1) {
 405       parity = !parity;
 406       alu1_actual_src = neg1->src[0].src;
 407
 408       for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(neg1, 0); i++)
 409          alu1_swizzle[i] = neg1->src[0].swizzle[i];
 410    } else {
 411       alu1_actual_src = alu1->src[src1].src;
 412
 413       for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(alu1, src1); i++)
 414          alu1_swizzle[i] = i;
 415    }
 416
 417    uint8_t alu2_swizzle[4] = {0};
 418    nir_src alu2_actual_src;
 419    nir_alu_instr *neg2 = get_neg_instr(alu2->src[src2].src);
 420
 421    if (neg2) {
 422       parity = !parity;
 423       alu2_actual_src = neg2->src[0].src;
 424
 425       for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(neg2, 0); i++)
 426          alu2_swizzle[i] = neg2->src[0].swizzle[i];
 427    } else {
 428       alu2_actual_src = alu2->src[src2].src;
 429
 430       for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(alu2, src2); i++)
 431          alu2_swizzle[i] = i;
 432    }
 433
 434    for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(alu1, src1); i++) {
 435       if (alu1_swizzle[alu1->src[src1].swizzle[i]] !=
 436           alu2_swizzle[alu2->src[src2].swizzle[i]])
 437          return false;
 438    }
 439
 440    return parity && nir_srcs_equal(alu1_actual_src, alu2_actual_src);
 441 }
 442
 443 bool
 444 nir_alu_srcs_equal(const nir_alu_instr *alu1, const nir_alu_instr *alu2,
 445                    unsigned src1, unsigned src2)
 446 {
 447    if (alu1->src[src1].abs != alu2->src[src2].abs ||
 448        alu1->src[src1].negate != alu2->src[src2].negate)
 449       return false;
 450
 451    for (unsigned i = 0; i < nir_ssa_alu_instr_src_components(alu1, src1); i++) {
 452       if (alu1->src[src1].swizzle[i] != alu2->src[src2].swizzle[i])
 453          return false;
 454    }
 455
 456    return nir_srcs_equal(alu1->src[src1].src, alu2->src[src2].src);
 457 }
 458
 459 /* Returns "true" if two instructions are equal. Note that this will only
 460  * work for the subset of instructions defined by instr_can_rewrite(). Also,
 461  * it should only return "true" for instructions that hash_instr() will return
 462  * the same hash for (ignoring collisions, of course).
 463  */
 464
 465 static bool
 466 nir_instrs_equal(const nir_instr *instr1, const nir_instr *instr2)
 467 {
 468    if (instr1->type != instr2->type)
 469       return false;
 470
 471    switch (instr1->type) {
 472    case nir_instr_type_alu: {
 473       nir_alu_instr *alu1 = nir_instr_as_alu(instr1);
 474       nir_alu_instr *alu2 = nir_instr_as_alu(instr2);
 475
 476       if (alu1->op != alu2->op)
 477          return false;
 478
 479       /* We explicitly don't compare instr->exact. */
 480
 481       if (alu1->no_signed_wrap != alu2->no_signed_wrap)
 482          return false;
 483
 484       if (alu1->no_unsigned_wrap != alu2->no_unsigned_wrap)
 485          return false;
 486
 487       /* TODO: We can probably acutally do something more inteligent such
 488        * as allowing different numbers and taking a maximum or something
 489        * here */
 490       if (alu1->dest.dest.ssa.num_components != alu2->dest.dest.ssa.num_components)
 491          return false;
 492
 493       if (alu1->dest.dest.ssa.bit_size != alu2->dest.dest.ssa.bit_size)
 494          return false;
 495
 496       if (nir_op_infos[alu1->op].algebraic_properties & NIR_OP_IS_2SRC_COMMUTATIVE) {
 497          if ((!nir_alu_srcs_equal(alu1, alu2, 0, 0) ||
 498               !nir_alu_srcs_equal(alu1, alu2, 1, 1)) &&
 499              (!nir_alu_srcs_equal(alu1, alu2, 0, 1) ||
 500               !nir_alu_srcs_equal(alu1, alu2, 1, 0)))
 501             return false;
 502
 503          for (unsigned i = 2; i < nir_op_infos[alu1->op].num_inputs; i++) {
 504             if (!nir_alu_srcs_equal(alu1, alu2, i, i))
 505                return false;
 506          }
 507       } else {
 508          for (unsigned i = 0; i < nir_op_infos[alu1->op].num_inputs; i++) {
 509             if (!nir_alu_srcs_equal(alu1, alu2, i, i))
 510                return false;
 511          }
 512       }
 513       return true;
 514    }
 515    case nir_instr_type_deref: {
 516       nir_deref_instr *deref1 = nir_instr_as_deref(instr1);
 517       nir_deref_instr *deref2 = nir_instr_as_deref(instr2);
 518
 519       if (deref1->deref_type != deref2->deref_type ||
 520           deref1->mode != deref2->mode ||
 521           deref1->type != deref2->type)
 522          return false;
 523
 524       if (deref1->deref_type == nir_deref_type_var)
 525          return deref1->var == deref2->var;
 526
 527       if (!nir_srcs_equal(deref1->parent, deref2->parent))
 528          return false;
 529
 530       switch (deref1->deref_type) {
 531       case nir_deref_type_struct:
 532          if (deref1->strct.index != deref2->strct.index)
 533             return false;
 534          break;
 535
 536       case nir_deref_type_array:
 537       case nir_deref_type_ptr_as_array:
 538          if (!nir_srcs_equal(deref1->arr.index, deref2->arr.index))
 539             return false;
 540          break;
 541
 542       case nir_deref_type_cast:
 543          if (deref1->cast.ptr_stride != deref2->cast.ptr_stride)
 544             return false;
 545          break;
 546
 547       case nir_deref_type_var:
 548       case nir_deref_type_array_wildcard:
 549          /* Nothing to do */
 550          break;
 551
 552       default:
 553          unreachable("Invalid instruction deref type");
 554       }
 555       return true;
 556    }
 557    case nir_instr_type_tex: {
 558       nir_tex_instr *tex1 = nir_instr_as_tex(instr1);
 559       nir_tex_instr *tex2 = nir_instr_as_tex(instr2);
 560
 561       if (tex1->op != tex2->op)
 562          return false;
 563
 564       if (tex1->num_srcs != tex2->num_srcs)
 565          return false;
 566       for (unsigned i = 0; i < tex1->num_srcs; i++) {
 567          if (tex1->src[i].src_type != tex2->src[i].src_type ||
 568              !nir_srcs_equal(tex1->src[i].src, tex2->src[i].src)) {
 569             return false;
 570          }
 571       }
 572
 573       if (tex1->coord_components != tex2->coord_components ||
 574           tex1->sampler_dim != tex2->sampler_dim ||
 575           tex1->is_array != tex2->is_array ||
 576           tex1->is_shadow != tex2->is_shadow ||
 577           tex1->is_new_style_shadow != tex2->is_new_style_shadow ||
 578           tex1->component != tex2->component ||
 579          tex1->texture_index != tex2->texture_index ||
 580          tex1->texture_array_size != tex2->texture_array_size ||
 581          tex1->sampler_index != tex2->sampler_index) {
 582          return false;
 583       }
 584
 585       if (memcmp(tex1->tg4_offsets, tex2->tg4_offsets,
 586                  sizeof(tex1->tg4_offsets)))
 587          return false;
 588
 589       return true;
 590    }
 591    case nir_instr_type_load_const: {
 592       nir_load_const_instr *load1 = nir_instr_as_load_const(instr1);
 593       nir_load_const_instr *load2 = nir_instr_as_load_const(instr2);
 594
 595       if (load1->def.num_components != load2->def.num_components)
 596          return false;
 597
 598       if (load1->def.bit_size != load2->def.bit_size)
 599          return false;
 600
 601       if (load1->def.bit_size == 1) {
 602          for (unsigned i = 0; i < load1->def.num_components; ++i) {
 603             if (load1->value[i].b != load2->value[i].b)
 604                return false;
 605          }
 606       } else {
 607          unsigned size = load1->def.num_components * sizeof(*load1->value);
 608          if (memcmp(load1->value, load2->value, size) != 0)
 609             return false;
 610       }
 611       return true;
 612    }
 613    case nir_instr_type_phi: {
 614       nir_phi_instr *phi1 = nir_instr_as_phi(instr1);
 615       nir_phi_instr *phi2 = nir_instr_as_phi(instr2);
 616
 617       if (phi1->instr.block != phi2->instr.block)
 618          return false;
 619
 620       nir_foreach_phi_src(src1, phi1) {
 621          nir_foreach_phi_src(src2, phi2) {
 622             if (src1->pred == src2->pred) {
 623                if (!nir_srcs_equal(src1->src, src2->src))
 624                   return false;
 625
 626                break;
 627             }
 628          }
 629       }
 630
 631       return true;
 632    }
 633    case nir_instr_type_intrinsic: {
 634       nir_intrinsic_instr *intrinsic1 = nir_instr_as_intrinsic(instr1);
 635       nir_intrinsic_instr *intrinsic2 = nir_instr_as_intrinsic(instr2);
 636       const nir_intrinsic_info *info =
 637          &nir_intrinsic_infos[intrinsic1->intrinsic];
 638
 639       if (intrinsic1->intrinsic != intrinsic2->intrinsic ||
 640           intrinsic1->num_components != intrinsic2->num_components)
 641          return false;
 642
 643       if (info->has_dest && intrinsic1->dest.ssa.num_components !=
 644                             intrinsic2->dest.ssa.num_components)
 645          return false;
 646
 647       if (info->has_dest && intrinsic1->dest.ssa.bit_size !=
 648                             intrinsic2->dest.ssa.bit_size)
 649          return false;
 650
 651       for (unsigned i = 0; i < info->num_srcs; i++) {
 652          if (!nir_srcs_equal(intrinsic1->src[i], intrinsic2->src[i]))
 653             return false;
 654       }
 655
 656       for (unsigned i = 0; i < info->num_indices; i++) {
 657          if (intrinsic1->const_index[i] != intrinsic2->const_index[i])
 658             return false;
 659       }
 660
 661       return true;
 662    }
 663    case nir_instr_type_call:
 664    case nir_instr_type_jump:
 665    case nir_instr_type_ssa_undef:
 666    case nir_instr_type_parallel_copy:
 667    default:
 668       unreachable("Invalid instruction type");
 669    }
 670
 671    unreachable("All cases in the above switch should return");
 672 }
 673
 674 static bool
 675 src_is_ssa(nir_src *src, void *data)
 676 {
 677    (void) data;
 678    return src->is_ssa;
 679 }
 680
 681 static bool
 682 dest_is_ssa(nir_dest *dest, void *data)
 683 {
 684    (void) data;
 685    return dest->is_ssa;
 686 }
 687
 688 static inline bool
 689 instr_each_src_and_dest_is_ssa(nir_instr *instr)
 690 {
 691    if (!nir_foreach_dest(instr, dest_is_ssa, NULL) ||
 692        !nir_foreach_src(instr, src_is_ssa, NULL))
 693       return false;
 694
 695    return true;
 696 }
 697
 698 /* This function determines if uses of an instruction can safely be rewritten
 699  * to use another identical instruction instead. Note that this function must
 700  * be kept in sync with hash_instr() and nir_instrs_equal() -- only
 701  * instructions that pass this test will be handed on to those functions, and
 702  * conversely they must handle everything that this function returns true for.
 703  */
 704
 705 static bool
 706 instr_can_rewrite(nir_instr *instr)
 707 {
 708    /* We only handle SSA. */
 709    assert(instr_each_src_and_dest_is_ssa(instr));
 710
 711    switch (instr->type) {
 712    case nir_instr_type_alu:
 713    case nir_instr_type_deref:
 714    case nir_instr_type_tex:
 715    case nir_instr_type_load_const:
 716    case nir_instr_type_phi:
 717       return true;
 718    case nir_instr_type_intrinsic:
 719       return nir_intrinsic_can_reorder(nir_instr_as_intrinsic(instr));
 720    case nir_instr_type_call:
 721    case nir_instr_type_jump:
 722    case nir_instr_type_ssa_undef:
 723       return false;
 724    case nir_instr_type_parallel_copy:
 725    default:
 726       unreachable("Invalid instruction type");
 727    }
 728
 729    return false;
 730 }
 731
 732 static nir_ssa_def *
 733 nir_instr_get_dest_ssa_def(nir_instr *instr)
 734 {
 735    switch (instr->type) {
 736    case nir_instr_type_alu:
 737       assert(nir_instr_as_alu(instr)->dest.dest.is_ssa);
 738       return &nir_instr_as_alu(instr)->dest.dest.ssa;
 739    case nir_instr_type_deref:
 740       assert(nir_instr_as_deref(instr)->dest.is_ssa);
 741       return &nir_instr_as_deref(instr)->dest.ssa;
 742    case nir_instr_type_load_const:
 743       return &nir_instr_as_load_const(instr)->def;
 744    case nir_instr_type_phi:
 745       assert(nir_instr_as_phi(instr)->dest.is_ssa);
 746       return &nir_instr_as_phi(instr)->dest.ssa;
 747    case nir_instr_type_intrinsic:
 748       assert(nir_instr_as_intrinsic(instr)->dest.is_ssa);
 749       return &nir_instr_as_intrinsic(instr)->dest.ssa;
 750    case nir_instr_type_tex:
 751       assert(nir_instr_as_tex(instr)->dest.is_ssa);
 752       return &nir_instr_as_tex(instr)->dest.ssa;
 753    default:
 754       unreachable("We never ask for any of these");
 755    }
 756 }
 757
 758 static bool
 759 cmp_func(const void *data1, const void *data2)
 760 {
 761    return nir_instrs_equal(data1, data2);
 762 }
 763
 764 struct set *
 765 nir_instr_set_create(void *mem_ctx)
 766 {
 767    return _mesa_set_create(mem_ctx, hash_instr, cmp_func);
 768 }
 769
 770 void
 771 nir_instr_set_destroy(struct set *instr_set)
 772 {
 773    _mesa_set_destroy(instr_set, NULL);
 774 }
 775
 776 bool
 777 nir_instr_set_add_or_rewrite(struct set *instr_set, nir_instr *instr)
 778 {
 779    if (!instr_can_rewrite(instr))
 780       return false;
 781
 782    struct set_entry *e = _mesa_set_search_or_add(instr_set, instr);
 783    nir_instr *match = (nir_instr *) e->key;
 784    if (match != instr) {
 785       nir_ssa_def *def = nir_instr_get_dest_ssa_def(instr);
 786       nir_ssa_def *new_def = nir_instr_get_dest_ssa_def(match);
 787
 788       /* It's safe to replace an exact instruction with an inexact one as
 789        * long as we make it exact.  If we got here, the two instructions are
 790        * exactly identical in every other way so, once we've set the exact
 791        * bit, they are the same.
 792        */
 793       if (instr->type == nir_instr_type_alu && nir_instr_as_alu(instr)->exact)
 794          nir_instr_as_alu(match)->exact = true;
 795
 796       nir_ssa_def_rewrite_uses(def, nir_src_for_ssa(new_def));
 797       return true;
 798    }
 799
 800    return false;
 801 }
 802
 803 void
 804 nir_instr_set_remove(struct set *instr_set, nir_instr *instr)
 805 {
 806    if (!instr_can_rewrite(instr))
 807       return;
 808
 809    struct set_entry *entry = _mesa_set_search(instr_set, instr);
 810    if (entry)
 811       _mesa_set_remove(instr_set, entry);
 812 }
 813