2 * Copyright © 2014 Connor Abbott
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "nir_instr_set.h"
26 #include "util/half_float.h"
28 #define HASH(hash, data) _mesa_fnv32_1a_accumulate((hash), (data))
31 hash_src(uint32_t hash
, const nir_src
*src
)
34 hash
= HASH(hash
, src
->ssa
);
39 hash_alu_src(uint32_t hash
, const nir_alu_src
*src
, unsigned num_components
)
41 hash
= HASH(hash
, src
->abs
);
42 hash
= HASH(hash
, src
->negate
);
44 for (unsigned i
= 0; i
< num_components
; i
++)
45 hash
= HASH(hash
, src
->swizzle
[i
]);
47 hash
= hash_src(hash
, &src
->src
);
52 hash_alu(uint32_t hash
, const nir_alu_instr
*instr
)
54 hash
= HASH(hash
, instr
->op
);
55 hash
= HASH(hash
, instr
->dest
.dest
.ssa
.num_components
);
56 hash
= HASH(hash
, instr
->dest
.dest
.ssa
.bit_size
);
57 /* We explicitly don't hash instr->dest.dest.exact */
59 if (nir_op_infos
[instr
->op
].algebraic_properties
& NIR_OP_IS_COMMUTATIVE
) {
60 assert(nir_op_infos
[instr
->op
].num_inputs
== 2);
61 uint32_t hash0
= hash_alu_src(hash
, &instr
->src
[0],
62 nir_ssa_alu_instr_src_components(instr
, 0));
63 uint32_t hash1
= hash_alu_src(hash
, &instr
->src
[1],
64 nir_ssa_alu_instr_src_components(instr
, 1));
65 /* For commutative operations, we need some commutative way of
66 * combining the hashes. One option would be to XOR them but that
67 * means that anything with two identical sources will hash to 0 and
68 * that's common enough we probably don't want the guaranteed
69 * collision. Either addition or multiplication will also work.
73 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
74 hash
= hash_alu_src(hash
, &instr
->src
[i
],
75 nir_ssa_alu_instr_src_components(instr
, i
));
83 hash_deref(uint32_t hash
, const nir_deref_instr
*instr
)
85 hash
= HASH(hash
, instr
->deref_type
);
86 hash
= HASH(hash
, instr
->mode
);
87 hash
= HASH(hash
, instr
->type
);
89 if (instr
->deref_type
== nir_deref_type_var
)
90 return HASH(hash
, instr
->var
);
92 hash
= hash_src(hash
, &instr
->parent
);
94 switch (instr
->deref_type
) {
95 case nir_deref_type_struct
:
96 hash
= HASH(hash
, instr
->strct
.index
);
99 case nir_deref_type_array
:
100 case nir_deref_type_ptr_as_array
:
101 hash
= hash_src(hash
, &instr
->arr
.index
);
104 case nir_deref_type_cast
:
105 hash
= HASH(hash
, instr
->cast
.ptr_stride
);
108 case nir_deref_type_var
:
109 case nir_deref_type_array_wildcard
:
114 unreachable("Invalid instruction deref type");
121 hash_load_const(uint32_t hash
, const nir_load_const_instr
*instr
)
123 hash
= HASH(hash
, instr
->def
.num_components
);
125 if (instr
->def
.bit_size
== 1) {
126 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
127 uint8_t b
= instr
->value
.b
[i
];
128 hash
= HASH(hash
, b
);
131 unsigned size
= instr
->def
.num_components
* (instr
->def
.bit_size
/ 8);
132 hash
= _mesa_fnv32_1a_accumulate_block(hash
, instr
->value
.f32
, size
);
139 cmp_phi_src(const void *data1
, const void *data2
)
141 nir_phi_src
*src1
= *(nir_phi_src
**)data1
;
142 nir_phi_src
*src2
= *(nir_phi_src
**)data2
;
143 return src1
->pred
- src2
->pred
;
147 hash_phi(uint32_t hash
, const nir_phi_instr
*instr
)
149 hash
= HASH(hash
, instr
->instr
.block
);
151 /* sort sources by predecessor, since the order shouldn't matter */
152 unsigned num_preds
= instr
->instr
.block
->predecessors
->entries
;
153 NIR_VLA(nir_phi_src
*, srcs
, num_preds
);
155 nir_foreach_phi_src(src
, instr
) {
159 qsort(srcs
, num_preds
, sizeof(nir_phi_src
*), cmp_phi_src
);
161 for (i
= 0; i
< num_preds
; i
++) {
162 hash
= hash_src(hash
, &srcs
[i
]->src
);
163 hash
= HASH(hash
, srcs
[i
]->pred
);
170 hash_intrinsic(uint32_t hash
, const nir_intrinsic_instr
*instr
)
172 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
173 hash
= HASH(hash
, instr
->intrinsic
);
175 if (info
->has_dest
) {
176 hash
= HASH(hash
, instr
->dest
.ssa
.num_components
);
177 hash
= HASH(hash
, instr
->dest
.ssa
.bit_size
);
180 hash
= _mesa_fnv32_1a_accumulate_block(hash
, instr
->const_index
,
182 * sizeof(instr
->const_index
[0]));
187 hash_tex(uint32_t hash
, const nir_tex_instr
*instr
)
189 hash
= HASH(hash
, instr
->op
);
190 hash
= HASH(hash
, instr
->num_srcs
);
192 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
193 hash
= HASH(hash
, instr
->src
[i
].src_type
);
194 hash
= hash_src(hash
, &instr
->src
[i
].src
);
197 hash
= HASH(hash
, instr
->coord_components
);
198 hash
= HASH(hash
, instr
->sampler_dim
);
199 hash
= HASH(hash
, instr
->is_array
);
200 hash
= HASH(hash
, instr
->is_shadow
);
201 hash
= HASH(hash
, instr
->is_new_style_shadow
);
202 unsigned component
= instr
->component
;
203 hash
= HASH(hash
, component
);
204 for (unsigned i
= 0; i
< 4; ++i
)
205 for (unsigned j
= 0; j
< 2; ++j
)
206 hash
= HASH(hash
, instr
->tg4_offsets
[i
][j
]);
207 hash
= HASH(hash
, instr
->texture_index
);
208 hash
= HASH(hash
, instr
->texture_array_size
);
209 hash
= HASH(hash
, instr
->sampler_index
);
214 /* Computes a hash of an instruction for use in a hash table. Note that this
215 * will only work for instructions where instr_can_rewrite() returns true, and
216 * it should return identical hashes for two instructions that are the same
217 * according nir_instrs_equal().
221 hash_instr(const void *data
)
223 const nir_instr
*instr
= data
;
224 uint32_t hash
= _mesa_fnv32_1a_offset_bias
;
226 switch (instr
->type
) {
227 case nir_instr_type_alu
:
228 hash
= hash_alu(hash
, nir_instr_as_alu(instr
));
230 case nir_instr_type_deref
:
231 hash
= hash_deref(hash
, nir_instr_as_deref(instr
));
233 case nir_instr_type_load_const
:
234 hash
= hash_load_const(hash
, nir_instr_as_load_const(instr
));
236 case nir_instr_type_phi
:
237 hash
= hash_phi(hash
, nir_instr_as_phi(instr
));
239 case nir_instr_type_intrinsic
:
240 hash
= hash_intrinsic(hash
, nir_instr_as_intrinsic(instr
));
242 case nir_instr_type_tex
:
243 hash
= hash_tex(hash
, nir_instr_as_tex(instr
));
246 unreachable("Invalid instruction type");
253 nir_srcs_equal(nir_src src1
, nir_src src2
)
257 return src1
.ssa
== src2
.ssa
;
265 if ((src1
.reg
.indirect
== NULL
) != (src2
.reg
.indirect
== NULL
))
268 if (src1
.reg
.indirect
) {
269 if (!nir_srcs_equal(*src1
.reg
.indirect
, *src2
.reg
.indirect
))
273 return src1
.reg
.reg
== src2
.reg
.reg
&&
274 src1
.reg
.base_offset
== src2
.reg
.base_offset
;
280 * If the \p s is an SSA value that was generated by a negation instruction,
281 * that instruction is returned as a \c nir_alu_instr. Otherwise \c NULL is
284 static const struct nir_alu_instr
*
285 get_neg_instr(const nir_src
*s
)
287 const struct nir_alu_instr
*const alu
= nir_src_as_alu_instr_const(s
);
289 return alu
!= NULL
&& (alu
->op
== nir_op_fneg
|| alu
->op
== nir_op_ineg
)
294 nir_const_value_negative_equal(const nir_const_value
*c1
,
295 const nir_const_value
*c2
,
297 nir_alu_type base_type
,
300 assert(base_type
== nir_alu_type_get_base_type(base_type
));
301 assert(base_type
!= nir_type_invalid
);
303 /* This can occur for 1-bit Boolean values. */
311 for (unsigned i
= 0; i
< components
; i
++) {
312 if (_mesa_half_to_float(c1
->u16
[i
]) !=
313 -_mesa_half_to_float(c2
->u16
[i
])) {
321 for (unsigned i
= 0; i
< components
; i
++) {
322 if (c1
->f32
[i
] != -c2
->f32
[i
])
329 for (unsigned i
= 0; i
< components
; i
++) {
330 if (c1
->f64
[i
] != -c2
->f64
[i
])
337 unreachable("unknown bit size");
346 for (unsigned i
= 0; i
< components
; i
++) {
347 if (c1
->i8
[i
] != -c2
->i8
[i
])
354 for (unsigned i
= 0; i
< components
; i
++) {
355 if (c1
->i16
[i
] != -c2
->i16
[i
])
363 for (unsigned i
= 0; i
< components
; i
++) {
364 if (c1
->i32
[i
] != -c2
->i32
[i
])
371 for (unsigned i
= 0; i
< components
; i
++) {
372 if (c1
->i64
[i
] != -c2
->i64
[i
])
379 unreachable("unknown bit size");
395 * Shallow compare of ALU srcs to determine if one is the negation of the other
397 * This function detects cases where \p alu1 is a constant and \p alu2 is a
398 * constant that is its negation. It will also detect cases where \p alu2 is
399 * an SSA value that is a \c nir_op_fneg applied to \p alu1 (and vice versa).
401 * This function does not detect the general case when \p alu1 and \p alu2 are
402 * SSA values that are the negations of each other (e.g., \p alu1 represents
403 * (a * b) and \p alu2 represents (-a * b)).
406 nir_alu_srcs_negative_equal(const nir_alu_instr
*alu1
,
407 const nir_alu_instr
*alu2
,
408 unsigned src1
, unsigned src2
)
410 if (alu1
->src
[src1
].abs
!= alu2
->src
[src2
].abs
)
413 bool parity
= alu1
->src
[src1
].negate
!= alu2
->src
[src2
].negate
;
415 /* Handling load_const instructions is tricky. */
417 const nir_const_value
*const const1
=
418 nir_src_as_const_value(alu1
->src
[src1
].src
);
420 if (const1
!= NULL
) {
421 /* Assume that constant folding will eliminate source mods and unary
427 const nir_const_value
*const const2
=
428 nir_src_as_const_value(alu2
->src
[src2
].src
);
433 /* FINISHME: Apply the swizzle? */
434 return nir_const_value_negative_equal(const1
,
436 nir_ssa_alu_instr_src_components(alu1
, src1
),
437 nir_op_infos
[alu1
->op
].input_types
[src1
],
438 alu1
->dest
.dest
.ssa
.bit_size
);
441 uint8_t alu1_swizzle
[4] = {};
442 nir_src alu1_actual_src
;
443 const struct nir_alu_instr
*const neg1
= get_neg_instr(&alu1
->src
[src1
].src
);
447 alu1_actual_src
= neg1
->src
[0].src
;
449 for (unsigned i
= 0; i
< nir_ssa_alu_instr_src_components(neg1
, 0); i
++)
450 alu1_swizzle
[i
] = neg1
->src
[0].swizzle
[i
];
452 alu1_actual_src
= alu1
->src
[src1
].src
;
454 for (unsigned i
= 0; i
< nir_ssa_alu_instr_src_components(alu1
, src1
); i
++)
458 uint8_t alu2_swizzle
[4] = {};
459 nir_src alu2_actual_src
;
460 const struct nir_alu_instr
*const neg2
= get_neg_instr(&alu2
->src
[src2
].src
);
464 alu2_actual_src
= neg2
->src
[0].src
;
466 for (unsigned i
= 0; i
< nir_ssa_alu_instr_src_components(neg2
, 0); i
++)
467 alu2_swizzle
[i
] = neg2
->src
[0].swizzle
[i
];
469 alu2_actual_src
= alu2
->src
[src2
].src
;
471 for (unsigned i
= 0; i
< nir_ssa_alu_instr_src_components(alu2
, src2
); i
++)
475 for (unsigned i
= 0; i
< nir_ssa_alu_instr_src_components(alu1
, src1
); i
++) {
476 if (alu1_swizzle
[alu1
->src
[src1
].swizzle
[i
]] !=
477 alu2_swizzle
[alu2
->src
[src2
].swizzle
[i
]])
481 return parity
&& nir_srcs_equal(alu1_actual_src
, alu2_actual_src
);
485 nir_alu_srcs_equal(const nir_alu_instr
*alu1
, const nir_alu_instr
*alu2
,
486 unsigned src1
, unsigned src2
)
488 if (alu1
->src
[src1
].abs
!= alu2
->src
[src2
].abs
||
489 alu1
->src
[src1
].negate
!= alu2
->src
[src2
].negate
)
492 for (unsigned i
= 0; i
< nir_ssa_alu_instr_src_components(alu1
, src1
); i
++) {
493 if (alu1
->src
[src1
].swizzle
[i
] != alu2
->src
[src2
].swizzle
[i
])
497 return nir_srcs_equal(alu1
->src
[src1
].src
, alu2
->src
[src2
].src
);
500 /* Returns "true" if two instructions are equal. Note that this will only
501 * work for the subset of instructions defined by instr_can_rewrite(). Also,
502 * it should only return "true" for instructions that hash_instr() will return
503 * the same hash for (ignoring collisions, of course).
507 nir_instrs_equal(const nir_instr
*instr1
, const nir_instr
*instr2
)
509 if (instr1
->type
!= instr2
->type
)
512 switch (instr1
->type
) {
513 case nir_instr_type_alu
: {
514 nir_alu_instr
*alu1
= nir_instr_as_alu(instr1
);
515 nir_alu_instr
*alu2
= nir_instr_as_alu(instr2
);
517 if (alu1
->op
!= alu2
->op
)
520 /* TODO: We can probably acutally do something more inteligent such
521 * as allowing different numbers and taking a maximum or something
523 if (alu1
->dest
.dest
.ssa
.num_components
!= alu2
->dest
.dest
.ssa
.num_components
)
526 if (alu1
->dest
.dest
.ssa
.bit_size
!= alu2
->dest
.dest
.ssa
.bit_size
)
529 /* We explicitly don't hash instr->dest.dest.exact */
531 if (nir_op_infos
[alu1
->op
].algebraic_properties
& NIR_OP_IS_COMMUTATIVE
) {
532 assert(nir_op_infos
[alu1
->op
].num_inputs
== 2);
533 return (nir_alu_srcs_equal(alu1
, alu2
, 0, 0) &&
534 nir_alu_srcs_equal(alu1
, alu2
, 1, 1)) ||
535 (nir_alu_srcs_equal(alu1
, alu2
, 0, 1) &&
536 nir_alu_srcs_equal(alu1
, alu2
, 1, 0));
538 for (unsigned i
= 0; i
< nir_op_infos
[alu1
->op
].num_inputs
; i
++) {
539 if (!nir_alu_srcs_equal(alu1
, alu2
, i
, i
))
545 case nir_instr_type_deref
: {
546 nir_deref_instr
*deref1
= nir_instr_as_deref(instr1
);
547 nir_deref_instr
*deref2
= nir_instr_as_deref(instr2
);
549 if (deref1
->deref_type
!= deref2
->deref_type
||
550 deref1
->mode
!= deref2
->mode
||
551 deref1
->type
!= deref2
->type
)
554 if (deref1
->deref_type
== nir_deref_type_var
)
555 return deref1
->var
== deref2
->var
;
557 if (!nir_srcs_equal(deref1
->parent
, deref2
->parent
))
560 switch (deref1
->deref_type
) {
561 case nir_deref_type_struct
:
562 if (deref1
->strct
.index
!= deref2
->strct
.index
)
566 case nir_deref_type_array
:
567 case nir_deref_type_ptr_as_array
:
568 if (!nir_srcs_equal(deref1
->arr
.index
, deref2
->arr
.index
))
572 case nir_deref_type_cast
:
573 if (deref1
->cast
.ptr_stride
!= deref2
->cast
.ptr_stride
)
577 case nir_deref_type_var
:
578 case nir_deref_type_array_wildcard
:
583 unreachable("Invalid instruction deref type");
587 case nir_instr_type_tex
: {
588 nir_tex_instr
*tex1
= nir_instr_as_tex(instr1
);
589 nir_tex_instr
*tex2
= nir_instr_as_tex(instr2
);
591 if (tex1
->op
!= tex2
->op
)
594 if (tex1
->num_srcs
!= tex2
->num_srcs
)
596 for (unsigned i
= 0; i
< tex1
->num_srcs
; i
++) {
597 if (tex1
->src
[i
].src_type
!= tex2
->src
[i
].src_type
||
598 !nir_srcs_equal(tex1
->src
[i
].src
, tex2
->src
[i
].src
)) {
603 if (tex1
->coord_components
!= tex2
->coord_components
||
604 tex1
->sampler_dim
!= tex2
->sampler_dim
||
605 tex1
->is_array
!= tex2
->is_array
||
606 tex1
->is_shadow
!= tex2
->is_shadow
||
607 tex1
->is_new_style_shadow
!= tex2
->is_new_style_shadow
||
608 tex1
->component
!= tex2
->component
||
609 tex1
->texture_index
!= tex2
->texture_index
||
610 tex1
->texture_array_size
!= tex2
->texture_array_size
||
611 tex1
->sampler_index
!= tex2
->sampler_index
) {
615 if (memcmp(tex1
->tg4_offsets
, tex2
->tg4_offsets
,
616 sizeof(tex1
->tg4_offsets
)))
621 case nir_instr_type_load_const
: {
622 nir_load_const_instr
*load1
= nir_instr_as_load_const(instr1
);
623 nir_load_const_instr
*load2
= nir_instr_as_load_const(instr2
);
625 if (load1
->def
.num_components
!= load2
->def
.num_components
)
628 if (load1
->def
.bit_size
!= load2
->def
.bit_size
)
631 if (load1
->def
.bit_size
== 1) {
632 unsigned size
= load1
->def
.num_components
* sizeof(bool);
633 return memcmp(load1
->value
.b
, load2
->value
.b
, size
) == 0;
635 unsigned size
= load1
->def
.num_components
* (load1
->def
.bit_size
/ 8);
636 return memcmp(load1
->value
.f32
, load2
->value
.f32
, size
) == 0;
639 case nir_instr_type_phi
: {
640 nir_phi_instr
*phi1
= nir_instr_as_phi(instr1
);
641 nir_phi_instr
*phi2
= nir_instr_as_phi(instr2
);
643 if (phi1
->instr
.block
!= phi2
->instr
.block
)
646 nir_foreach_phi_src(src1
, phi1
) {
647 nir_foreach_phi_src(src2
, phi2
) {
648 if (src1
->pred
== src2
->pred
) {
649 if (!nir_srcs_equal(src1
->src
, src2
->src
))
659 case nir_instr_type_intrinsic
: {
660 nir_intrinsic_instr
*intrinsic1
= nir_instr_as_intrinsic(instr1
);
661 nir_intrinsic_instr
*intrinsic2
= nir_instr_as_intrinsic(instr2
);
662 const nir_intrinsic_info
*info
=
663 &nir_intrinsic_infos
[intrinsic1
->intrinsic
];
665 if (intrinsic1
->intrinsic
!= intrinsic2
->intrinsic
||
666 intrinsic1
->num_components
!= intrinsic2
->num_components
)
669 if (info
->has_dest
&& intrinsic1
->dest
.ssa
.num_components
!=
670 intrinsic2
->dest
.ssa
.num_components
)
673 if (info
->has_dest
&& intrinsic1
->dest
.ssa
.bit_size
!=
674 intrinsic2
->dest
.ssa
.bit_size
)
677 for (unsigned i
= 0; i
< info
->num_srcs
; i
++) {
678 if (!nir_srcs_equal(intrinsic1
->src
[i
], intrinsic2
->src
[i
]))
682 for (unsigned i
= 0; i
< info
->num_indices
; i
++) {
683 if (intrinsic1
->const_index
[i
] != intrinsic2
->const_index
[i
])
689 case nir_instr_type_call
:
690 case nir_instr_type_jump
:
691 case nir_instr_type_ssa_undef
:
692 case nir_instr_type_parallel_copy
:
694 unreachable("Invalid instruction type");
697 unreachable("All cases in the above switch should return");
701 src_is_ssa(nir_src
*src
, void *data
)
708 dest_is_ssa(nir_dest
*dest
, void *data
)
715 instr_each_src_and_dest_is_ssa(nir_instr
*instr
)
717 if (!nir_foreach_dest(instr
, dest_is_ssa
, NULL
) ||
718 !nir_foreach_src(instr
, src_is_ssa
, NULL
))
724 /* This function determines if uses of an instruction can safely be rewritten
725 * to use another identical instruction instead. Note that this function must
726 * be kept in sync with hash_instr() and nir_instrs_equal() -- only
727 * instructions that pass this test will be handed on to those functions, and
728 * conversely they must handle everything that this function returns true for.
732 instr_can_rewrite(nir_instr
*instr
)
734 /* We only handle SSA. */
735 assert(instr_each_src_and_dest_is_ssa(instr
));
737 switch (instr
->type
) {
738 case nir_instr_type_alu
:
739 case nir_instr_type_deref
:
740 case nir_instr_type_tex
:
741 case nir_instr_type_load_const
:
742 case nir_instr_type_phi
:
744 case nir_instr_type_intrinsic
: {
745 const nir_intrinsic_info
*info
=
746 &nir_intrinsic_infos
[nir_instr_as_intrinsic(instr
)->intrinsic
];
747 return (info
->flags
& NIR_INTRINSIC_CAN_ELIMINATE
) &&
748 (info
->flags
& NIR_INTRINSIC_CAN_REORDER
);
750 case nir_instr_type_call
:
751 case nir_instr_type_jump
:
752 case nir_instr_type_ssa_undef
:
754 case nir_instr_type_parallel_copy
:
756 unreachable("Invalid instruction type");
763 nir_instr_get_dest_ssa_def(nir_instr
*instr
)
765 switch (instr
->type
) {
766 case nir_instr_type_alu
:
767 assert(nir_instr_as_alu(instr
)->dest
.dest
.is_ssa
);
768 return &nir_instr_as_alu(instr
)->dest
.dest
.ssa
;
769 case nir_instr_type_deref
:
770 assert(nir_instr_as_deref(instr
)->dest
.is_ssa
);
771 return &nir_instr_as_deref(instr
)->dest
.ssa
;
772 case nir_instr_type_load_const
:
773 return &nir_instr_as_load_const(instr
)->def
;
774 case nir_instr_type_phi
:
775 assert(nir_instr_as_phi(instr
)->dest
.is_ssa
);
776 return &nir_instr_as_phi(instr
)->dest
.ssa
;
777 case nir_instr_type_intrinsic
:
778 assert(nir_instr_as_intrinsic(instr
)->dest
.is_ssa
);
779 return &nir_instr_as_intrinsic(instr
)->dest
.ssa
;
780 case nir_instr_type_tex
:
781 assert(nir_instr_as_tex(instr
)->dest
.is_ssa
);
782 return &nir_instr_as_tex(instr
)->dest
.ssa
;
784 unreachable("We never ask for any of these");
789 cmp_func(const void *data1
, const void *data2
)
791 return nir_instrs_equal(data1
, data2
);
795 nir_instr_set_create(void *mem_ctx
)
797 return _mesa_set_create(mem_ctx
, hash_instr
, cmp_func
);
801 nir_instr_set_destroy(struct set
*instr_set
)
803 _mesa_set_destroy(instr_set
, NULL
);
807 nir_instr_set_add_or_rewrite(struct set
*instr_set
, nir_instr
*instr
)
809 if (!instr_can_rewrite(instr
))
812 uint32_t hash
= hash_instr(instr
);
813 struct set_entry
*e
= _mesa_set_search_pre_hashed(instr_set
, hash
, instr
);
815 nir_ssa_def
*def
= nir_instr_get_dest_ssa_def(instr
);
816 nir_instr
*match
= (nir_instr
*) e
->key
;
817 nir_ssa_def
*new_def
= nir_instr_get_dest_ssa_def(match
);
819 /* It's safe to replace an exact instruction with an inexact one as
820 * long as we make it exact. If we got here, the two instructions are
821 * exactly identical in every other way so, once we've set the exact
822 * bit, they are the same.
824 if (instr
->type
== nir_instr_type_alu
&& nir_instr_as_alu(instr
)->exact
)
825 nir_instr_as_alu(match
)->exact
= true;
827 nir_ssa_def_rewrite_uses(def
, nir_src_for_ssa(new_def
));
831 _mesa_set_add_pre_hashed(instr_set
, hash
, instr
);
836 nir_instr_set_remove(struct set
*instr_set
, nir_instr
*instr
)
838 if (!instr_can_rewrite(instr
))
841 struct set_entry
*entry
= _mesa_set_search(instr_set
, instr
);
843 _mesa_set_remove(instr_set
, entry
);