2 * Copyright © 2018 Intel Corporation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "nir_builder.h"
28 assert_ssa_def_is_not_1bit(nir_ssa_def
*def
, UNUSED
void *unused
)
30 assert(def
->bit_size
> 1);
35 rewrite_1bit_ssa_def_to_32bit(nir_ssa_def
*def
, void *_progress
)
37 bool *progress
= _progress
;
38 if (def
->bit_size
== 1) {
46 lower_alu_instr(nir_builder
*b
, nir_alu_instr
*alu
)
48 const nir_op_info
*op_info
= &nir_op_infos
[alu
->op
];
50 b
->cursor
= nir_before_instr(&alu
->instr
);
52 /* Replacement SSA value */
53 nir_ssa_def
*rep
= NULL
;
59 /* These we expect to have booleans but the opcode doesn't change */
62 case nir_op_b2f32
: alu
->op
= nir_op_mov
; break;
63 case nir_op_b2i32
: alu
->op
= nir_op_mov
; break;
66 rep
= nir_sne(b
, nir_ssa_for_alu_src(b
, alu
, 0),
70 case nir_op_flt
: alu
->op
= nir_op_slt
; break;
71 case nir_op_fge
: alu
->op
= nir_op_sge
; break;
72 case nir_op_feq
: alu
->op
= nir_op_seq
; break;
73 case nir_op_fne
: alu
->op
= nir_op_sne
; break;
74 case nir_op_ilt
: alu
->op
= nir_op_slt
; break;
75 case nir_op_ige
: alu
->op
= nir_op_sge
; break;
76 case nir_op_ieq
: alu
->op
= nir_op_seq
; break;
77 case nir_op_ine
: alu
->op
= nir_op_sne
; break;
78 case nir_op_ult
: alu
->op
= nir_op_slt
; break;
79 case nir_op_uge
: alu
->op
= nir_op_sge
; break;
81 case nir_op_ball_fequal2
: alu
->op
= nir_op_fall_equal2
; break;
82 case nir_op_ball_fequal3
: alu
->op
= nir_op_fall_equal3
; break;
83 case nir_op_ball_fequal4
: alu
->op
= nir_op_fall_equal4
; break;
84 case nir_op_bany_fnequal2
: alu
->op
= nir_op_fany_nequal2
; break;
85 case nir_op_bany_fnequal3
: alu
->op
= nir_op_fany_nequal3
; break;
86 case nir_op_bany_fnequal4
: alu
->op
= nir_op_fany_nequal4
; break;
87 case nir_op_ball_iequal2
: alu
->op
= nir_op_fall_equal2
; break;
88 case nir_op_ball_iequal3
: alu
->op
= nir_op_fall_equal3
; break;
89 case nir_op_ball_iequal4
: alu
->op
= nir_op_fall_equal4
; break;
90 case nir_op_bany_inequal2
: alu
->op
= nir_op_fany_nequal2
; break;
91 case nir_op_bany_inequal3
: alu
->op
= nir_op_fany_nequal3
; break;
92 case nir_op_bany_inequal4
: alu
->op
= nir_op_fany_nequal4
; break;
94 case nir_op_bcsel
: alu
->op
= nir_op_fcsel
; break;
96 case nir_op_iand
: alu
->op
= nir_op_fmul
; break;
97 case nir_op_ixor
: alu
->op
= nir_op_sne
; break;
98 case nir_op_ior
: alu
->op
= nir_op_fmax
; break;
101 rep
= nir_seq(b
, nir_ssa_for_alu_src(b
, alu
, 0),
102 nir_imm_float(b
, 0));
106 assert(alu
->dest
.dest
.ssa
.bit_size
> 1);
107 for (unsigned i
= 0; i
< op_info
->num_inputs
; i
++)
108 assert(alu
->src
[i
].src
.ssa
->bit_size
> 1);
113 /* We've emitted a replacement instruction */
114 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(rep
));
115 nir_instr_remove(&alu
->instr
);
117 if (alu
->dest
.dest
.ssa
.bit_size
== 1)
118 alu
->dest
.dest
.ssa
.bit_size
= 32;
125 nir_lower_bool_to_float_impl(nir_function_impl
*impl
)
127 bool progress
= false;
130 nir_builder_init(&b
, impl
);
132 nir_foreach_block(block
, impl
) {
133 nir_foreach_instr_safe(instr
, block
) {
134 switch (instr
->type
) {
135 case nir_instr_type_alu
:
136 progress
|= lower_alu_instr(&b
, nir_instr_as_alu(instr
));
139 case nir_instr_type_load_const
: {
140 nir_load_const_instr
*load
= nir_instr_as_load_const(instr
);
141 if (load
->def
.bit_size
== 1) {
142 nir_const_value
*value
= load
->value
;
143 for (unsigned i
= 0; i
< load
->def
.num_components
; i
++)
144 load
->value
[i
].f32
= value
[i
].b
? 1.0 : 0.0;
145 load
->def
.bit_size
= 32;
151 case nir_instr_type_intrinsic
:
152 case nir_instr_type_ssa_undef
:
153 case nir_instr_type_phi
:
154 case nir_instr_type_tex
:
155 nir_foreach_ssa_def(instr
, rewrite_1bit_ssa_def_to_32bit
,
160 nir_foreach_ssa_def(instr
, assert_ssa_def_is_not_1bit
, NULL
);
166 nir_metadata_preserve(impl
, nir_metadata_block_index
|
167 nir_metadata_dominance
);
174 nir_lower_bool_to_float(nir_shader
*shader
)
176 bool progress
= false;
178 nir_foreach_function(function
, shader
) {
179 if (function
->impl
&& nir_lower_bool_to_float_impl(function
->impl
))