src/compiler/nir/nir_lower_bool_to_int32.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "nir.h"
  25
  26 static bool
  27 assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
  28 {
  29    assert(def->bit_size > 1);
  30    return true;
  31 }
  32
  33 static bool
  34 rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
  35 {
  36    bool *progress = _progress;
  37    if (def->bit_size == 1) {
  38       def->bit_size = 32;
  39       *progress = true;
  40    }
  41    return true;
  42 }
  43
  44 static bool
  45 lower_alu_instr(nir_alu_instr *alu)
  46 {
  47    const nir_op_info *op_info = &nir_op_infos[alu->op];
  48
  49    switch (alu->op) {
  50    case nir_op_imov:
  51    case nir_op_vec2:
  52    case nir_op_vec3:
  53    case nir_op_vec4:
  54    case nir_op_inot:
  55    case nir_op_iand:
  56    case nir_op_ior:
  57    case nir_op_ixor:
  58       /* These we expect to have booleans but the opcode doesn't change */
  59       break;
  60
  61    case nir_op_f2b1: alu->op = nir_op_f2b32; break;
  62    case nir_op_i2b1: alu->op = nir_op_i2b32; break;
  63
  64    case nir_op_flt: alu->op = nir_op_flt32; break;
  65    case nir_op_fge: alu->op = nir_op_fge32; break;
  66    case nir_op_feq: alu->op = nir_op_feq32; break;
  67    case nir_op_fne: alu->op = nir_op_fne32; break;
  68    case nir_op_ilt: alu->op = nir_op_ilt32; break;
  69    case nir_op_ige: alu->op = nir_op_ige32; break;
  70    case nir_op_ieq: alu->op = nir_op_ieq32; break;
  71    case nir_op_ine: alu->op = nir_op_ine32; break;
  72    case nir_op_ult: alu->op = nir_op_ult32; break;
  73    case nir_op_uge: alu->op = nir_op_uge32; break;
  74
  75    case nir_op_ball_fequal2:  alu->op = nir_op_b32all_fequal2; break;
  76    case nir_op_ball_fequal3:  alu->op = nir_op_b32all_fequal3; break;
  77    case nir_op_ball_fequal4:  alu->op = nir_op_b32all_fequal4; break;
  78    case nir_op_bany_fnequal2: alu->op = nir_op_b32any_fnequal2; break;
  79    case nir_op_bany_fnequal3: alu->op = nir_op_b32any_fnequal3; break;
  80    case nir_op_bany_fnequal4: alu->op = nir_op_b32any_fnequal4; break;
  81    case nir_op_ball_iequal2:  alu->op = nir_op_b32all_iequal2; break;
  82    case nir_op_ball_iequal3:  alu->op = nir_op_b32all_iequal3; break;
  83    case nir_op_ball_iequal4:  alu->op = nir_op_b32all_iequal4; break;
  84    case nir_op_bany_inequal2: alu->op = nir_op_b32any_inequal2; break;
  85    case nir_op_bany_inequal3: alu->op = nir_op_b32any_inequal3; break;
  86    case nir_op_bany_inequal4: alu->op = nir_op_b32any_inequal4; break;
  87
  88    case nir_op_bcsel: alu->op = nir_op_b32csel; break;
  89
  90    default:
  91       assert(alu->dest.dest.ssa.bit_size > 1);
  92       for (unsigned i = 0; i < op_info->num_inputs; i++)
  93          assert(alu->src[i].src.ssa->bit_size > 1);
  94       return false;
  95    }
  96
  97    if (alu->dest.dest.ssa.bit_size == 1)
  98       alu->dest.dest.ssa.bit_size = 32;
  99
 100    return true;
 101 }
 102
 103 static bool
 104 nir_lower_bool_to_int32_impl(nir_function_impl *impl)
 105 {
 106    bool progress = false;
 107
 108    nir_foreach_block(block, impl) {
 109       nir_foreach_instr_safe(instr, block) {
 110          switch (instr->type) {
 111          case nir_instr_type_alu:
 112             progress |= lower_alu_instr(nir_instr_as_alu(instr));
 113             break;
 114
 115          case nir_instr_type_load_const: {
 116             nir_load_const_instr *load = nir_instr_as_load_const(instr);
 117             if (load->def.bit_size == 1) {
 118                nir_const_value value = load->value;
 119                for (unsigned i = 0; i < load->def.num_components; i++)
 120                   load->value.u32[i] = value.b[i] ? NIR_TRUE : NIR_FALSE;
 121                load->def.bit_size = 32;
 122                progress = true;
 123             }
 124             break;
 125          }
 126
 127          case nir_instr_type_intrinsic:
 128          case nir_instr_type_ssa_undef:
 129          case nir_instr_type_phi:
 130          case nir_instr_type_tex:
 131             nir_foreach_ssa_def(instr, rewrite_1bit_ssa_def_to_32bit,
 132                                 &progress);
 133             break;
 134
 135          default:
 136             nir_foreach_ssa_def(instr, assert_ssa_def_is_not_1bit, NULL);
 137          }
 138       }
 139    }
 140
 141    if (progress) {
 142       nir_metadata_preserve(impl, nir_metadata_block_index |
 143                                   nir_metadata_dominance);
 144    }
 145
 146    return progress;
 147 }
 148
 149 bool
 150 nir_lower_bool_to_int32(nir_shader *shader)
 151 {
 152    bool progress = false;
 153
 154    nir_foreach_function(function, shader) {
 155       if (function->impl && nir_lower_bool_to_int32_impl(function->impl))
 156          progress = true;
 157    }
 158
 159    return progress;
 160 }