nir: Remove shared support from lower_io
[mesa.git] / src / compiler / nir / nir_lower_io.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Connor Abbott (cwabbott0@gmail.com)
25 * Jason Ekstrand (jason@jlekstrand.net)
26 *
27 */
28
29 /*
30 * This lowering pass converts references to input/output variables with
31 * loads/stores to actual input/output intrinsics.
32 */
33
34 #include "nir.h"
35 #include "nir_builder.h"
36 #include "nir_deref.h"
37
38 #include "util/u_math.h"
39
40 struct lower_io_state {
41 void *dead_ctx;
42 nir_builder builder;
43 int (*type_size)(const struct glsl_type *type, bool);
44 nir_variable_mode modes;
45 nir_lower_io_options options;
46 };
47
48 static nir_intrinsic_op
49 ssbo_atomic_for_deref(nir_intrinsic_op deref_op)
50 {
51 switch (deref_op) {
52 #define OP(O) case nir_intrinsic_deref_##O: return nir_intrinsic_ssbo_##O;
53 OP(atomic_exchange)
54 OP(atomic_comp_swap)
55 OP(atomic_add)
56 OP(atomic_imin)
57 OP(atomic_umin)
58 OP(atomic_imax)
59 OP(atomic_umax)
60 OP(atomic_and)
61 OP(atomic_or)
62 OP(atomic_xor)
63 OP(atomic_fadd)
64 OP(atomic_fmin)
65 OP(atomic_fmax)
66 OP(atomic_fcomp_swap)
67 #undef OP
68 default:
69 unreachable("Invalid SSBO atomic");
70 }
71 }
72
73 static nir_intrinsic_op
74 global_atomic_for_deref(nir_intrinsic_op deref_op)
75 {
76 switch (deref_op) {
77 #define OP(O) case nir_intrinsic_deref_##O: return nir_intrinsic_global_##O;
78 OP(atomic_exchange)
79 OP(atomic_comp_swap)
80 OP(atomic_add)
81 OP(atomic_imin)
82 OP(atomic_umin)
83 OP(atomic_imax)
84 OP(atomic_umax)
85 OP(atomic_and)
86 OP(atomic_or)
87 OP(atomic_xor)
88 OP(atomic_fadd)
89 OP(atomic_fmin)
90 OP(atomic_fmax)
91 OP(atomic_fcomp_swap)
92 #undef OP
93 default:
94 unreachable("Invalid SSBO atomic");
95 }
96 }
97
98 static nir_intrinsic_op
99 shared_atomic_for_deref(nir_intrinsic_op deref_op)
100 {
101 switch (deref_op) {
102 #define OP(O) case nir_intrinsic_deref_##O: return nir_intrinsic_shared_##O;
103 OP(atomic_exchange)
104 OP(atomic_comp_swap)
105 OP(atomic_add)
106 OP(atomic_imin)
107 OP(atomic_umin)
108 OP(atomic_imax)
109 OP(atomic_umax)
110 OP(atomic_and)
111 OP(atomic_or)
112 OP(atomic_xor)
113 OP(atomic_fadd)
114 OP(atomic_fmin)
115 OP(atomic_fmax)
116 OP(atomic_fcomp_swap)
117 #undef OP
118 default:
119 unreachable("Invalid shared atomic");
120 }
121 }
122
123 void
124 nir_assign_var_locations(struct exec_list *var_list, unsigned *size,
125 int (*type_size)(const struct glsl_type *, bool))
126 {
127 unsigned location = 0;
128
129 nir_foreach_variable(var, var_list) {
130 /*
131 * UBOs have their own address spaces, so don't count them towards the
132 * number of global uniforms
133 */
134 if (var->data.mode == nir_var_mem_ubo || var->data.mode == nir_var_mem_ssbo)
135 continue;
136
137 var->data.driver_location = location;
138 bool bindless_type_size = var->data.mode == nir_var_shader_in ||
139 var->data.mode == nir_var_shader_out ||
140 var->data.bindless;
141 location += type_size(var->type, bindless_type_size);
142 }
143
144 *size = location;
145 }
146
147 /**
148 * Return true if the given variable is a per-vertex input/output array.
149 * (such as geometry shader inputs).
150 */
151 bool
152 nir_is_per_vertex_io(const nir_variable *var, gl_shader_stage stage)
153 {
154 if (var->data.patch || !glsl_type_is_array(var->type))
155 return false;
156
157 if (var->data.mode == nir_var_shader_in)
158 return stage == MESA_SHADER_GEOMETRY ||
159 stage == MESA_SHADER_TESS_CTRL ||
160 stage == MESA_SHADER_TESS_EVAL;
161
162 if (var->data.mode == nir_var_shader_out)
163 return stage == MESA_SHADER_TESS_CTRL;
164
165 return false;
166 }
167
168 static nir_ssa_def *
169 get_io_offset(nir_builder *b, nir_deref_instr *deref,
170 nir_ssa_def **vertex_index,
171 int (*type_size)(const struct glsl_type *, bool),
172 unsigned *component, bool bts)
173 {
174 nir_deref_path path;
175 nir_deref_path_init(&path, deref, NULL);
176
177 assert(path.path[0]->deref_type == nir_deref_type_var);
178 nir_deref_instr **p = &path.path[1];
179
180 /* For per-vertex input arrays (i.e. geometry shader inputs), keep the
181 * outermost array index separate. Process the rest normally.
182 */
183 if (vertex_index != NULL) {
184 assert((*p)->deref_type == nir_deref_type_array);
185 *vertex_index = nir_ssa_for_src(b, (*p)->arr.index, 1);
186 p++;
187 }
188
189 if (path.path[0]->var->data.compact) {
190 assert((*p)->deref_type == nir_deref_type_array);
191 assert(glsl_type_is_scalar((*p)->type));
192
193 /* We always lower indirect dereferences for "compact" array vars. */
194 const unsigned index = nir_src_as_uint((*p)->arr.index);
195 const unsigned total_offset = *component + index;
196 const unsigned slot_offset = total_offset / 4;
197 *component = total_offset % 4;
198 return nir_imm_int(b, type_size(glsl_vec4_type(), bts) * slot_offset);
199 }
200
201 /* Just emit code and let constant-folding go to town */
202 nir_ssa_def *offset = nir_imm_int(b, 0);
203
204 for (; *p; p++) {
205 if ((*p)->deref_type == nir_deref_type_array) {
206 unsigned size = type_size((*p)->type, bts);
207
208 nir_ssa_def *mul =
209 nir_amul_imm(b, nir_ssa_for_src(b, (*p)->arr.index, 1), size);
210
211 offset = nir_iadd(b, offset, mul);
212 } else if ((*p)->deref_type == nir_deref_type_struct) {
213 /* p starts at path[1], so this is safe */
214 nir_deref_instr *parent = *(p - 1);
215
216 unsigned field_offset = 0;
217 for (unsigned i = 0; i < (*p)->strct.index; i++) {
218 field_offset += type_size(glsl_get_struct_field(parent->type, i), bts);
219 }
220 offset = nir_iadd_imm(b, offset, field_offset);
221 } else {
222 unreachable("Unsupported deref type");
223 }
224 }
225
226 nir_deref_path_finish(&path);
227
228 return offset;
229 }
230
231 static nir_ssa_def *
232 emit_load(struct lower_io_state *state,
233 nir_ssa_def *vertex_index, nir_variable *var, nir_ssa_def *offset,
234 unsigned component, unsigned num_components, unsigned bit_size,
235 nir_alu_type type)
236 {
237 nir_builder *b = &state->builder;
238 const nir_shader *nir = b->shader;
239 nir_variable_mode mode = var->data.mode;
240 nir_ssa_def *barycentric = NULL;
241
242 nir_intrinsic_op op;
243 switch (mode) {
244 case nir_var_shader_in:
245 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
246 nir->options->use_interpolated_input_intrinsics &&
247 var->data.interpolation != INTERP_MODE_FLAT) {
248 if (var->data.interpolation == INTERP_MODE_EXPLICIT) {
249 assert(vertex_index != NULL);
250 op = nir_intrinsic_load_input_vertex;
251 } else {
252 assert(vertex_index == NULL);
253
254 nir_intrinsic_op bary_op;
255 if (var->data.sample ||
256 (state->options & nir_lower_io_force_sample_interpolation))
257 bary_op = nir_intrinsic_load_barycentric_sample;
258 else if (var->data.centroid)
259 bary_op = nir_intrinsic_load_barycentric_centroid;
260 else
261 bary_op = nir_intrinsic_load_barycentric_pixel;
262
263 barycentric = nir_load_barycentric(&state->builder, bary_op,
264 var->data.interpolation);
265 op = nir_intrinsic_load_interpolated_input;
266 }
267 } else {
268 op = vertex_index ? nir_intrinsic_load_per_vertex_input :
269 nir_intrinsic_load_input;
270 }
271 break;
272 case nir_var_shader_out:
273 op = vertex_index ? nir_intrinsic_load_per_vertex_output :
274 nir_intrinsic_load_output;
275 break;
276 case nir_var_uniform:
277 op = nir_intrinsic_load_uniform;
278 break;
279 default:
280 unreachable("Unknown variable mode");
281 }
282
283 nir_intrinsic_instr *load =
284 nir_intrinsic_instr_create(state->builder.shader, op);
285 load->num_components = num_components;
286
287 nir_intrinsic_set_base(load, var->data.driver_location);
288 if (mode == nir_var_shader_in || mode == nir_var_shader_out)
289 nir_intrinsic_set_component(load, component);
290
291 if (load->intrinsic == nir_intrinsic_load_uniform)
292 nir_intrinsic_set_range(load,
293 state->type_size(var->type, var->data.bindless));
294
295 if (load->intrinsic == nir_intrinsic_load_input ||
296 load->intrinsic == nir_intrinsic_load_input_vertex ||
297 load->intrinsic == nir_intrinsic_load_uniform)
298 nir_intrinsic_set_type(load, type);
299
300 if (vertex_index) {
301 load->src[0] = nir_src_for_ssa(vertex_index);
302 load->src[1] = nir_src_for_ssa(offset);
303 } else if (barycentric) {
304 load->src[0] = nir_src_for_ssa(barycentric);
305 load->src[1] = nir_src_for_ssa(offset);
306 } else {
307 load->src[0] = nir_src_for_ssa(offset);
308 }
309
310 nir_ssa_dest_init(&load->instr, &load->dest,
311 num_components, bit_size, NULL);
312 nir_builder_instr_insert(b, &load->instr);
313
314 return &load->dest.ssa;
315 }
316
317 static nir_ssa_def *
318 lower_load(nir_intrinsic_instr *intrin, struct lower_io_state *state,
319 nir_ssa_def *vertex_index, nir_variable *var, nir_ssa_def *offset,
320 unsigned component, const struct glsl_type *type)
321 {
322 assert(intrin->dest.is_ssa);
323 if (intrin->dest.ssa.bit_size == 64 &&
324 (state->options & nir_lower_io_lower_64bit_to_32)) {
325 nir_builder *b = &state->builder;
326
327 const unsigned slot_size = state->type_size(glsl_dvec_type(2), false);
328
329 nir_ssa_def *comp64[4];
330 assert(component == 0 || component == 2);
331 unsigned dest_comp = 0;
332 while (dest_comp < intrin->dest.ssa.num_components) {
333 const unsigned num_comps =
334 MIN2(intrin->dest.ssa.num_components - dest_comp,
335 (4 - component) / 2);
336
337 nir_ssa_def *data32 =
338 emit_load(state, vertex_index, var, offset, component,
339 num_comps * 2, 32, nir_type_uint32);
340 for (unsigned i = 0; i < num_comps; i++) {
341 comp64[dest_comp + i] =
342 nir_pack_64_2x32(b, nir_channels(b, data32, 3 << (i * 2)));
343 }
344
345 /* Only the first store has a component offset */
346 component = 0;
347 dest_comp += num_comps;
348 offset = nir_iadd_imm(b, offset, slot_size);
349 }
350
351 return nir_vec(b, comp64, intrin->dest.ssa.num_components);
352 } else if (intrin->dest.ssa.bit_size == 1) {
353 /* Booleans are 32-bit */
354 assert(glsl_type_is_boolean(type));
355 return nir_b2b1(&state->builder,
356 emit_load(state, vertex_index, var, offset, component,
357 intrin->dest.ssa.num_components, 32,
358 nir_type_bool32));
359 } else {
360 return emit_load(state, vertex_index, var, offset, component,
361 intrin->dest.ssa.num_components,
362 intrin->dest.ssa.bit_size,
363 nir_get_nir_type_for_glsl_type(type));
364 }
365 }
366
367 static void
368 emit_store(struct lower_io_state *state, nir_ssa_def *data,
369 nir_ssa_def *vertex_index, nir_variable *var, nir_ssa_def *offset,
370 unsigned component, unsigned num_components,
371 nir_component_mask_t write_mask, nir_alu_type type)
372 {
373 nir_builder *b = &state->builder;
374 nir_variable_mode mode = var->data.mode;
375
376 assert(mode == nir_var_shader_out);
377 nir_intrinsic_op op;
378 op = vertex_index ? nir_intrinsic_store_per_vertex_output :
379 nir_intrinsic_store_output;
380
381 nir_intrinsic_instr *store =
382 nir_intrinsic_instr_create(state->builder.shader, op);
383 store->num_components = num_components;
384
385 store->src[0] = nir_src_for_ssa(data);
386
387 nir_intrinsic_set_base(store, var->data.driver_location);
388
389 if (mode == nir_var_shader_out)
390 nir_intrinsic_set_component(store, component);
391
392 if (store->intrinsic == nir_intrinsic_store_output)
393 nir_intrinsic_set_type(store, type);
394
395 nir_intrinsic_set_write_mask(store, write_mask);
396
397 if (vertex_index)
398 store->src[1] = nir_src_for_ssa(vertex_index);
399
400 store->src[vertex_index ? 2 : 1] = nir_src_for_ssa(offset);
401
402 nir_builder_instr_insert(b, &store->instr);
403 }
404
405 static void
406 lower_store(nir_intrinsic_instr *intrin, struct lower_io_state *state,
407 nir_ssa_def *vertex_index, nir_variable *var, nir_ssa_def *offset,
408 unsigned component, const struct glsl_type *type)
409 {
410 assert(intrin->src[1].is_ssa);
411 if (intrin->src[1].ssa->bit_size == 64 &&
412 (state->options & nir_lower_io_lower_64bit_to_32)) {
413 nir_builder *b = &state->builder;
414
415 const unsigned slot_size = state->type_size(glsl_dvec_type(2), false);
416
417 assert(component == 0 || component == 2);
418 unsigned src_comp = 0;
419 nir_component_mask_t write_mask = nir_intrinsic_write_mask(intrin);
420 while (src_comp < intrin->num_components) {
421 const unsigned num_comps =
422 MIN2(intrin->num_components - src_comp,
423 (4 - component) / 2);
424
425 if (write_mask & BITFIELD_MASK(num_comps)) {
426 nir_ssa_def *data =
427 nir_channels(b, intrin->src[1].ssa,
428 BITFIELD_RANGE(src_comp, num_comps));
429 nir_ssa_def *data32 = nir_bitcast_vector(b, data, 32);
430
431 nir_component_mask_t write_mask32 = 0;
432 for (unsigned i = 0; i < num_comps; i++) {
433 if (write_mask & BITFIELD_MASK(num_comps) & (1 << i))
434 write_mask32 |= 3 << (i * 2);
435 }
436
437 emit_store(state, data32, vertex_index, var, offset,
438 component, data32->num_components, write_mask32,
439 nir_type_uint32);
440 }
441
442 /* Only the first store has a component offset */
443 component = 0;
444 src_comp += num_comps;
445 write_mask >>= num_comps;
446 offset = nir_iadd_imm(b, offset, slot_size);
447 }
448 } else if (intrin->dest.ssa.bit_size == 1) {
449 /* Booleans are 32-bit */
450 assert(glsl_type_is_boolean(type));
451 nir_ssa_def *b32_val = nir_b2b32(&state->builder, intrin->src[1].ssa);
452 emit_store(state, b32_val, vertex_index, var, offset,
453 component, intrin->num_components,
454 nir_intrinsic_write_mask(intrin),
455 nir_type_bool32);
456 } else {
457 emit_store(state, intrin->src[1].ssa, vertex_index, var, offset,
458 component, intrin->num_components,
459 nir_intrinsic_write_mask(intrin),
460 nir_get_nir_type_for_glsl_type(type));
461 }
462 }
463
464 static nir_ssa_def *
465 lower_interpolate_at(nir_intrinsic_instr *intrin, struct lower_io_state *state,
466 nir_variable *var, nir_ssa_def *offset, unsigned component,
467 const struct glsl_type *type)
468 {
469 nir_builder *b = &state->builder;
470 assert(var->data.mode == nir_var_shader_in);
471
472 /* Ignore interpolateAt() for flat variables - flat is flat. Lower
473 * interpolateAtVertex() for explicit variables.
474 */
475 if (var->data.interpolation == INTERP_MODE_FLAT ||
476 var->data.interpolation == INTERP_MODE_EXPLICIT) {
477 nir_ssa_def *vertex_index = NULL;
478
479 if (var->data.interpolation == INTERP_MODE_EXPLICIT) {
480 assert(intrin->intrinsic == nir_intrinsic_interp_deref_at_vertex);
481 vertex_index = intrin->src[1].ssa;
482 }
483
484 return lower_load(intrin, state, vertex_index, var, offset, component, type);
485 }
486
487 /* None of the supported APIs allow interpolation on 64-bit things */
488 assert(intrin->dest.is_ssa && intrin->dest.ssa.bit_size <= 32);
489
490 nir_intrinsic_op bary_op;
491 switch (intrin->intrinsic) {
492 case nir_intrinsic_interp_deref_at_centroid:
493 bary_op = (state->options & nir_lower_io_force_sample_interpolation) ?
494 nir_intrinsic_load_barycentric_sample :
495 nir_intrinsic_load_barycentric_centroid;
496 break;
497 case nir_intrinsic_interp_deref_at_sample:
498 bary_op = nir_intrinsic_load_barycentric_at_sample;
499 break;
500 case nir_intrinsic_interp_deref_at_offset:
501 bary_op = nir_intrinsic_load_barycentric_at_offset;
502 break;
503 default:
504 unreachable("Bogus interpolateAt() intrinsic.");
505 }
506
507 nir_intrinsic_instr *bary_setup =
508 nir_intrinsic_instr_create(state->builder.shader, bary_op);
509
510 nir_ssa_dest_init(&bary_setup->instr, &bary_setup->dest, 2, 32, NULL);
511 nir_intrinsic_set_interp_mode(bary_setup, var->data.interpolation);
512
513 if (intrin->intrinsic == nir_intrinsic_interp_deref_at_sample ||
514 intrin->intrinsic == nir_intrinsic_interp_deref_at_offset ||
515 intrin->intrinsic == nir_intrinsic_interp_deref_at_vertex)
516 nir_src_copy(&bary_setup->src[0], &intrin->src[1], bary_setup);
517
518 nir_builder_instr_insert(b, &bary_setup->instr);
519
520 nir_intrinsic_instr *load =
521 nir_intrinsic_instr_create(state->builder.shader,
522 nir_intrinsic_load_interpolated_input);
523 load->num_components = intrin->num_components;
524
525 nir_intrinsic_set_base(load, var->data.driver_location);
526 nir_intrinsic_set_component(load, component);
527
528 load->src[0] = nir_src_for_ssa(&bary_setup->dest.ssa);
529 load->src[1] = nir_src_for_ssa(offset);
530
531 assert(intrin->dest.is_ssa);
532 nir_ssa_dest_init(&load->instr, &load->dest,
533 intrin->dest.ssa.num_components,
534 intrin->dest.ssa.bit_size, NULL);
535 nir_builder_instr_insert(b, &load->instr);
536
537 return &load->dest.ssa;
538 }
539
540 static bool
541 nir_lower_io_block(nir_block *block,
542 struct lower_io_state *state)
543 {
544 nir_builder *b = &state->builder;
545 const nir_shader_compiler_options *options = b->shader->options;
546 bool progress = false;
547
548 nir_foreach_instr_safe(instr, block) {
549 if (instr->type != nir_instr_type_intrinsic)
550 continue;
551
552 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
553
554 switch (intrin->intrinsic) {
555 case nir_intrinsic_load_deref:
556 case nir_intrinsic_store_deref:
557 /* We can lower the io for this nir instrinsic */
558 break;
559 case nir_intrinsic_interp_deref_at_centroid:
560 case nir_intrinsic_interp_deref_at_sample:
561 case nir_intrinsic_interp_deref_at_offset:
562 case nir_intrinsic_interp_deref_at_vertex:
563 /* We can optionally lower these to load_interpolated_input */
564 if (options->use_interpolated_input_intrinsics)
565 break;
566 default:
567 /* We can't lower the io for this nir instrinsic, so skip it */
568 continue;
569 }
570
571 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
572
573 nir_variable_mode mode = deref->mode;
574 assert(util_is_power_of_two_nonzero(mode));
575 if ((state->modes & mode) == 0)
576 continue;
577
578 nir_variable *var = nir_deref_instr_get_variable(deref);
579
580 b->cursor = nir_before_instr(instr);
581
582 const bool per_vertex = nir_is_per_vertex_io(var, b->shader->info.stage);
583
584 nir_ssa_def *offset;
585 nir_ssa_def *vertex_index = NULL;
586 unsigned component_offset = var->data.location_frac;
587 bool bindless_type_size = mode == nir_var_shader_in ||
588 mode == nir_var_shader_out ||
589 var->data.bindless;
590
591 offset = get_io_offset(b, deref, per_vertex ? &vertex_index : NULL,
592 state->type_size, &component_offset,
593 bindless_type_size);
594
595 nir_ssa_def *replacement = NULL;
596
597 switch (intrin->intrinsic) {
598 case nir_intrinsic_load_deref:
599 replacement = lower_load(intrin, state, vertex_index, var, offset,
600 component_offset, deref->type);
601 break;
602
603 case nir_intrinsic_store_deref:
604 lower_store(intrin, state, vertex_index, var, offset,
605 component_offset, deref->type);
606 break;
607
608 case nir_intrinsic_interp_deref_at_centroid:
609 case nir_intrinsic_interp_deref_at_sample:
610 case nir_intrinsic_interp_deref_at_offset:
611 case nir_intrinsic_interp_deref_at_vertex:
612 assert(vertex_index == NULL);
613 replacement = lower_interpolate_at(intrin, state, var, offset,
614 component_offset, deref->type);
615 break;
616
617 default:
618 continue;
619 }
620
621 if (replacement) {
622 nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
623 nir_src_for_ssa(replacement));
624 }
625 nir_instr_remove(&intrin->instr);
626 progress = true;
627 }
628
629 return progress;
630 }
631
632 static bool
633 nir_lower_io_impl(nir_function_impl *impl,
634 nir_variable_mode modes,
635 int (*type_size)(const struct glsl_type *, bool),
636 nir_lower_io_options options)
637 {
638 struct lower_io_state state;
639 bool progress = false;
640
641 nir_builder_init(&state.builder, impl);
642 state.dead_ctx = ralloc_context(NULL);
643 state.modes = modes;
644 state.type_size = type_size;
645 state.options = options;
646
647 ASSERTED nir_variable_mode supported_modes =
648 nir_var_shader_in | nir_var_shader_out | nir_var_uniform;
649 assert(!(modes & ~supported_modes));
650
651 nir_foreach_block(block, impl) {
652 progress |= nir_lower_io_block(block, &state);
653 }
654
655 ralloc_free(state.dead_ctx);
656
657 nir_metadata_preserve(impl, nir_metadata_block_index |
658 nir_metadata_dominance);
659 return progress;
660 }
661
662 bool
663 nir_lower_io(nir_shader *shader, nir_variable_mode modes,
664 int (*type_size)(const struct glsl_type *, bool),
665 nir_lower_io_options options)
666 {
667 bool progress = false;
668
669 nir_foreach_function(function, shader) {
670 if (function->impl) {
671 progress |= nir_lower_io_impl(function->impl, modes,
672 type_size, options);
673 }
674 }
675
676 return progress;
677 }
678
679 static unsigned
680 type_scalar_size_bytes(const struct glsl_type *type)
681 {
682 assert(glsl_type_is_vector_or_scalar(type) ||
683 glsl_type_is_matrix(type));
684 return glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
685 }
686
687 static nir_ssa_def *
688 build_addr_iadd(nir_builder *b, nir_ssa_def *addr,
689 nir_address_format addr_format, nir_ssa_def *offset)
690 {
691 assert(offset->num_components == 1);
692 assert(addr->bit_size == offset->bit_size);
693
694 switch (addr_format) {
695 case nir_address_format_32bit_global:
696 case nir_address_format_64bit_global:
697 case nir_address_format_32bit_offset:
698 assert(addr->num_components == 1);
699 return nir_iadd(b, addr, offset);
700
701 case nir_address_format_64bit_bounded_global:
702 assert(addr->num_components == 4);
703 return nir_vec4(b, nir_channel(b, addr, 0),
704 nir_channel(b, addr, 1),
705 nir_channel(b, addr, 2),
706 nir_iadd(b, nir_channel(b, addr, 3), offset));
707
708 case nir_address_format_32bit_index_offset:
709 assert(addr->num_components == 2);
710 return nir_vec2(b, nir_channel(b, addr, 0),
711 nir_iadd(b, nir_channel(b, addr, 1), offset));
712 case nir_address_format_vec2_index_32bit_offset:
713 assert(addr->num_components == 3);
714 return nir_vec3(b, nir_channel(b, addr, 0), nir_channel(b, addr, 1),
715 nir_iadd(b, nir_channel(b, addr, 2), offset));
716 case nir_address_format_logical:
717 unreachable("Unsupported address format");
718 }
719 unreachable("Invalid address format");
720 }
721
722 static nir_ssa_def *
723 build_addr_iadd_imm(nir_builder *b, nir_ssa_def *addr,
724 nir_address_format addr_format, int64_t offset)
725 {
726 return build_addr_iadd(b, addr, addr_format,
727 nir_imm_intN_t(b, offset, addr->bit_size));
728 }
729
730 static nir_ssa_def *
731 addr_to_index(nir_builder *b, nir_ssa_def *addr,
732 nir_address_format addr_format)
733 {
734 if (addr_format == nir_address_format_32bit_index_offset) {
735 assert(addr->num_components == 2);
736 return nir_channel(b, addr, 0);
737 } else if (addr_format == nir_address_format_vec2_index_32bit_offset) {
738 assert(addr->num_components == 3);
739 return nir_channels(b, addr, 0x3);
740 } else {
741 unreachable("bad address format for index");
742 }
743 }
744
745 static nir_ssa_def *
746 addr_to_offset(nir_builder *b, nir_ssa_def *addr,
747 nir_address_format addr_format)
748 {
749 if (addr_format == nir_address_format_32bit_index_offset) {
750 assert(addr->num_components == 2);
751 return nir_channel(b, addr, 1);
752 } else if (addr_format == nir_address_format_vec2_index_32bit_offset) {
753 assert(addr->num_components == 3);
754 return nir_channel(b, addr, 2);
755 } else {
756 unreachable("bad address format for offset");
757 }
758 }
759
760 /** Returns true if the given address format resolves to a global address */
761 static bool
762 addr_format_is_global(nir_address_format addr_format)
763 {
764 return addr_format == nir_address_format_32bit_global ||
765 addr_format == nir_address_format_64bit_global ||
766 addr_format == nir_address_format_64bit_bounded_global;
767 }
768
769 static nir_ssa_def *
770 addr_to_global(nir_builder *b, nir_ssa_def *addr,
771 nir_address_format addr_format)
772 {
773 switch (addr_format) {
774 case nir_address_format_32bit_global:
775 case nir_address_format_64bit_global:
776 assert(addr->num_components == 1);
777 return addr;
778
779 case nir_address_format_64bit_bounded_global:
780 assert(addr->num_components == 4);
781 return nir_iadd(b, nir_pack_64_2x32(b, nir_channels(b, addr, 0x3)),
782 nir_u2u64(b, nir_channel(b, addr, 3)));
783
784 case nir_address_format_32bit_index_offset:
785 case nir_address_format_vec2_index_32bit_offset:
786 case nir_address_format_32bit_offset:
787 case nir_address_format_logical:
788 unreachable("Cannot get a 64-bit address with this address format");
789 }
790
791 unreachable("Invalid address format");
792 }
793
794 static bool
795 addr_format_needs_bounds_check(nir_address_format addr_format)
796 {
797 return addr_format == nir_address_format_64bit_bounded_global;
798 }
799
800 static nir_ssa_def *
801 addr_is_in_bounds(nir_builder *b, nir_ssa_def *addr,
802 nir_address_format addr_format, unsigned size)
803 {
804 assert(addr_format == nir_address_format_64bit_bounded_global);
805 assert(addr->num_components == 4);
806 return nir_ige(b, nir_channel(b, addr, 2),
807 nir_iadd_imm(b, nir_channel(b, addr, 3), size));
808 }
809
810 static nir_ssa_def *
811 build_explicit_io_load(nir_builder *b, nir_intrinsic_instr *intrin,
812 nir_ssa_def *addr, nir_address_format addr_format,
813 unsigned num_components)
814 {
815 nir_variable_mode mode = nir_src_as_deref(intrin->src[0])->mode;
816
817 nir_intrinsic_op op;
818 switch (mode) {
819 case nir_var_mem_ubo:
820 op = nir_intrinsic_load_ubo;
821 break;
822 case nir_var_mem_ssbo:
823 if (addr_format_is_global(addr_format))
824 op = nir_intrinsic_load_global;
825 else
826 op = nir_intrinsic_load_ssbo;
827 break;
828 case nir_var_mem_global:
829 assert(addr_format_is_global(addr_format));
830 op = nir_intrinsic_load_global;
831 break;
832 case nir_var_shader_in:
833 assert(addr_format_is_global(addr_format));
834 op = nir_intrinsic_load_kernel_input;
835 break;
836 case nir_var_mem_shared:
837 assert(addr_format == nir_address_format_32bit_offset);
838 op = nir_intrinsic_load_shared;
839 break;
840 default:
841 unreachable("Unsupported explicit IO variable mode");
842 }
843
844 nir_intrinsic_instr *load = nir_intrinsic_instr_create(b->shader, op);
845
846 if (addr_format_is_global(addr_format)) {
847 load->src[0] = nir_src_for_ssa(addr_to_global(b, addr, addr_format));
848 } else if (addr_format == nir_address_format_32bit_offset) {
849 assert(addr->num_components == 1);
850 load->src[0] = nir_src_for_ssa(addr);
851 } else {
852 load->src[0] = nir_src_for_ssa(addr_to_index(b, addr, addr_format));
853 load->src[1] = nir_src_for_ssa(addr_to_offset(b, addr, addr_format));
854 }
855
856 if (mode != nir_var_shader_in && mode != nir_var_mem_shared)
857 nir_intrinsic_set_access(load, nir_intrinsic_access(intrin));
858
859 unsigned bit_size = intrin->dest.ssa.bit_size;
860 if (bit_size == 1) {
861 /* TODO: Make the native bool bit_size an option. */
862 bit_size = 32;
863 }
864
865 /* TODO: We should try and provide a better alignment. For OpenCL, we need
866 * to plumb the alignment through from SPIR-V when we have one.
867 */
868 nir_intrinsic_set_align(load, bit_size / 8, 0);
869
870 assert(intrin->dest.is_ssa);
871 load->num_components = num_components;
872 nir_ssa_dest_init(&load->instr, &load->dest, num_components,
873 bit_size, intrin->dest.ssa.name);
874
875 assert(bit_size % 8 == 0);
876
877 nir_ssa_def *result;
878 if (addr_format_needs_bounds_check(addr_format)) {
879 /* The Vulkan spec for robustBufferAccess gives us quite a few options
880 * as to what we can do with an OOB read. Unfortunately, returning
881 * undefined values isn't one of them so we return an actual zero.
882 */
883 nir_ssa_def *zero = nir_imm_zero(b, load->num_components, bit_size);
884
885 const unsigned load_size = (bit_size / 8) * load->num_components;
886 nir_push_if(b, addr_is_in_bounds(b, addr, addr_format, load_size));
887
888 nir_builder_instr_insert(b, &load->instr);
889
890 nir_pop_if(b, NULL);
891
892 result = nir_if_phi(b, &load->dest.ssa, zero);
893 } else {
894 nir_builder_instr_insert(b, &load->instr);
895 result = &load->dest.ssa;
896 }
897
898 if (intrin->dest.ssa.bit_size == 1) {
899 /* For shared, we can go ahead and use NIR's and/or the back-end's
900 * standard encoding for booleans rather than forcing a 0/1 boolean.
901 * This should save an instruction or two.
902 */
903 if (mode == nir_var_mem_shared)
904 result = nir_b2b1(b, result);
905 else
906 result = nir_i2b(b, result);
907 }
908
909 return result;
910 }
911
912 static void
913 build_explicit_io_store(nir_builder *b, nir_intrinsic_instr *intrin,
914 nir_ssa_def *addr, nir_address_format addr_format,
915 nir_ssa_def *value, nir_component_mask_t write_mask)
916 {
917 nir_variable_mode mode = nir_src_as_deref(intrin->src[0])->mode;
918
919 nir_intrinsic_op op;
920 switch (mode) {
921 case nir_var_mem_ssbo:
922 if (addr_format_is_global(addr_format))
923 op = nir_intrinsic_store_global;
924 else
925 op = nir_intrinsic_store_ssbo;
926 break;
927 case nir_var_mem_global:
928 assert(addr_format_is_global(addr_format));
929 op = nir_intrinsic_store_global;
930 break;
931 case nir_var_mem_shared:
932 assert(addr_format == nir_address_format_32bit_offset);
933 op = nir_intrinsic_store_shared;
934 break;
935 default:
936 unreachable("Unsupported explicit IO variable mode");
937 }
938
939 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b->shader, op);
940
941 if (value->bit_size == 1) {
942 /* For shared, we can go ahead and use NIR's and/or the back-end's
943 * standard encoding for booleans rather than forcing a 0/1 boolean.
944 * This should save an instruction or two.
945 *
946 * TODO: Make the native bool bit_size an option.
947 */
948 if (mode == nir_var_mem_shared)
949 value = nir_b2b32(b, value);
950 else
951 value = nir_b2i(b, value, 32);
952 }
953
954 store->src[0] = nir_src_for_ssa(value);
955 if (addr_format_is_global(addr_format)) {
956 store->src[1] = nir_src_for_ssa(addr_to_global(b, addr, addr_format));
957 } else if (addr_format == nir_address_format_32bit_offset) {
958 assert(addr->num_components == 1);
959 store->src[1] = nir_src_for_ssa(addr);
960 } else {
961 store->src[1] = nir_src_for_ssa(addr_to_index(b, addr, addr_format));
962 store->src[2] = nir_src_for_ssa(addr_to_offset(b, addr, addr_format));
963 }
964
965 nir_intrinsic_set_write_mask(store, write_mask);
966
967 if (mode != nir_var_mem_shared)
968 nir_intrinsic_set_access(store, nir_intrinsic_access(intrin));
969
970 /* TODO: We should try and provide a better alignment. For OpenCL, we need
971 * to plumb the alignment through from SPIR-V when we have one.
972 */
973 nir_intrinsic_set_align(store, value->bit_size / 8, 0);
974
975 assert(value->num_components == 1 ||
976 value->num_components == intrin->num_components);
977 store->num_components = value->num_components;
978
979 assert(value->bit_size % 8 == 0);
980
981 if (addr_format_needs_bounds_check(addr_format)) {
982 const unsigned store_size = (value->bit_size / 8) * store->num_components;
983 nir_push_if(b, addr_is_in_bounds(b, addr, addr_format, store_size));
984
985 nir_builder_instr_insert(b, &store->instr);
986
987 nir_pop_if(b, NULL);
988 } else {
989 nir_builder_instr_insert(b, &store->instr);
990 }
991 }
992
993 static nir_ssa_def *
994 build_explicit_io_atomic(nir_builder *b, nir_intrinsic_instr *intrin,
995 nir_ssa_def *addr, nir_address_format addr_format)
996 {
997 nir_variable_mode mode = nir_src_as_deref(intrin->src[0])->mode;
998 const unsigned num_data_srcs =
999 nir_intrinsic_infos[intrin->intrinsic].num_srcs - 1;
1000
1001 nir_intrinsic_op op;
1002 switch (mode) {
1003 case nir_var_mem_ssbo:
1004 if (addr_format_is_global(addr_format))
1005 op = global_atomic_for_deref(intrin->intrinsic);
1006 else
1007 op = ssbo_atomic_for_deref(intrin->intrinsic);
1008 break;
1009 case nir_var_mem_global:
1010 assert(addr_format_is_global(addr_format));
1011 op = global_atomic_for_deref(intrin->intrinsic);
1012 break;
1013 case nir_var_mem_shared:
1014 assert(addr_format == nir_address_format_32bit_offset);
1015 op = shared_atomic_for_deref(intrin->intrinsic);
1016 break;
1017 default:
1018 unreachable("Unsupported explicit IO variable mode");
1019 }
1020
1021 nir_intrinsic_instr *atomic = nir_intrinsic_instr_create(b->shader, op);
1022
1023 unsigned src = 0;
1024 if (addr_format_is_global(addr_format)) {
1025 atomic->src[src++] = nir_src_for_ssa(addr_to_global(b, addr, addr_format));
1026 } else if (addr_format == nir_address_format_32bit_offset) {
1027 assert(addr->num_components == 1);
1028 atomic->src[src++] = nir_src_for_ssa(addr);
1029 } else {
1030 atomic->src[src++] = nir_src_for_ssa(addr_to_index(b, addr, addr_format));
1031 atomic->src[src++] = nir_src_for_ssa(addr_to_offset(b, addr, addr_format));
1032 }
1033 for (unsigned i = 0; i < num_data_srcs; i++) {
1034 atomic->src[src++] = nir_src_for_ssa(intrin->src[1 + i].ssa);
1035 }
1036
1037 /* Global atomics don't have access flags because they assume that the
1038 * address may be non-uniform.
1039 */
1040 if (!addr_format_is_global(addr_format) && mode != nir_var_mem_shared)
1041 nir_intrinsic_set_access(atomic, nir_intrinsic_access(intrin));
1042
1043 assert(intrin->dest.ssa.num_components == 1);
1044 nir_ssa_dest_init(&atomic->instr, &atomic->dest,
1045 1, intrin->dest.ssa.bit_size, intrin->dest.ssa.name);
1046
1047 assert(atomic->dest.ssa.bit_size % 8 == 0);
1048
1049 if (addr_format_needs_bounds_check(addr_format)) {
1050 const unsigned atomic_size = atomic->dest.ssa.bit_size / 8;
1051 nir_push_if(b, addr_is_in_bounds(b, addr, addr_format, atomic_size));
1052
1053 nir_builder_instr_insert(b, &atomic->instr);
1054
1055 nir_pop_if(b, NULL);
1056 return nir_if_phi(b, &atomic->dest.ssa,
1057 nir_ssa_undef(b, 1, atomic->dest.ssa.bit_size));
1058 } else {
1059 nir_builder_instr_insert(b, &atomic->instr);
1060 return &atomic->dest.ssa;
1061 }
1062 }
1063
1064 nir_ssa_def *
1065 nir_explicit_io_address_from_deref(nir_builder *b, nir_deref_instr *deref,
1066 nir_ssa_def *base_addr,
1067 nir_address_format addr_format)
1068 {
1069 assert(deref->dest.is_ssa);
1070 switch (deref->deref_type) {
1071 case nir_deref_type_var:
1072 assert(deref->mode & (nir_var_shader_in | nir_var_mem_shared));
1073 return nir_imm_intN_t(b, deref->var->data.driver_location,
1074 deref->dest.ssa.bit_size);
1075
1076 case nir_deref_type_array: {
1077 nir_deref_instr *parent = nir_deref_instr_parent(deref);
1078
1079 unsigned stride = glsl_get_explicit_stride(parent->type);
1080 if ((glsl_type_is_matrix(parent->type) &&
1081 glsl_matrix_type_is_row_major(parent->type)) ||
1082 (glsl_type_is_vector(parent->type) && stride == 0))
1083 stride = type_scalar_size_bytes(parent->type);
1084
1085 assert(stride > 0);
1086
1087 nir_ssa_def *index = nir_ssa_for_src(b, deref->arr.index, 1);
1088 index = nir_i2i(b, index, base_addr->bit_size);
1089 return build_addr_iadd(b, base_addr, addr_format,
1090 nir_amul_imm(b, index, stride));
1091 }
1092
1093 case nir_deref_type_ptr_as_array: {
1094 nir_ssa_def *index = nir_ssa_for_src(b, deref->arr.index, 1);
1095 index = nir_i2i(b, index, base_addr->bit_size);
1096 unsigned stride = nir_deref_instr_ptr_as_array_stride(deref);
1097 return build_addr_iadd(b, base_addr, addr_format,
1098 nir_amul_imm(b, index, stride));
1099 }
1100
1101 case nir_deref_type_array_wildcard:
1102 unreachable("Wildcards should be lowered by now");
1103 break;
1104
1105 case nir_deref_type_struct: {
1106 nir_deref_instr *parent = nir_deref_instr_parent(deref);
1107 int offset = glsl_get_struct_field_offset(parent->type,
1108 deref->strct.index);
1109 assert(offset >= 0);
1110 return build_addr_iadd_imm(b, base_addr, addr_format, offset);
1111 }
1112
1113 case nir_deref_type_cast:
1114 /* Nothing to do here */
1115 return base_addr;
1116 }
1117
1118 unreachable("Invalid NIR deref type");
1119 }
1120
1121 void
1122 nir_lower_explicit_io_instr(nir_builder *b,
1123 nir_intrinsic_instr *intrin,
1124 nir_ssa_def *addr,
1125 nir_address_format addr_format)
1126 {
1127 b->cursor = nir_after_instr(&intrin->instr);
1128
1129 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
1130 unsigned vec_stride = glsl_get_explicit_stride(deref->type);
1131 unsigned scalar_size = type_scalar_size_bytes(deref->type);
1132 assert(vec_stride == 0 || glsl_type_is_vector(deref->type));
1133 assert(vec_stride == 0 || vec_stride >= scalar_size);
1134
1135 if (intrin->intrinsic == nir_intrinsic_load_deref) {
1136 nir_ssa_def *value;
1137 if (vec_stride > scalar_size) {
1138 nir_ssa_def *comps[4] = { NULL, };
1139 for (unsigned i = 0; i < intrin->num_components; i++) {
1140 nir_ssa_def *comp_addr = build_addr_iadd_imm(b, addr, addr_format,
1141 vec_stride * i);
1142 comps[i] = build_explicit_io_load(b, intrin, comp_addr,
1143 addr_format, 1);
1144 }
1145 value = nir_vec(b, comps, intrin->num_components);
1146 } else {
1147 value = build_explicit_io_load(b, intrin, addr, addr_format,
1148 intrin->num_components);
1149 }
1150 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(value));
1151 } else if (intrin->intrinsic == nir_intrinsic_store_deref) {
1152 assert(intrin->src[1].is_ssa);
1153 nir_ssa_def *value = intrin->src[1].ssa;
1154 nir_component_mask_t write_mask = nir_intrinsic_write_mask(intrin);
1155 if (vec_stride > scalar_size) {
1156 for (unsigned i = 0; i < intrin->num_components; i++) {
1157 if (!(write_mask & (1 << i)))
1158 continue;
1159
1160 nir_ssa_def *comp_addr = build_addr_iadd_imm(b, addr, addr_format,
1161 vec_stride * i);
1162 build_explicit_io_store(b, intrin, comp_addr, addr_format,
1163 nir_channel(b, value, i), 1);
1164 }
1165 } else {
1166 build_explicit_io_store(b, intrin, addr, addr_format,
1167 value, write_mask);
1168 }
1169 } else {
1170 nir_ssa_def *value =
1171 build_explicit_io_atomic(b, intrin, addr, addr_format);
1172 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(value));
1173 }
1174
1175 nir_instr_remove(&intrin->instr);
1176 }
1177
1178 static void
1179 lower_explicit_io_deref(nir_builder *b, nir_deref_instr *deref,
1180 nir_address_format addr_format)
1181 {
1182 /* Just delete the deref if it's not used. We can't use
1183 * nir_deref_instr_remove_if_unused here because it may remove more than
1184 * one deref which could break our list walking since we walk the list
1185 * backwards.
1186 */
1187 assert(list_is_empty(&deref->dest.ssa.if_uses));
1188 if (list_is_empty(&deref->dest.ssa.uses)) {
1189 nir_instr_remove(&deref->instr);
1190 return;
1191 }
1192
1193 b->cursor = nir_after_instr(&deref->instr);
1194
1195 nir_ssa_def *base_addr = NULL;
1196 if (deref->deref_type != nir_deref_type_var) {
1197 assert(deref->parent.is_ssa);
1198 base_addr = deref->parent.ssa;
1199 }
1200
1201 nir_ssa_def *addr = nir_explicit_io_address_from_deref(b, deref, base_addr,
1202 addr_format);
1203
1204 nir_instr_remove(&deref->instr);
1205 nir_ssa_def_rewrite_uses(&deref->dest.ssa, nir_src_for_ssa(addr));
1206 }
1207
1208 static void
1209 lower_explicit_io_access(nir_builder *b, nir_intrinsic_instr *intrin,
1210 nir_address_format addr_format)
1211 {
1212 assert(intrin->src[0].is_ssa);
1213 nir_lower_explicit_io_instr(b, intrin, intrin->src[0].ssa, addr_format);
1214 }
1215
1216 static void
1217 lower_explicit_io_array_length(nir_builder *b, nir_intrinsic_instr *intrin,
1218 nir_address_format addr_format)
1219 {
1220 b->cursor = nir_after_instr(&intrin->instr);
1221
1222 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
1223
1224 assert(glsl_type_is_array(deref->type));
1225 assert(glsl_get_length(deref->type) == 0);
1226 unsigned stride = glsl_get_explicit_stride(deref->type);
1227 assert(stride > 0);
1228
1229 assert(addr_format == nir_address_format_32bit_index_offset ||
1230 addr_format == nir_address_format_vec2_index_32bit_offset);
1231 nir_ssa_def *addr = &deref->dest.ssa;
1232 nir_ssa_def *index = addr_to_index(b, addr, addr_format);
1233 nir_ssa_def *offset = addr_to_offset(b, addr, addr_format);
1234
1235 nir_intrinsic_instr *bsize =
1236 nir_intrinsic_instr_create(b->shader, nir_intrinsic_get_buffer_size);
1237 bsize->src[0] = nir_src_for_ssa(index);
1238 nir_ssa_dest_init(&bsize->instr, &bsize->dest, 1, 32, NULL);
1239 nir_builder_instr_insert(b, &bsize->instr);
1240
1241 nir_ssa_def *arr_size =
1242 nir_idiv(b, nir_isub(b, &bsize->dest.ssa, offset),
1243 nir_imm_int(b, stride));
1244
1245 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(arr_size));
1246 nir_instr_remove(&intrin->instr);
1247 }
1248
1249 static bool
1250 nir_lower_explicit_io_impl(nir_function_impl *impl, nir_variable_mode modes,
1251 nir_address_format addr_format)
1252 {
1253 bool progress = false;
1254
1255 nir_builder b;
1256 nir_builder_init(&b, impl);
1257
1258 /* Walk in reverse order so that we can see the full deref chain when we
1259 * lower the access operations. We lower them assuming that the derefs
1260 * will be turned into address calculations later.
1261 */
1262 nir_foreach_block_reverse(block, impl) {
1263 nir_foreach_instr_reverse_safe(instr, block) {
1264 switch (instr->type) {
1265 case nir_instr_type_deref: {
1266 nir_deref_instr *deref = nir_instr_as_deref(instr);
1267 if (deref->mode & modes) {
1268 lower_explicit_io_deref(&b, deref, addr_format);
1269 progress = true;
1270 }
1271 break;
1272 }
1273
1274 case nir_instr_type_intrinsic: {
1275 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
1276 switch (intrin->intrinsic) {
1277 case nir_intrinsic_load_deref:
1278 case nir_intrinsic_store_deref:
1279 case nir_intrinsic_deref_atomic_add:
1280 case nir_intrinsic_deref_atomic_imin:
1281 case nir_intrinsic_deref_atomic_umin:
1282 case nir_intrinsic_deref_atomic_imax:
1283 case nir_intrinsic_deref_atomic_umax:
1284 case nir_intrinsic_deref_atomic_and:
1285 case nir_intrinsic_deref_atomic_or:
1286 case nir_intrinsic_deref_atomic_xor:
1287 case nir_intrinsic_deref_atomic_exchange:
1288 case nir_intrinsic_deref_atomic_comp_swap:
1289 case nir_intrinsic_deref_atomic_fadd:
1290 case nir_intrinsic_deref_atomic_fmin:
1291 case nir_intrinsic_deref_atomic_fmax:
1292 case nir_intrinsic_deref_atomic_fcomp_swap: {
1293 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
1294 if (deref->mode & modes) {
1295 lower_explicit_io_access(&b, intrin, addr_format);
1296 progress = true;
1297 }
1298 break;
1299 }
1300
1301 case nir_intrinsic_deref_buffer_array_length: {
1302 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
1303 if (deref->mode & modes) {
1304 lower_explicit_io_array_length(&b, intrin, addr_format);
1305 progress = true;
1306 }
1307 break;
1308 }
1309
1310 default:
1311 break;
1312 }
1313 break;
1314 }
1315
1316 default:
1317 /* Nothing to do */
1318 break;
1319 }
1320 }
1321 }
1322
1323 if (progress) {
1324 nir_metadata_preserve(impl, nir_metadata_block_index |
1325 nir_metadata_dominance);
1326 }
1327
1328 return progress;
1329 }
1330
1331 bool
1332 nir_lower_explicit_io(nir_shader *shader, nir_variable_mode modes,
1333 nir_address_format addr_format)
1334 {
1335 bool progress = false;
1336
1337 nir_foreach_function(function, shader) {
1338 if (function->impl &&
1339 nir_lower_explicit_io_impl(function->impl, modes, addr_format))
1340 progress = true;
1341 }
1342
1343 return progress;
1344 }
1345
1346 static bool
1347 nir_lower_vars_to_explicit_types_impl(nir_function_impl *impl,
1348 nir_variable_mode modes,
1349 glsl_type_size_align_func type_info)
1350 {
1351 bool progress = false;
1352
1353 nir_foreach_block(block, impl) {
1354 nir_foreach_instr(instr, block) {
1355 if (instr->type != nir_instr_type_deref)
1356 continue;
1357
1358 nir_deref_instr *deref = nir_instr_as_deref(instr);
1359 if (!(deref->mode & modes))
1360 continue;
1361
1362 unsigned size, alignment;
1363 const struct glsl_type *new_type =
1364 glsl_get_explicit_type_for_size_align(deref->type, type_info, &size, &alignment);
1365 if (new_type != deref->type) {
1366 progress = true;
1367 deref->type = new_type;
1368 }
1369 if (deref->deref_type == nir_deref_type_cast) {
1370 /* See also glsl_type::get_explicit_type_for_size_align() */
1371 unsigned new_stride = align(size, alignment);
1372 if (new_stride != deref->cast.ptr_stride) {
1373 deref->cast.ptr_stride = new_stride;
1374 progress = true;
1375 }
1376 }
1377 }
1378 }
1379
1380 if (progress) {
1381 nir_metadata_preserve(impl, nir_metadata_block_index |
1382 nir_metadata_dominance |
1383 nir_metadata_live_ssa_defs |
1384 nir_metadata_loop_analysis);
1385 }
1386
1387 return progress;
1388 }
1389
1390 static bool
1391 lower_vars_to_explicit(nir_shader *shader,
1392 struct exec_list *vars, nir_variable_mode mode,
1393 glsl_type_size_align_func type_info)
1394 {
1395 bool progress = false;
1396 unsigned offset = 0;
1397 nir_foreach_variable(var, vars) {
1398 unsigned size, align;
1399 const struct glsl_type *explicit_type =
1400 glsl_get_explicit_type_for_size_align(var->type, type_info, &size, &align);
1401
1402 if (explicit_type != var->type) {
1403 progress = true;
1404 var->type = explicit_type;
1405 }
1406
1407 var->data.driver_location = ALIGN_POT(offset, align);
1408 offset = var->data.driver_location + size;
1409 }
1410
1411 if (mode == nir_var_mem_shared) {
1412 shader->info.cs.shared_size = offset;
1413 shader->num_shared = offset;
1414 }
1415
1416 return progress;
1417 }
1418
1419 bool
1420 nir_lower_vars_to_explicit_types(nir_shader *shader,
1421 nir_variable_mode modes,
1422 glsl_type_size_align_func type_info)
1423 {
1424 /* TODO: Situations which need to be handled to support more modes:
1425 * - row-major matrices
1426 * - compact shader inputs/outputs
1427 * - interface types
1428 */
1429 ASSERTED nir_variable_mode supported = nir_var_mem_shared |
1430 nir_var_shader_temp | nir_var_function_temp;
1431 assert(!(modes & ~supported) && "unsupported");
1432
1433 bool progress = false;
1434
1435 if (modes & nir_var_mem_shared)
1436 progress |= lower_vars_to_explicit(shader, &shader->shared, nir_var_mem_shared, type_info);
1437 if (modes & nir_var_shader_temp)
1438 progress |= lower_vars_to_explicit(shader, &shader->globals, nir_var_shader_temp, type_info);
1439
1440 nir_foreach_function(function, shader) {
1441 if (function->impl) {
1442 if (modes & nir_var_function_temp)
1443 progress |= lower_vars_to_explicit(shader, &function->impl->locals, nir_var_function_temp, type_info);
1444
1445 progress |= nir_lower_vars_to_explicit_types_impl(function->impl, modes, type_info);
1446 }
1447 }
1448
1449 return progress;
1450 }
1451
1452 /**
1453 * Return the offset source for a load/store intrinsic.
1454 */
1455 nir_src *
1456 nir_get_io_offset_src(nir_intrinsic_instr *instr)
1457 {
1458 switch (instr->intrinsic) {
1459 case nir_intrinsic_load_input:
1460 case nir_intrinsic_load_output:
1461 case nir_intrinsic_load_shared:
1462 case nir_intrinsic_load_uniform:
1463 case nir_intrinsic_load_global:
1464 case nir_intrinsic_load_scratch:
1465 case nir_intrinsic_load_fs_input_interp_deltas:
1466 return &instr->src[0];
1467 case nir_intrinsic_load_ubo:
1468 case nir_intrinsic_load_ssbo:
1469 case nir_intrinsic_load_per_vertex_input:
1470 case nir_intrinsic_load_per_vertex_output:
1471 case nir_intrinsic_load_interpolated_input:
1472 case nir_intrinsic_store_output:
1473 case nir_intrinsic_store_shared:
1474 case nir_intrinsic_store_global:
1475 case nir_intrinsic_store_scratch:
1476 case nir_intrinsic_ssbo_atomic_add:
1477 case nir_intrinsic_ssbo_atomic_imin:
1478 case nir_intrinsic_ssbo_atomic_umin:
1479 case nir_intrinsic_ssbo_atomic_imax:
1480 case nir_intrinsic_ssbo_atomic_umax:
1481 case nir_intrinsic_ssbo_atomic_and:
1482 case nir_intrinsic_ssbo_atomic_or:
1483 case nir_intrinsic_ssbo_atomic_xor:
1484 case nir_intrinsic_ssbo_atomic_exchange:
1485 case nir_intrinsic_ssbo_atomic_comp_swap:
1486 case nir_intrinsic_ssbo_atomic_fadd:
1487 case nir_intrinsic_ssbo_atomic_fmin:
1488 case nir_intrinsic_ssbo_atomic_fmax:
1489 case nir_intrinsic_ssbo_atomic_fcomp_swap:
1490 return &instr->src[1];
1491 case nir_intrinsic_store_ssbo:
1492 case nir_intrinsic_store_per_vertex_output:
1493 return &instr->src[2];
1494 default:
1495 return NULL;
1496 }
1497 }
1498
1499 /**
1500 * Return the vertex index source for a load/store per_vertex intrinsic.
1501 */
1502 nir_src *
1503 nir_get_io_vertex_index_src(nir_intrinsic_instr *instr)
1504 {
1505 switch (instr->intrinsic) {
1506 case nir_intrinsic_load_per_vertex_input:
1507 case nir_intrinsic_load_per_vertex_output:
1508 return &instr->src[0];
1509 case nir_intrinsic_store_per_vertex_output:
1510 return &instr->src[1];
1511 default:
1512 return NULL;
1513 }
1514 }
1515
1516 /**
1517 * Return the numeric constant that identify a NULL pointer for each address
1518 * format.
1519 */
1520 const nir_const_value *
1521 nir_address_format_null_value(nir_address_format addr_format)
1522 {
1523 const static nir_const_value null_values[][NIR_MAX_VEC_COMPONENTS] = {
1524 [nir_address_format_32bit_global] = {{0}},
1525 [nir_address_format_64bit_global] = {{0}},
1526 [nir_address_format_64bit_bounded_global] = {{0}},
1527 [nir_address_format_32bit_index_offset] = {{.u32 = ~0}, {.u32 = ~0}},
1528 [nir_address_format_vec2_index_32bit_offset] = {{.u32 = ~0}, {.u32 = ~0}, {.u32 = ~0}},
1529 [nir_address_format_32bit_offset] = {{.u32 = ~0}},
1530 [nir_address_format_logical] = {{.u32 = ~0}},
1531 };
1532
1533 assert(addr_format < ARRAY_SIZE(null_values));
1534 return null_values[addr_format];
1535 }
1536
1537 nir_ssa_def *
1538 nir_build_addr_ieq(nir_builder *b, nir_ssa_def *addr0, nir_ssa_def *addr1,
1539 nir_address_format addr_format)
1540 {
1541 switch (addr_format) {
1542 case nir_address_format_32bit_global:
1543 case nir_address_format_64bit_global:
1544 case nir_address_format_64bit_bounded_global:
1545 case nir_address_format_32bit_index_offset:
1546 case nir_address_format_vec2_index_32bit_offset:
1547 case nir_address_format_32bit_offset:
1548 return nir_ball_iequal(b, addr0, addr1);
1549
1550 case nir_address_format_logical:
1551 unreachable("Unsupported address format");
1552 }
1553
1554 unreachable("Invalid address format");
1555 }
1556
1557 nir_ssa_def *
1558 nir_build_addr_isub(nir_builder *b, nir_ssa_def *addr0, nir_ssa_def *addr1,
1559 nir_address_format addr_format)
1560 {
1561 switch (addr_format) {
1562 case nir_address_format_32bit_global:
1563 case nir_address_format_64bit_global:
1564 case nir_address_format_32bit_offset:
1565 assert(addr0->num_components == 1);
1566 assert(addr1->num_components == 1);
1567 return nir_isub(b, addr0, addr1);
1568
1569 case nir_address_format_64bit_bounded_global:
1570 return nir_isub(b, addr_to_global(b, addr0, addr_format),
1571 addr_to_global(b, addr1, addr_format));
1572
1573 case nir_address_format_32bit_index_offset:
1574 assert(addr0->num_components == 2);
1575 assert(addr1->num_components == 2);
1576 /* Assume the same buffer index. */
1577 return nir_isub(b, nir_channel(b, addr0, 1), nir_channel(b, addr1, 1));
1578
1579 case nir_address_format_vec2_index_32bit_offset:
1580 assert(addr0->num_components == 3);
1581 assert(addr1->num_components == 3);
1582 /* Assume the same buffer index. */
1583 return nir_isub(b, nir_channel(b, addr0, 2), nir_channel(b, addr1, 2));
1584
1585 case nir_address_format_logical:
1586 unreachable("Unsupported address format");
1587 }
1588
1589 unreachable("Invalid address format");
1590 }
1591
1592 static bool
1593 is_input(nir_intrinsic_instr *intrin)
1594 {
1595 return intrin->intrinsic == nir_intrinsic_load_input ||
1596 intrin->intrinsic == nir_intrinsic_load_per_vertex_input ||
1597 intrin->intrinsic == nir_intrinsic_load_interpolated_input ||
1598 intrin->intrinsic == nir_intrinsic_load_fs_input_interp_deltas;
1599 }
1600
1601 static bool
1602 is_output(nir_intrinsic_instr *intrin)
1603 {
1604 return intrin->intrinsic == nir_intrinsic_load_output ||
1605 intrin->intrinsic == nir_intrinsic_load_per_vertex_output ||
1606 intrin->intrinsic == nir_intrinsic_store_output ||
1607 intrin->intrinsic == nir_intrinsic_store_per_vertex_output;
1608 }
1609
1610
1611 /**
1612 * This pass adds constant offsets to instr->const_index[0] for input/output
1613 * intrinsics, and resets the offset source to 0. Non-constant offsets remain
1614 * unchanged - since we don't know what part of a compound variable is
1615 * accessed, we allocate storage for the entire thing. For drivers that use
1616 * nir_lower_io_to_temporaries() before nir_lower_io(), this guarantees that
1617 * the offset source will be 0, so that they don't have to add it in manually.
1618 */
1619
1620 static bool
1621 add_const_offset_to_base_block(nir_block *block, nir_builder *b,
1622 nir_variable_mode mode)
1623 {
1624 bool progress = false;
1625 nir_foreach_instr_safe(instr, block) {
1626 if (instr->type != nir_instr_type_intrinsic)
1627 continue;
1628
1629 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
1630
1631 if ((mode == nir_var_shader_in && is_input(intrin)) ||
1632 (mode == nir_var_shader_out && is_output(intrin))) {
1633 nir_src *offset = nir_get_io_offset_src(intrin);
1634
1635 if (nir_src_is_const(*offset)) {
1636 intrin->const_index[0] += nir_src_as_uint(*offset);
1637 b->cursor = nir_before_instr(&intrin->instr);
1638 nir_instr_rewrite_src(&intrin->instr, offset,
1639 nir_src_for_ssa(nir_imm_int(b, 0)));
1640 progress = true;
1641 }
1642 }
1643 }
1644
1645 return progress;
1646 }
1647
1648 bool
1649 nir_io_add_const_offset_to_base(nir_shader *nir, nir_variable_mode mode)
1650 {
1651 bool progress = false;
1652
1653 nir_foreach_function(f, nir) {
1654 if (f->impl) {
1655 nir_builder b;
1656 nir_builder_init(&b, f->impl);
1657 nir_foreach_block(block, f->impl) {
1658 progress |= add_const_offset_to_base_block(block, &b, mode);
1659 }
1660 }
1661 }
1662
1663 return progress;
1664 }
1665