2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Connor Abbott (cwabbott0@gmail.com)
25 * Jason Ekstrand (jason@jlekstrand.net)
30 * This lowering pass converts references to input/output variables with
31 * loads/stores to actual input/output intrinsics.
35 #include "nir_builder.h"
36 #include "nir_deref.h"
38 #include "util/u_math.h"
40 struct lower_io_state
{
43 int (*type_size
)(const struct glsl_type
*type
, bool);
44 nir_variable_mode modes
;
45 nir_lower_io_options options
;
48 static nir_intrinsic_op
49 ssbo_atomic_for_deref(nir_intrinsic_op deref_op
)
52 #define OP(O) case nir_intrinsic_deref_##O: return nir_intrinsic_ssbo_##O;
69 unreachable("Invalid SSBO atomic");
73 static nir_intrinsic_op
74 global_atomic_for_deref(nir_intrinsic_op deref_op
)
77 #define OP(O) case nir_intrinsic_deref_##O: return nir_intrinsic_global_##O;
94 unreachable("Invalid SSBO atomic");
98 static nir_intrinsic_op
99 shared_atomic_for_deref(nir_intrinsic_op deref_op
)
102 #define OP(O) case nir_intrinsic_deref_##O: return nir_intrinsic_shared_##O;
116 OP(atomic_fcomp_swap
)
119 unreachable("Invalid shared atomic");
124 nir_assign_var_locations(nir_shader
*shader
, nir_variable_mode mode
,
126 int (*type_size
)(const struct glsl_type
*, bool))
128 unsigned location
= 0;
130 nir_foreach_variable_with_modes(var
, shader
, mode
) {
131 var
->data
.driver_location
= location
;
132 bool bindless_type_size
= var
->data
.mode
== nir_var_shader_in
||
133 var
->data
.mode
== nir_var_shader_out
||
135 location
+= type_size(var
->type
, bindless_type_size
);
142 * Return true if the given variable is a per-vertex input/output array.
143 * (such as geometry shader inputs).
146 nir_is_per_vertex_io(const nir_variable
*var
, gl_shader_stage stage
)
148 if (var
->data
.patch
|| !glsl_type_is_array(var
->type
))
151 if (var
->data
.mode
== nir_var_shader_in
)
152 return stage
== MESA_SHADER_GEOMETRY
||
153 stage
== MESA_SHADER_TESS_CTRL
||
154 stage
== MESA_SHADER_TESS_EVAL
;
156 if (var
->data
.mode
== nir_var_shader_out
)
157 return stage
== MESA_SHADER_TESS_CTRL
;
162 static unsigned get_number_of_slots(struct lower_io_state
*state
,
163 const nir_variable
*var
)
165 const struct glsl_type
*type
= var
->type
;
167 if (nir_is_per_vertex_io(var
, state
->builder
.shader
->info
.stage
)) {
168 assert(glsl_type_is_array(type
));
169 type
= glsl_get_array_element(type
);
172 return state
->type_size(type
, var
->data
.bindless
);
176 get_io_offset(nir_builder
*b
, nir_deref_instr
*deref
,
177 nir_ssa_def
**vertex_index
,
178 int (*type_size
)(const struct glsl_type
*, bool),
179 unsigned *component
, bool bts
)
182 nir_deref_path_init(&path
, deref
, NULL
);
184 assert(path
.path
[0]->deref_type
== nir_deref_type_var
);
185 nir_deref_instr
**p
= &path
.path
[1];
187 /* For per-vertex input arrays (i.e. geometry shader inputs), keep the
188 * outermost array index separate. Process the rest normally.
190 if (vertex_index
!= NULL
) {
191 assert((*p
)->deref_type
== nir_deref_type_array
);
192 *vertex_index
= nir_ssa_for_src(b
, (*p
)->arr
.index
, 1);
196 if (path
.path
[0]->var
->data
.compact
) {
197 assert((*p
)->deref_type
== nir_deref_type_array
);
198 assert(glsl_type_is_scalar((*p
)->type
));
200 /* We always lower indirect dereferences for "compact" array vars. */
201 const unsigned index
= nir_src_as_uint((*p
)->arr
.index
);
202 const unsigned total_offset
= *component
+ index
;
203 const unsigned slot_offset
= total_offset
/ 4;
204 *component
= total_offset
% 4;
205 return nir_imm_int(b
, type_size(glsl_vec4_type(), bts
) * slot_offset
);
208 /* Just emit code and let constant-folding go to town */
209 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
212 if ((*p
)->deref_type
== nir_deref_type_array
) {
213 unsigned size
= type_size((*p
)->type
, bts
);
216 nir_amul_imm(b
, nir_ssa_for_src(b
, (*p
)->arr
.index
, 1), size
);
218 offset
= nir_iadd(b
, offset
, mul
);
219 } else if ((*p
)->deref_type
== nir_deref_type_struct
) {
220 /* p starts at path[1], so this is safe */
221 nir_deref_instr
*parent
= *(p
- 1);
223 unsigned field_offset
= 0;
224 for (unsigned i
= 0; i
< (*p
)->strct
.index
; i
++) {
225 field_offset
+= type_size(glsl_get_struct_field(parent
->type
, i
), bts
);
227 offset
= nir_iadd_imm(b
, offset
, field_offset
);
229 unreachable("Unsupported deref type");
233 nir_deref_path_finish(&path
);
239 emit_load(struct lower_io_state
*state
,
240 nir_ssa_def
*vertex_index
, nir_variable
*var
, nir_ssa_def
*offset
,
241 unsigned component
, unsigned num_components
, unsigned bit_size
,
244 nir_builder
*b
= &state
->builder
;
245 const nir_shader
*nir
= b
->shader
;
246 nir_variable_mode mode
= var
->data
.mode
;
247 nir_ssa_def
*barycentric
= NULL
;
251 case nir_var_shader_in
:
252 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
253 nir
->options
->use_interpolated_input_intrinsics
&&
254 var
->data
.interpolation
!= INTERP_MODE_FLAT
) {
255 if (var
->data
.interpolation
== INTERP_MODE_EXPLICIT
) {
256 assert(vertex_index
!= NULL
);
257 op
= nir_intrinsic_load_input_vertex
;
259 assert(vertex_index
== NULL
);
261 nir_intrinsic_op bary_op
;
262 if (var
->data
.sample
||
263 (state
->options
& nir_lower_io_force_sample_interpolation
))
264 bary_op
= nir_intrinsic_load_barycentric_sample
;
265 else if (var
->data
.centroid
)
266 bary_op
= nir_intrinsic_load_barycentric_centroid
;
268 bary_op
= nir_intrinsic_load_barycentric_pixel
;
270 barycentric
= nir_load_barycentric(&state
->builder
, bary_op
,
271 var
->data
.interpolation
);
272 op
= nir_intrinsic_load_interpolated_input
;
275 op
= vertex_index
? nir_intrinsic_load_per_vertex_input
:
276 nir_intrinsic_load_input
;
279 case nir_var_shader_out
:
280 op
= vertex_index
? nir_intrinsic_load_per_vertex_output
:
281 nir_intrinsic_load_output
;
283 case nir_var_uniform
:
284 op
= nir_intrinsic_load_uniform
;
287 unreachable("Unknown variable mode");
290 nir_intrinsic_instr
*load
=
291 nir_intrinsic_instr_create(state
->builder
.shader
, op
);
292 load
->num_components
= num_components
;
294 nir_intrinsic_set_base(load
, var
->data
.driver_location
);
295 if (mode
== nir_var_shader_in
|| mode
== nir_var_shader_out
)
296 nir_intrinsic_set_component(load
, component
);
298 if (load
->intrinsic
== nir_intrinsic_load_uniform
)
299 nir_intrinsic_set_range(load
,
300 state
->type_size(var
->type
, var
->data
.bindless
));
302 if (load
->intrinsic
== nir_intrinsic_load_input
||
303 load
->intrinsic
== nir_intrinsic_load_input_vertex
||
304 load
->intrinsic
== nir_intrinsic_load_uniform
)
305 nir_intrinsic_set_type(load
, type
);
307 if (load
->intrinsic
!= nir_intrinsic_load_uniform
) {
308 nir_io_semantics semantics
= {0};
309 semantics
.location
= var
->data
.location
;
310 semantics
.num_slots
= get_number_of_slots(state
, var
);
311 semantics
.fb_fetch_output
= var
->data
.fb_fetch_output
;
312 nir_intrinsic_set_io_semantics(load
, semantics
);
316 load
->src
[0] = nir_src_for_ssa(vertex_index
);
317 load
->src
[1] = nir_src_for_ssa(offset
);
318 } else if (barycentric
) {
319 load
->src
[0] = nir_src_for_ssa(barycentric
);
320 load
->src
[1] = nir_src_for_ssa(offset
);
322 load
->src
[0] = nir_src_for_ssa(offset
);
325 nir_ssa_dest_init(&load
->instr
, &load
->dest
,
326 num_components
, bit_size
, NULL
);
327 nir_builder_instr_insert(b
, &load
->instr
);
329 return &load
->dest
.ssa
;
333 lower_load(nir_intrinsic_instr
*intrin
, struct lower_io_state
*state
,
334 nir_ssa_def
*vertex_index
, nir_variable
*var
, nir_ssa_def
*offset
,
335 unsigned component
, const struct glsl_type
*type
)
337 assert(intrin
->dest
.is_ssa
);
338 if (intrin
->dest
.ssa
.bit_size
== 64 &&
339 (state
->options
& nir_lower_io_lower_64bit_to_32
)) {
340 nir_builder
*b
= &state
->builder
;
342 const unsigned slot_size
= state
->type_size(glsl_dvec_type(2), false);
344 nir_ssa_def
*comp64
[4];
345 assert(component
== 0 || component
== 2);
346 unsigned dest_comp
= 0;
347 while (dest_comp
< intrin
->dest
.ssa
.num_components
) {
348 const unsigned num_comps
=
349 MIN2(intrin
->dest
.ssa
.num_components
- dest_comp
,
350 (4 - component
) / 2);
352 nir_ssa_def
*data32
=
353 emit_load(state
, vertex_index
, var
, offset
, component
,
354 num_comps
* 2, 32, nir_type_uint32
);
355 for (unsigned i
= 0; i
< num_comps
; i
++) {
356 comp64
[dest_comp
+ i
] =
357 nir_pack_64_2x32(b
, nir_channels(b
, data32
, 3 << (i
* 2)));
360 /* Only the first store has a component offset */
362 dest_comp
+= num_comps
;
363 offset
= nir_iadd_imm(b
, offset
, slot_size
);
366 return nir_vec(b
, comp64
, intrin
->dest
.ssa
.num_components
);
367 } else if (intrin
->dest
.ssa
.bit_size
== 1) {
368 /* Booleans are 32-bit */
369 assert(glsl_type_is_boolean(type
));
370 return nir_b2b1(&state
->builder
,
371 emit_load(state
, vertex_index
, var
, offset
, component
,
372 intrin
->dest
.ssa
.num_components
, 32,
375 return emit_load(state
, vertex_index
, var
, offset
, component
,
376 intrin
->dest
.ssa
.num_components
,
377 intrin
->dest
.ssa
.bit_size
,
378 nir_get_nir_type_for_glsl_type(type
));
383 emit_store(struct lower_io_state
*state
, nir_ssa_def
*data
,
384 nir_ssa_def
*vertex_index
, nir_variable
*var
, nir_ssa_def
*offset
,
385 unsigned component
, unsigned num_components
,
386 nir_component_mask_t write_mask
, nir_alu_type type
)
388 nir_builder
*b
= &state
->builder
;
389 nir_variable_mode mode
= var
->data
.mode
;
391 assert(mode
== nir_var_shader_out
);
393 op
= vertex_index
? nir_intrinsic_store_per_vertex_output
:
394 nir_intrinsic_store_output
;
396 nir_intrinsic_instr
*store
=
397 nir_intrinsic_instr_create(state
->builder
.shader
, op
);
398 store
->num_components
= num_components
;
400 store
->src
[0] = nir_src_for_ssa(data
);
402 nir_intrinsic_set_base(store
, var
->data
.driver_location
);
404 if (mode
== nir_var_shader_out
)
405 nir_intrinsic_set_component(store
, component
);
407 if (store
->intrinsic
== nir_intrinsic_store_output
)
408 nir_intrinsic_set_type(store
, type
);
410 nir_intrinsic_set_write_mask(store
, write_mask
);
413 store
->src
[1] = nir_src_for_ssa(vertex_index
);
415 store
->src
[vertex_index
? 2 : 1] = nir_src_for_ssa(offset
);
417 unsigned gs_streams
= 0;
418 if (state
->builder
.shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
419 if (var
->data
.stream
& NIR_STREAM_PACKED
) {
420 gs_streams
= var
->data
.stream
& ~NIR_STREAM_PACKED
;
422 assert(var
->data
.stream
< 4);
424 for (unsigned i
= 0; i
< num_components
; ++i
)
425 gs_streams
|= var
->data
.stream
<< (2 * i
);
429 nir_io_semantics semantics
= {0};
430 semantics
.location
= var
->data
.location
;
431 semantics
.num_slots
= get_number_of_slots(state
, var
);
432 semantics
.dual_source_blend_index
= var
->data
.index
;
433 semantics
.gs_streams
= gs_streams
;
434 nir_intrinsic_set_io_semantics(store
, semantics
);
436 nir_builder_instr_insert(b
, &store
->instr
);
440 lower_store(nir_intrinsic_instr
*intrin
, struct lower_io_state
*state
,
441 nir_ssa_def
*vertex_index
, nir_variable
*var
, nir_ssa_def
*offset
,
442 unsigned component
, const struct glsl_type
*type
)
444 assert(intrin
->src
[1].is_ssa
);
445 if (intrin
->src
[1].ssa
->bit_size
== 64 &&
446 (state
->options
& nir_lower_io_lower_64bit_to_32
)) {
447 nir_builder
*b
= &state
->builder
;
449 const unsigned slot_size
= state
->type_size(glsl_dvec_type(2), false);
451 assert(component
== 0 || component
== 2);
452 unsigned src_comp
= 0;
453 nir_component_mask_t write_mask
= nir_intrinsic_write_mask(intrin
);
454 while (src_comp
< intrin
->num_components
) {
455 const unsigned num_comps
=
456 MIN2(intrin
->num_components
- src_comp
,
457 (4 - component
) / 2);
459 if (write_mask
& BITFIELD_MASK(num_comps
)) {
461 nir_channels(b
, intrin
->src
[1].ssa
,
462 BITFIELD_RANGE(src_comp
, num_comps
));
463 nir_ssa_def
*data32
= nir_bitcast_vector(b
, data
, 32);
465 nir_component_mask_t write_mask32
= 0;
466 for (unsigned i
= 0; i
< num_comps
; i
++) {
467 if (write_mask
& BITFIELD_MASK(num_comps
) & (1 << i
))
468 write_mask32
|= 3 << (i
* 2);
471 emit_store(state
, data32
, vertex_index
, var
, offset
,
472 component
, data32
->num_components
, write_mask32
,
476 /* Only the first store has a component offset */
478 src_comp
+= num_comps
;
479 write_mask
>>= num_comps
;
480 offset
= nir_iadd_imm(b
, offset
, slot_size
);
482 } else if (intrin
->dest
.ssa
.bit_size
== 1) {
483 /* Booleans are 32-bit */
484 assert(glsl_type_is_boolean(type
));
485 nir_ssa_def
*b32_val
= nir_b2b32(&state
->builder
, intrin
->src
[1].ssa
);
486 emit_store(state
, b32_val
, vertex_index
, var
, offset
,
487 component
, intrin
->num_components
,
488 nir_intrinsic_write_mask(intrin
),
491 emit_store(state
, intrin
->src
[1].ssa
, vertex_index
, var
, offset
,
492 component
, intrin
->num_components
,
493 nir_intrinsic_write_mask(intrin
),
494 nir_get_nir_type_for_glsl_type(type
));
499 lower_interpolate_at(nir_intrinsic_instr
*intrin
, struct lower_io_state
*state
,
500 nir_variable
*var
, nir_ssa_def
*offset
, unsigned component
,
501 const struct glsl_type
*type
)
503 nir_builder
*b
= &state
->builder
;
504 assert(var
->data
.mode
== nir_var_shader_in
);
506 /* Ignore interpolateAt() for flat variables - flat is flat. Lower
507 * interpolateAtVertex() for explicit variables.
509 if (var
->data
.interpolation
== INTERP_MODE_FLAT
||
510 var
->data
.interpolation
== INTERP_MODE_EXPLICIT
) {
511 nir_ssa_def
*vertex_index
= NULL
;
513 if (var
->data
.interpolation
== INTERP_MODE_EXPLICIT
) {
514 assert(intrin
->intrinsic
== nir_intrinsic_interp_deref_at_vertex
);
515 vertex_index
= intrin
->src
[1].ssa
;
518 return lower_load(intrin
, state
, vertex_index
, var
, offset
, component
, type
);
521 /* None of the supported APIs allow interpolation on 64-bit things */
522 assert(intrin
->dest
.is_ssa
&& intrin
->dest
.ssa
.bit_size
<= 32);
524 nir_intrinsic_op bary_op
;
525 switch (intrin
->intrinsic
) {
526 case nir_intrinsic_interp_deref_at_centroid
:
527 bary_op
= (state
->options
& nir_lower_io_force_sample_interpolation
) ?
528 nir_intrinsic_load_barycentric_sample
:
529 nir_intrinsic_load_barycentric_centroid
;
531 case nir_intrinsic_interp_deref_at_sample
:
532 bary_op
= nir_intrinsic_load_barycentric_at_sample
;
534 case nir_intrinsic_interp_deref_at_offset
:
535 bary_op
= nir_intrinsic_load_barycentric_at_offset
;
538 unreachable("Bogus interpolateAt() intrinsic.");
541 nir_intrinsic_instr
*bary_setup
=
542 nir_intrinsic_instr_create(state
->builder
.shader
, bary_op
);
544 nir_ssa_dest_init(&bary_setup
->instr
, &bary_setup
->dest
, 2, 32, NULL
);
545 nir_intrinsic_set_interp_mode(bary_setup
, var
->data
.interpolation
);
547 if (intrin
->intrinsic
== nir_intrinsic_interp_deref_at_sample
||
548 intrin
->intrinsic
== nir_intrinsic_interp_deref_at_offset
||
549 intrin
->intrinsic
== nir_intrinsic_interp_deref_at_vertex
)
550 nir_src_copy(&bary_setup
->src
[0], &intrin
->src
[1], bary_setup
);
552 nir_builder_instr_insert(b
, &bary_setup
->instr
);
554 nir_intrinsic_instr
*load
=
555 nir_intrinsic_instr_create(state
->builder
.shader
,
556 nir_intrinsic_load_interpolated_input
);
557 load
->num_components
= intrin
->num_components
;
559 nir_intrinsic_set_base(load
, var
->data
.driver_location
);
560 nir_intrinsic_set_component(load
, component
);
562 nir_io_semantics semantics
= {0};
563 semantics
.location
= var
->data
.location
;
564 semantics
.num_slots
= get_number_of_slots(state
, var
);
565 nir_intrinsic_set_io_semantics(load
, semantics
);
567 load
->src
[0] = nir_src_for_ssa(&bary_setup
->dest
.ssa
);
568 load
->src
[1] = nir_src_for_ssa(offset
);
570 assert(intrin
->dest
.is_ssa
);
571 nir_ssa_dest_init(&load
->instr
, &load
->dest
,
572 intrin
->dest
.ssa
.num_components
,
573 intrin
->dest
.ssa
.bit_size
, NULL
);
574 nir_builder_instr_insert(b
, &load
->instr
);
576 return &load
->dest
.ssa
;
580 nir_lower_io_block(nir_block
*block
,
581 struct lower_io_state
*state
)
583 nir_builder
*b
= &state
->builder
;
584 const nir_shader_compiler_options
*options
= b
->shader
->options
;
585 bool progress
= false;
587 nir_foreach_instr_safe(instr
, block
) {
588 if (instr
->type
!= nir_instr_type_intrinsic
)
591 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
593 switch (intrin
->intrinsic
) {
594 case nir_intrinsic_load_deref
:
595 case nir_intrinsic_store_deref
:
596 /* We can lower the io for this nir instrinsic */
598 case nir_intrinsic_interp_deref_at_centroid
:
599 case nir_intrinsic_interp_deref_at_sample
:
600 case nir_intrinsic_interp_deref_at_offset
:
601 case nir_intrinsic_interp_deref_at_vertex
:
602 /* We can optionally lower these to load_interpolated_input */
603 if (options
->use_interpolated_input_intrinsics
)
606 /* We can't lower the io for this nir instrinsic, so skip it */
610 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
612 nir_variable_mode mode
= deref
->mode
;
613 assert(util_is_power_of_two_nonzero(mode
));
614 if ((state
->modes
& mode
) == 0)
617 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
619 b
->cursor
= nir_before_instr(instr
);
621 const bool per_vertex
= nir_is_per_vertex_io(var
, b
->shader
->info
.stage
);
624 nir_ssa_def
*vertex_index
= NULL
;
625 unsigned component_offset
= var
->data
.location_frac
;
626 bool bindless_type_size
= mode
== nir_var_shader_in
||
627 mode
== nir_var_shader_out
||
630 offset
= get_io_offset(b
, deref
, per_vertex
? &vertex_index
: NULL
,
631 state
->type_size
, &component_offset
,
634 nir_ssa_def
*replacement
= NULL
;
636 switch (intrin
->intrinsic
) {
637 case nir_intrinsic_load_deref
:
638 replacement
= lower_load(intrin
, state
, vertex_index
, var
, offset
,
639 component_offset
, deref
->type
);
642 case nir_intrinsic_store_deref
:
643 lower_store(intrin
, state
, vertex_index
, var
, offset
,
644 component_offset
, deref
->type
);
647 case nir_intrinsic_interp_deref_at_centroid
:
648 case nir_intrinsic_interp_deref_at_sample
:
649 case nir_intrinsic_interp_deref_at_offset
:
650 case nir_intrinsic_interp_deref_at_vertex
:
651 assert(vertex_index
== NULL
);
652 replacement
= lower_interpolate_at(intrin
, state
, var
, offset
,
653 component_offset
, deref
->type
);
661 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
662 nir_src_for_ssa(replacement
));
664 nir_instr_remove(&intrin
->instr
);
672 nir_lower_io_impl(nir_function_impl
*impl
,
673 nir_variable_mode modes
,
674 int (*type_size
)(const struct glsl_type
*, bool),
675 nir_lower_io_options options
)
677 struct lower_io_state state
;
678 bool progress
= false;
680 nir_builder_init(&state
.builder
, impl
);
681 state
.dead_ctx
= ralloc_context(NULL
);
683 state
.type_size
= type_size
;
684 state
.options
= options
;
686 ASSERTED nir_variable_mode supported_modes
=
687 nir_var_shader_in
| nir_var_shader_out
| nir_var_uniform
;
688 assert(!(modes
& ~supported_modes
));
690 nir_foreach_block(block
, impl
) {
691 progress
|= nir_lower_io_block(block
, &state
);
694 ralloc_free(state
.dead_ctx
);
696 nir_metadata_preserve(impl
, nir_metadata_block_index
|
697 nir_metadata_dominance
);
701 /** Lower load/store_deref intrinsics on I/O variables to offset-based intrinsics
703 * This pass is intended to be used for cross-stage shader I/O and driver-
704 * managed uniforms to turn deref-based access into a simpler model using
705 * locations or offsets. For fragment shader inputs, it can optionally turn
706 * load_deref into an explicit interpolation using barycentrics coming from
707 * one of the load_barycentric_* intrinsics. This pass requires that all
708 * deref chains are complete and contain no casts.
711 nir_lower_io(nir_shader
*shader
, nir_variable_mode modes
,
712 int (*type_size
)(const struct glsl_type
*, bool),
713 nir_lower_io_options options
)
715 bool progress
= false;
717 nir_foreach_function(function
, shader
) {
718 if (function
->impl
) {
719 progress
|= nir_lower_io_impl(function
->impl
, modes
,
728 type_scalar_size_bytes(const struct glsl_type
*type
)
730 assert(glsl_type_is_vector_or_scalar(type
) ||
731 glsl_type_is_matrix(type
));
732 return glsl_type_is_boolean(type
) ? 4 : glsl_get_bit_size(type
) / 8;
736 build_addr_iadd(nir_builder
*b
, nir_ssa_def
*addr
,
737 nir_address_format addr_format
, nir_ssa_def
*offset
)
739 assert(offset
->num_components
== 1);
741 switch (addr_format
) {
742 case nir_address_format_32bit_global
:
743 case nir_address_format_64bit_global
:
744 case nir_address_format_32bit_offset
:
745 assert(addr
->bit_size
== offset
->bit_size
);
746 assert(addr
->num_components
== 1);
747 return nir_iadd(b
, addr
, offset
);
749 case nir_address_format_32bit_offset_as_64bit
:
750 assert(addr
->num_components
== 1);
751 assert(offset
->bit_size
== 32);
752 return nir_u2u64(b
, nir_iadd(b
, nir_u2u32(b
, addr
), offset
));
754 case nir_address_format_64bit_bounded_global
:
755 assert(addr
->num_components
== 4);
756 assert(addr
->bit_size
== offset
->bit_size
);
757 return nir_vec4(b
, nir_channel(b
, addr
, 0),
758 nir_channel(b
, addr
, 1),
759 nir_channel(b
, addr
, 2),
760 nir_iadd(b
, nir_channel(b
, addr
, 3), offset
));
762 case nir_address_format_32bit_index_offset
:
763 assert(addr
->num_components
== 2);
764 assert(addr
->bit_size
== offset
->bit_size
);
765 return nir_vec2(b
, nir_channel(b
, addr
, 0),
766 nir_iadd(b
, nir_channel(b
, addr
, 1), offset
));
768 case nir_address_format_32bit_index_offset_pack64
:
769 assert(addr
->num_components
== 1);
770 assert(offset
->bit_size
== 32);
771 return nir_pack_64_2x32_split(b
,
772 nir_iadd(b
, nir_unpack_64_2x32_split_x(b
, addr
), offset
),
773 nir_unpack_64_2x32_split_y(b
, addr
));
775 case nir_address_format_vec2_index_32bit_offset
:
776 assert(addr
->num_components
== 3);
777 assert(offset
->bit_size
== 32);
778 return nir_vec3(b
, nir_channel(b
, addr
, 0), nir_channel(b
, addr
, 1),
779 nir_iadd(b
, nir_channel(b
, addr
, 2), offset
));
781 case nir_address_format_logical
:
782 unreachable("Unsupported address format");
784 unreachable("Invalid address format");
788 addr_get_offset_bit_size(nir_ssa_def
*addr
, nir_address_format addr_format
)
790 if (addr_format
== nir_address_format_32bit_offset_as_64bit
||
791 addr_format
== nir_address_format_32bit_index_offset_pack64
)
793 return addr
->bit_size
;
797 build_addr_iadd_imm(nir_builder
*b
, nir_ssa_def
*addr
,
798 nir_address_format addr_format
, int64_t offset
)
800 return build_addr_iadd(b
, addr
, addr_format
,
801 nir_imm_intN_t(b
, offset
,
802 addr_get_offset_bit_size(addr
, addr_format
)));
806 build_addr_for_var(nir_builder
*b
, nir_variable
*var
,
807 nir_address_format addr_format
)
809 assert(var
->data
.mode
& (nir_var_uniform
| nir_var_mem_shared
|
810 nir_var_shader_temp
| nir_var_function_temp
));
812 const unsigned num_comps
= nir_address_format_num_components(addr_format
);
813 const unsigned bit_size
= nir_address_format_bit_size(addr_format
);
815 switch (addr_format
) {
816 case nir_address_format_32bit_global
:
817 case nir_address_format_64bit_global
: {
818 nir_ssa_def
*base_addr
;
819 switch (var
->data
.mode
) {
820 case nir_var_shader_temp
:
821 base_addr
= nir_load_scratch_base_ptr(b
, 0, num_comps
, bit_size
);
824 case nir_var_function_temp
:
825 base_addr
= nir_load_scratch_base_ptr(b
, 1, num_comps
, bit_size
);
829 unreachable("Unsupported variable mode");
832 return build_addr_iadd_imm(b
, base_addr
, addr_format
,
833 var
->data
.driver_location
);
836 case nir_address_format_32bit_offset
:
837 assert(var
->data
.driver_location
<= UINT32_MAX
);
838 return nir_imm_int(b
, var
->data
.driver_location
);
840 case nir_address_format_32bit_offset_as_64bit
:
841 assert(var
->data
.driver_location
<= UINT32_MAX
);
842 return nir_imm_int64(b
, var
->data
.driver_location
);
845 unreachable("Unsupported address format");
850 addr_to_index(nir_builder
*b
, nir_ssa_def
*addr
,
851 nir_address_format addr_format
)
853 switch (addr_format
) {
854 case nir_address_format_32bit_index_offset
:
855 assert(addr
->num_components
== 2);
856 return nir_channel(b
, addr
, 0);
857 case nir_address_format_32bit_index_offset_pack64
:
858 return nir_unpack_64_2x32_split_y(b
, addr
);
859 case nir_address_format_vec2_index_32bit_offset
:
860 assert(addr
->num_components
== 3);
861 return nir_channels(b
, addr
, 0x3);
862 default: unreachable("Invalid address format");
867 addr_to_offset(nir_builder
*b
, nir_ssa_def
*addr
,
868 nir_address_format addr_format
)
870 switch (addr_format
) {
871 case nir_address_format_32bit_index_offset
:
872 assert(addr
->num_components
== 2);
873 return nir_channel(b
, addr
, 1);
874 case nir_address_format_32bit_index_offset_pack64
:
875 return nir_unpack_64_2x32_split_x(b
, addr
);
876 case nir_address_format_vec2_index_32bit_offset
:
877 assert(addr
->num_components
== 3);
878 return nir_channel(b
, addr
, 2);
879 case nir_address_format_32bit_offset
:
881 case nir_address_format_32bit_offset_as_64bit
:
882 return nir_u2u32(b
, addr
);
884 unreachable("Invalid address format");
888 /** Returns true if the given address format resolves to a global address */
890 addr_format_is_global(nir_address_format addr_format
)
892 return addr_format
== nir_address_format_32bit_global
||
893 addr_format
== nir_address_format_64bit_global
||
894 addr_format
== nir_address_format_64bit_bounded_global
;
898 addr_format_is_offset(nir_address_format addr_format
)
900 return addr_format
== nir_address_format_32bit_offset
||
901 addr_format
== nir_address_format_32bit_offset_as_64bit
;
905 addr_to_global(nir_builder
*b
, nir_ssa_def
*addr
,
906 nir_address_format addr_format
)
908 switch (addr_format
) {
909 case nir_address_format_32bit_global
:
910 case nir_address_format_64bit_global
:
911 assert(addr
->num_components
== 1);
914 case nir_address_format_64bit_bounded_global
:
915 assert(addr
->num_components
== 4);
916 return nir_iadd(b
, nir_pack_64_2x32(b
, nir_channels(b
, addr
, 0x3)),
917 nir_u2u64(b
, nir_channel(b
, addr
, 3)));
919 case nir_address_format_32bit_index_offset
:
920 case nir_address_format_32bit_index_offset_pack64
:
921 case nir_address_format_vec2_index_32bit_offset
:
922 case nir_address_format_32bit_offset
:
923 case nir_address_format_32bit_offset_as_64bit
:
924 case nir_address_format_logical
:
925 unreachable("Cannot get a 64-bit address with this address format");
928 unreachable("Invalid address format");
932 addr_format_needs_bounds_check(nir_address_format addr_format
)
934 return addr_format
== nir_address_format_64bit_bounded_global
;
938 addr_is_in_bounds(nir_builder
*b
, nir_ssa_def
*addr
,
939 nir_address_format addr_format
, unsigned size
)
941 assert(addr_format
== nir_address_format_64bit_bounded_global
);
942 assert(addr
->num_components
== 4);
943 return nir_ige(b
, nir_channel(b
, addr
, 2),
944 nir_iadd_imm(b
, nir_channel(b
, addr
, 3), size
));
948 build_explicit_io_load(nir_builder
*b
, nir_intrinsic_instr
*intrin
,
949 nir_ssa_def
*addr
, nir_address_format addr_format
,
950 unsigned num_components
)
952 nir_variable_mode mode
= nir_src_as_deref(intrin
->src
[0])->mode
;
956 case nir_var_mem_ubo
:
957 op
= nir_intrinsic_load_ubo
;
959 case nir_var_mem_ssbo
:
960 if (addr_format_is_global(addr_format
))
961 op
= nir_intrinsic_load_global
;
963 op
= nir_intrinsic_load_ssbo
;
965 case nir_var_mem_global
:
966 assert(addr_format_is_global(addr_format
));
967 op
= nir_intrinsic_load_global
;
969 case nir_var_uniform
:
970 assert(addr_format_is_offset(addr_format
));
971 assert(b
->shader
->info
.stage
== MESA_SHADER_KERNEL
);
972 op
= nir_intrinsic_load_kernel_input
;
974 case nir_var_mem_shared
:
975 assert(addr_format_is_offset(addr_format
));
976 op
= nir_intrinsic_load_shared
;
978 case nir_var_shader_temp
:
979 case nir_var_function_temp
:
980 if (addr_format_is_offset(addr_format
)) {
981 op
= nir_intrinsic_load_scratch
;
983 assert(addr_format_is_global(addr_format
));
984 op
= nir_intrinsic_load_global
;
988 unreachable("Unsupported explicit IO variable mode");
991 nir_intrinsic_instr
*load
= nir_intrinsic_instr_create(b
->shader
, op
);
993 if (addr_format_is_global(addr_format
)) {
994 load
->src
[0] = nir_src_for_ssa(addr_to_global(b
, addr
, addr_format
));
995 } else if (addr_format_is_offset(addr_format
)) {
996 assert(addr
->num_components
== 1);
997 load
->src
[0] = nir_src_for_ssa(addr_to_offset(b
, addr
, addr_format
));
999 load
->src
[0] = nir_src_for_ssa(addr_to_index(b
, addr
, addr_format
));
1000 load
->src
[1] = nir_src_for_ssa(addr_to_offset(b
, addr
, addr_format
));
1003 if (nir_intrinsic_has_access(load
))
1004 nir_intrinsic_set_access(load
, nir_intrinsic_access(intrin
));
1006 unsigned bit_size
= intrin
->dest
.ssa
.bit_size
;
1007 if (bit_size
== 1) {
1008 /* TODO: Make the native bool bit_size an option. */
1012 /* TODO: We should try and provide a better alignment. For OpenCL, we need
1013 * to plumb the alignment through from SPIR-V when we have one.
1015 nir_intrinsic_set_align(load
, bit_size
/ 8, 0);
1017 assert(intrin
->dest
.is_ssa
);
1018 load
->num_components
= num_components
;
1019 nir_ssa_dest_init(&load
->instr
, &load
->dest
, num_components
,
1020 bit_size
, intrin
->dest
.ssa
.name
);
1022 assert(bit_size
% 8 == 0);
1024 nir_ssa_def
*result
;
1025 if (addr_format_needs_bounds_check(addr_format
)) {
1026 /* The Vulkan spec for robustBufferAccess gives us quite a few options
1027 * as to what we can do with an OOB read. Unfortunately, returning
1028 * undefined values isn't one of them so we return an actual zero.
1030 nir_ssa_def
*zero
= nir_imm_zero(b
, load
->num_components
, bit_size
);
1032 const unsigned load_size
= (bit_size
/ 8) * load
->num_components
;
1033 nir_push_if(b
, addr_is_in_bounds(b
, addr
, addr_format
, load_size
));
1035 nir_builder_instr_insert(b
, &load
->instr
);
1037 nir_pop_if(b
, NULL
);
1039 result
= nir_if_phi(b
, &load
->dest
.ssa
, zero
);
1041 nir_builder_instr_insert(b
, &load
->instr
);
1042 result
= &load
->dest
.ssa
;
1045 if (intrin
->dest
.ssa
.bit_size
== 1) {
1046 /* For shared, we can go ahead and use NIR's and/or the back-end's
1047 * standard encoding for booleans rather than forcing a 0/1 boolean.
1048 * This should save an instruction or two.
1050 if (mode
== nir_var_mem_shared
||
1051 mode
== nir_var_shader_temp
||
1052 mode
== nir_var_function_temp
)
1053 result
= nir_b2b1(b
, result
);
1055 result
= nir_i2b(b
, result
);
1062 build_explicit_io_store(nir_builder
*b
, nir_intrinsic_instr
*intrin
,
1063 nir_ssa_def
*addr
, nir_address_format addr_format
,
1064 nir_ssa_def
*value
, nir_component_mask_t write_mask
)
1066 nir_variable_mode mode
= nir_src_as_deref(intrin
->src
[0])->mode
;
1068 nir_intrinsic_op op
;
1070 case nir_var_mem_ssbo
:
1071 if (addr_format_is_global(addr_format
))
1072 op
= nir_intrinsic_store_global
;
1074 op
= nir_intrinsic_store_ssbo
;
1076 case nir_var_mem_global
:
1077 assert(addr_format_is_global(addr_format
));
1078 op
= nir_intrinsic_store_global
;
1080 case nir_var_mem_shared
:
1081 assert(addr_format_is_offset(addr_format
));
1082 op
= nir_intrinsic_store_shared
;
1084 case nir_var_shader_temp
:
1085 case nir_var_function_temp
:
1086 if (addr_format_is_offset(addr_format
)) {
1087 op
= nir_intrinsic_store_scratch
;
1089 assert(addr_format_is_global(addr_format
));
1090 op
= nir_intrinsic_store_global
;
1094 unreachable("Unsupported explicit IO variable mode");
1097 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
->shader
, op
);
1099 if (value
->bit_size
== 1) {
1100 /* For shared, we can go ahead and use NIR's and/or the back-end's
1101 * standard encoding for booleans rather than forcing a 0/1 boolean.
1102 * This should save an instruction or two.
1104 * TODO: Make the native bool bit_size an option.
1106 if (mode
== nir_var_mem_shared
||
1107 mode
== nir_var_shader_temp
||
1108 mode
== nir_var_function_temp
)
1109 value
= nir_b2b32(b
, value
);
1111 value
= nir_b2i(b
, value
, 32);
1114 store
->src
[0] = nir_src_for_ssa(value
);
1115 if (addr_format_is_global(addr_format
)) {
1116 store
->src
[1] = nir_src_for_ssa(addr_to_global(b
, addr
, addr_format
));
1117 } else if (addr_format_is_offset(addr_format
)) {
1118 assert(addr
->num_components
== 1);
1119 store
->src
[1] = nir_src_for_ssa(addr_to_offset(b
, addr
, addr_format
));
1121 store
->src
[1] = nir_src_for_ssa(addr_to_index(b
, addr
, addr_format
));
1122 store
->src
[2] = nir_src_for_ssa(addr_to_offset(b
, addr
, addr_format
));
1125 nir_intrinsic_set_write_mask(store
, write_mask
);
1127 if (nir_intrinsic_has_access(store
))
1128 nir_intrinsic_set_access(store
, nir_intrinsic_access(intrin
));
1130 /* TODO: We should try and provide a better alignment. For OpenCL, we need
1131 * to plumb the alignment through from SPIR-V when we have one.
1133 nir_intrinsic_set_align(store
, value
->bit_size
/ 8, 0);
1135 assert(value
->num_components
== 1 ||
1136 value
->num_components
== intrin
->num_components
);
1137 store
->num_components
= value
->num_components
;
1139 assert(value
->bit_size
% 8 == 0);
1141 if (addr_format_needs_bounds_check(addr_format
)) {
1142 const unsigned store_size
= (value
->bit_size
/ 8) * store
->num_components
;
1143 nir_push_if(b
, addr_is_in_bounds(b
, addr
, addr_format
, store_size
));
1145 nir_builder_instr_insert(b
, &store
->instr
);
1147 nir_pop_if(b
, NULL
);
1149 nir_builder_instr_insert(b
, &store
->instr
);
1153 static nir_ssa_def
*
1154 build_explicit_io_atomic(nir_builder
*b
, nir_intrinsic_instr
*intrin
,
1155 nir_ssa_def
*addr
, nir_address_format addr_format
)
1157 nir_variable_mode mode
= nir_src_as_deref(intrin
->src
[0])->mode
;
1158 const unsigned num_data_srcs
=
1159 nir_intrinsic_infos
[intrin
->intrinsic
].num_srcs
- 1;
1161 nir_intrinsic_op op
;
1163 case nir_var_mem_ssbo
:
1164 if (addr_format_is_global(addr_format
))
1165 op
= global_atomic_for_deref(intrin
->intrinsic
);
1167 op
= ssbo_atomic_for_deref(intrin
->intrinsic
);
1169 case nir_var_mem_global
:
1170 assert(addr_format_is_global(addr_format
));
1171 op
= global_atomic_for_deref(intrin
->intrinsic
);
1173 case nir_var_mem_shared
:
1174 assert(addr_format_is_offset(addr_format
));
1175 op
= shared_atomic_for_deref(intrin
->intrinsic
);
1178 unreachable("Unsupported explicit IO variable mode");
1181 nir_intrinsic_instr
*atomic
= nir_intrinsic_instr_create(b
->shader
, op
);
1184 if (addr_format_is_global(addr_format
)) {
1185 atomic
->src
[src
++] = nir_src_for_ssa(addr_to_global(b
, addr
, addr_format
));
1186 } else if (addr_format_is_offset(addr_format
)) {
1187 assert(addr
->num_components
== 1);
1188 atomic
->src
[src
++] = nir_src_for_ssa(addr_to_offset(b
, addr
, addr_format
));
1190 atomic
->src
[src
++] = nir_src_for_ssa(addr_to_index(b
, addr
, addr_format
));
1191 atomic
->src
[src
++] = nir_src_for_ssa(addr_to_offset(b
, addr
, addr_format
));
1193 for (unsigned i
= 0; i
< num_data_srcs
; i
++) {
1194 atomic
->src
[src
++] = nir_src_for_ssa(intrin
->src
[1 + i
].ssa
);
1197 /* Global atomics don't have access flags because they assume that the
1198 * address may be non-uniform.
1200 if (nir_intrinsic_has_access(atomic
))
1201 nir_intrinsic_set_access(atomic
, nir_intrinsic_access(intrin
));
1203 assert(intrin
->dest
.ssa
.num_components
== 1);
1204 nir_ssa_dest_init(&atomic
->instr
, &atomic
->dest
,
1205 1, intrin
->dest
.ssa
.bit_size
, intrin
->dest
.ssa
.name
);
1207 assert(atomic
->dest
.ssa
.bit_size
% 8 == 0);
1209 if (addr_format_needs_bounds_check(addr_format
)) {
1210 const unsigned atomic_size
= atomic
->dest
.ssa
.bit_size
/ 8;
1211 nir_push_if(b
, addr_is_in_bounds(b
, addr
, addr_format
, atomic_size
));
1213 nir_builder_instr_insert(b
, &atomic
->instr
);
1215 nir_pop_if(b
, NULL
);
1216 return nir_if_phi(b
, &atomic
->dest
.ssa
,
1217 nir_ssa_undef(b
, 1, atomic
->dest
.ssa
.bit_size
));
1219 nir_builder_instr_insert(b
, &atomic
->instr
);
1220 return &atomic
->dest
.ssa
;
1225 nir_explicit_io_address_from_deref(nir_builder
*b
, nir_deref_instr
*deref
,
1226 nir_ssa_def
*base_addr
,
1227 nir_address_format addr_format
)
1229 assert(deref
->dest
.is_ssa
);
1230 switch (deref
->deref_type
) {
1231 case nir_deref_type_var
:
1232 return build_addr_for_var(b
, deref
->var
, addr_format
);
1234 case nir_deref_type_array
: {
1235 nir_deref_instr
*parent
= nir_deref_instr_parent(deref
);
1237 unsigned stride
= glsl_get_explicit_stride(parent
->type
);
1238 if ((glsl_type_is_matrix(parent
->type
) &&
1239 glsl_matrix_type_is_row_major(parent
->type
)) ||
1240 (glsl_type_is_vector(parent
->type
) && stride
== 0))
1241 stride
= type_scalar_size_bytes(parent
->type
);
1245 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
1246 index
= nir_i2i(b
, index
, addr_get_offset_bit_size(base_addr
, addr_format
));
1247 return build_addr_iadd(b
, base_addr
, addr_format
,
1248 nir_amul_imm(b
, index
, stride
));
1251 case nir_deref_type_ptr_as_array
: {
1252 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
1253 index
= nir_i2i(b
, index
, addr_get_offset_bit_size(base_addr
, addr_format
));
1254 unsigned stride
= nir_deref_instr_ptr_as_array_stride(deref
);
1255 return build_addr_iadd(b
, base_addr
, addr_format
,
1256 nir_amul_imm(b
, index
, stride
));
1259 case nir_deref_type_array_wildcard
:
1260 unreachable("Wildcards should be lowered by now");
1263 case nir_deref_type_struct
: {
1264 nir_deref_instr
*parent
= nir_deref_instr_parent(deref
);
1265 int offset
= glsl_get_struct_field_offset(parent
->type
,
1266 deref
->strct
.index
);
1267 assert(offset
>= 0);
1268 return build_addr_iadd_imm(b
, base_addr
, addr_format
, offset
);
1271 case nir_deref_type_cast
:
1272 /* Nothing to do here */
1276 unreachable("Invalid NIR deref type");
1280 nir_lower_explicit_io_instr(nir_builder
*b
,
1281 nir_intrinsic_instr
*intrin
,
1283 nir_address_format addr_format
)
1285 b
->cursor
= nir_after_instr(&intrin
->instr
);
1287 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
1288 unsigned vec_stride
= glsl_get_explicit_stride(deref
->type
);
1289 unsigned scalar_size
= type_scalar_size_bytes(deref
->type
);
1290 assert(vec_stride
== 0 || glsl_type_is_vector(deref
->type
));
1291 assert(vec_stride
== 0 || vec_stride
>= scalar_size
);
1293 if (intrin
->intrinsic
== nir_intrinsic_load_deref
) {
1295 if (vec_stride
> scalar_size
) {
1296 nir_ssa_def
*comps
[4] = { NULL
, };
1297 for (unsigned i
= 0; i
< intrin
->num_components
; i
++) {
1298 nir_ssa_def
*comp_addr
= build_addr_iadd_imm(b
, addr
, addr_format
,
1300 comps
[i
] = build_explicit_io_load(b
, intrin
, comp_addr
,
1303 value
= nir_vec(b
, comps
, intrin
->num_components
);
1305 value
= build_explicit_io_load(b
, intrin
, addr
, addr_format
,
1306 intrin
->num_components
);
1308 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
, nir_src_for_ssa(value
));
1309 } else if (intrin
->intrinsic
== nir_intrinsic_store_deref
) {
1310 assert(intrin
->src
[1].is_ssa
);
1311 nir_ssa_def
*value
= intrin
->src
[1].ssa
;
1312 nir_component_mask_t write_mask
= nir_intrinsic_write_mask(intrin
);
1313 if (vec_stride
> scalar_size
) {
1314 for (unsigned i
= 0; i
< intrin
->num_components
; i
++) {
1315 if (!(write_mask
& (1 << i
)))
1318 nir_ssa_def
*comp_addr
= build_addr_iadd_imm(b
, addr
, addr_format
,
1320 build_explicit_io_store(b
, intrin
, comp_addr
, addr_format
,
1321 nir_channel(b
, value
, i
), 1);
1324 build_explicit_io_store(b
, intrin
, addr
, addr_format
,
1328 nir_ssa_def
*value
=
1329 build_explicit_io_atomic(b
, intrin
, addr
, addr_format
);
1330 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
, nir_src_for_ssa(value
));
1333 nir_instr_remove(&intrin
->instr
);
1337 lower_explicit_io_deref(nir_builder
*b
, nir_deref_instr
*deref
,
1338 nir_address_format addr_format
)
1340 /* Just delete the deref if it's not used. We can't use
1341 * nir_deref_instr_remove_if_unused here because it may remove more than
1342 * one deref which could break our list walking since we walk the list
1345 assert(list_is_empty(&deref
->dest
.ssa
.if_uses
));
1346 if (list_is_empty(&deref
->dest
.ssa
.uses
)) {
1347 nir_instr_remove(&deref
->instr
);
1351 b
->cursor
= nir_after_instr(&deref
->instr
);
1353 nir_ssa_def
*base_addr
= NULL
;
1354 if (deref
->deref_type
!= nir_deref_type_var
) {
1355 assert(deref
->parent
.is_ssa
);
1356 base_addr
= deref
->parent
.ssa
;
1359 nir_ssa_def
*addr
= nir_explicit_io_address_from_deref(b
, deref
, base_addr
,
1362 nir_instr_remove(&deref
->instr
);
1363 nir_ssa_def_rewrite_uses(&deref
->dest
.ssa
, nir_src_for_ssa(addr
));
1367 lower_explicit_io_access(nir_builder
*b
, nir_intrinsic_instr
*intrin
,
1368 nir_address_format addr_format
)
1370 assert(intrin
->src
[0].is_ssa
);
1371 nir_lower_explicit_io_instr(b
, intrin
, intrin
->src
[0].ssa
, addr_format
);
1375 lower_explicit_io_array_length(nir_builder
*b
, nir_intrinsic_instr
*intrin
,
1376 nir_address_format addr_format
)
1378 b
->cursor
= nir_after_instr(&intrin
->instr
);
1380 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
1382 assert(glsl_type_is_array(deref
->type
));
1383 assert(glsl_get_length(deref
->type
) == 0);
1384 unsigned stride
= glsl_get_explicit_stride(deref
->type
);
1387 nir_ssa_def
*addr
= &deref
->dest
.ssa
;
1388 nir_ssa_def
*index
= addr_to_index(b
, addr
, addr_format
);
1389 nir_ssa_def
*offset
= addr_to_offset(b
, addr
, addr_format
);
1391 nir_intrinsic_instr
*bsize
=
1392 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_get_buffer_size
);
1393 bsize
->src
[0] = nir_src_for_ssa(index
);
1394 nir_ssa_dest_init(&bsize
->instr
, &bsize
->dest
, 1, 32, NULL
);
1395 nir_builder_instr_insert(b
, &bsize
->instr
);
1397 nir_ssa_def
*arr_size
=
1398 nir_idiv(b
, nir_isub(b
, &bsize
->dest
.ssa
, offset
),
1399 nir_imm_int(b
, stride
));
1401 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
, nir_src_for_ssa(arr_size
));
1402 nir_instr_remove(&intrin
->instr
);
1406 nir_lower_explicit_io_impl(nir_function_impl
*impl
, nir_variable_mode modes
,
1407 nir_address_format addr_format
)
1409 bool progress
= false;
1412 nir_builder_init(&b
, impl
);
1414 /* Walk in reverse order so that we can see the full deref chain when we
1415 * lower the access operations. We lower them assuming that the derefs
1416 * will be turned into address calculations later.
1418 nir_foreach_block_reverse(block
, impl
) {
1419 nir_foreach_instr_reverse_safe(instr
, block
) {
1420 switch (instr
->type
) {
1421 case nir_instr_type_deref
: {
1422 nir_deref_instr
*deref
= nir_instr_as_deref(instr
);
1423 if (deref
->mode
& modes
) {
1424 lower_explicit_io_deref(&b
, deref
, addr_format
);
1430 case nir_instr_type_intrinsic
: {
1431 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
1432 switch (intrin
->intrinsic
) {
1433 case nir_intrinsic_load_deref
:
1434 case nir_intrinsic_store_deref
:
1435 case nir_intrinsic_deref_atomic_add
:
1436 case nir_intrinsic_deref_atomic_imin
:
1437 case nir_intrinsic_deref_atomic_umin
:
1438 case nir_intrinsic_deref_atomic_imax
:
1439 case nir_intrinsic_deref_atomic_umax
:
1440 case nir_intrinsic_deref_atomic_and
:
1441 case nir_intrinsic_deref_atomic_or
:
1442 case nir_intrinsic_deref_atomic_xor
:
1443 case nir_intrinsic_deref_atomic_exchange
:
1444 case nir_intrinsic_deref_atomic_comp_swap
:
1445 case nir_intrinsic_deref_atomic_fadd
:
1446 case nir_intrinsic_deref_atomic_fmin
:
1447 case nir_intrinsic_deref_atomic_fmax
:
1448 case nir_intrinsic_deref_atomic_fcomp_swap
: {
1449 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
1450 if (deref
->mode
& modes
) {
1451 lower_explicit_io_access(&b
, intrin
, addr_format
);
1457 case nir_intrinsic_deref_buffer_array_length
: {
1458 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
1459 if (deref
->mode
& modes
) {
1460 lower_explicit_io_array_length(&b
, intrin
, addr_format
);
1480 nir_metadata_preserve(impl
, nir_metadata_block_index
|
1481 nir_metadata_dominance
);
1487 /** Lower explicitly laid out I/O access to byte offset/address intrinsics
1489 * This pass is intended to be used for any I/O which touches memory external
1490 * to the shader or which is directly visible to the client. It requires that
1491 * all data types in the given modes have a explicit stride/offset decorations
1492 * to tell it exactly how to calculate the offset/address for the given load,
1493 * store, or atomic operation. If the offset/stride information does not come
1494 * from the client explicitly (as with shared variables in GL or Vulkan),
1495 * nir_lower_vars_to_explicit_types() can be used to add them.
1497 * Unlike nir_lower_io, this pass is fully capable of handling incomplete
1498 * pointer chains which may contain cast derefs. It does so by walking the
1499 * deref chain backwards and simply replacing each deref, one at a time, with
1500 * the appropriate address calculation. The pass takes a nir_address_format
1501 * parameter which describes how the offset or address is to be represented
1502 * during calculations. By ensuring that the address is always in a
1503 * consistent format, pointers can safely be conjured from thin air by the
1504 * driver, stored to variables, passed through phis, etc.
1506 * The one exception to the simple algorithm described above is for handling
1507 * row-major matrices in which case we may look down one additional level of
1511 nir_lower_explicit_io(nir_shader
*shader
, nir_variable_mode modes
,
1512 nir_address_format addr_format
)
1514 bool progress
= false;
1516 nir_foreach_function(function
, shader
) {
1517 if (function
->impl
&&
1518 nir_lower_explicit_io_impl(function
->impl
, modes
, addr_format
))
1526 nir_lower_vars_to_explicit_types_impl(nir_function_impl
*impl
,
1527 nir_variable_mode modes
,
1528 glsl_type_size_align_func type_info
)
1530 bool progress
= false;
1532 nir_foreach_block(block
, impl
) {
1533 nir_foreach_instr(instr
, block
) {
1534 if (instr
->type
!= nir_instr_type_deref
)
1537 nir_deref_instr
*deref
= nir_instr_as_deref(instr
);
1538 if (!(deref
->mode
& modes
))
1541 unsigned size
, alignment
;
1542 const struct glsl_type
*new_type
=
1543 glsl_get_explicit_type_for_size_align(deref
->type
, type_info
, &size
, &alignment
);
1544 if (new_type
!= deref
->type
) {
1546 deref
->type
= new_type
;
1548 if (deref
->deref_type
== nir_deref_type_cast
) {
1549 /* See also glsl_type::get_explicit_type_for_size_align() */
1550 unsigned new_stride
= align(size
, alignment
);
1551 if (new_stride
!= deref
->cast
.ptr_stride
) {
1552 deref
->cast
.ptr_stride
= new_stride
;
1560 nir_metadata_preserve(impl
, nir_metadata_block_index
|
1561 nir_metadata_dominance
|
1562 nir_metadata_live_ssa_defs
|
1563 nir_metadata_loop_analysis
);
1570 lower_vars_to_explicit(nir_shader
*shader
,
1571 struct exec_list
*vars
, nir_variable_mode mode
,
1572 glsl_type_size_align_func type_info
)
1574 bool progress
= false;
1577 case nir_var_function_temp
:
1578 case nir_var_shader_temp
:
1579 offset
= shader
->scratch_size
;
1581 case nir_var_mem_shared
:
1585 unreachable("Unsupported mode");
1587 nir_foreach_variable_in_list(var
, vars
) {
1588 if (var
->data
.mode
!= mode
)
1591 unsigned size
, align
;
1592 const struct glsl_type
*explicit_type
=
1593 glsl_get_explicit_type_for_size_align(var
->type
, type_info
, &size
, &align
);
1595 if (explicit_type
!= var
->type
) {
1597 var
->type
= explicit_type
;
1600 var
->data
.driver_location
= ALIGN_POT(offset
, align
);
1601 offset
= var
->data
.driver_location
+ size
;
1605 case nir_var_shader_temp
:
1606 case nir_var_function_temp
:
1607 shader
->scratch_size
= offset
;
1609 case nir_var_mem_shared
:
1610 shader
->info
.cs
.shared_size
= offset
;
1611 shader
->shared_size
= offset
;
1614 unreachable("Unsupported mode");
1621 nir_lower_vars_to_explicit_types(nir_shader
*shader
,
1622 nir_variable_mode modes
,
1623 glsl_type_size_align_func type_info
)
1625 /* TODO: Situations which need to be handled to support more modes:
1626 * - row-major matrices
1627 * - compact shader inputs/outputs
1630 ASSERTED nir_variable_mode supported
= nir_var_mem_shared
|
1631 nir_var_shader_temp
| nir_var_function_temp
;
1632 assert(!(modes
& ~supported
) && "unsupported");
1634 bool progress
= false;
1636 if (modes
& nir_var_mem_shared
)
1637 progress
|= lower_vars_to_explicit(shader
, &shader
->variables
, nir_var_mem_shared
, type_info
);
1638 if (modes
& nir_var_shader_temp
)
1639 progress
|= lower_vars_to_explicit(shader
, &shader
->variables
, nir_var_shader_temp
, type_info
);
1641 nir_foreach_function(function
, shader
) {
1642 if (function
->impl
) {
1643 if (modes
& nir_var_function_temp
)
1644 progress
|= lower_vars_to_explicit(shader
, &function
->impl
->locals
, nir_var_function_temp
, type_info
);
1646 progress
|= nir_lower_vars_to_explicit_types_impl(function
->impl
, modes
, type_info
);
1654 * Return the offset source for a load/store intrinsic.
1657 nir_get_io_offset_src(nir_intrinsic_instr
*instr
)
1659 switch (instr
->intrinsic
) {
1660 case nir_intrinsic_load_input
:
1661 case nir_intrinsic_load_output
:
1662 case nir_intrinsic_load_shared
:
1663 case nir_intrinsic_load_uniform
:
1664 case nir_intrinsic_load_global
:
1665 case nir_intrinsic_load_global_constant
:
1666 case nir_intrinsic_load_scratch
:
1667 case nir_intrinsic_load_fs_input_interp_deltas
:
1668 case nir_intrinsic_shared_atomic_add
:
1669 case nir_intrinsic_shared_atomic_and
:
1670 case nir_intrinsic_shared_atomic_comp_swap
:
1671 case nir_intrinsic_shared_atomic_exchange
:
1672 case nir_intrinsic_shared_atomic_fadd
:
1673 case nir_intrinsic_shared_atomic_fcomp_swap
:
1674 case nir_intrinsic_shared_atomic_fmax
:
1675 case nir_intrinsic_shared_atomic_fmin
:
1676 case nir_intrinsic_shared_atomic_imax
:
1677 case nir_intrinsic_shared_atomic_imin
:
1678 case nir_intrinsic_shared_atomic_or
:
1679 case nir_intrinsic_shared_atomic_umax
:
1680 case nir_intrinsic_shared_atomic_umin
:
1681 case nir_intrinsic_shared_atomic_xor
:
1682 case nir_intrinsic_global_atomic_add
:
1683 case nir_intrinsic_global_atomic_and
:
1684 case nir_intrinsic_global_atomic_comp_swap
:
1685 case nir_intrinsic_global_atomic_exchange
:
1686 case nir_intrinsic_global_atomic_fadd
:
1687 case nir_intrinsic_global_atomic_fcomp_swap
:
1688 case nir_intrinsic_global_atomic_fmax
:
1689 case nir_intrinsic_global_atomic_fmin
:
1690 case nir_intrinsic_global_atomic_imax
:
1691 case nir_intrinsic_global_atomic_imin
:
1692 case nir_intrinsic_global_atomic_or
:
1693 case nir_intrinsic_global_atomic_umax
:
1694 case nir_intrinsic_global_atomic_umin
:
1695 case nir_intrinsic_global_atomic_xor
:
1696 return &instr
->src
[0];
1697 case nir_intrinsic_load_ubo
:
1698 case nir_intrinsic_load_ssbo
:
1699 case nir_intrinsic_load_input_vertex
:
1700 case nir_intrinsic_load_per_vertex_input
:
1701 case nir_intrinsic_load_per_vertex_output
:
1702 case nir_intrinsic_load_interpolated_input
:
1703 case nir_intrinsic_store_output
:
1704 case nir_intrinsic_store_shared
:
1705 case nir_intrinsic_store_global
:
1706 case nir_intrinsic_store_scratch
:
1707 case nir_intrinsic_ssbo_atomic_add
:
1708 case nir_intrinsic_ssbo_atomic_imin
:
1709 case nir_intrinsic_ssbo_atomic_umin
:
1710 case nir_intrinsic_ssbo_atomic_imax
:
1711 case nir_intrinsic_ssbo_atomic_umax
:
1712 case nir_intrinsic_ssbo_atomic_and
:
1713 case nir_intrinsic_ssbo_atomic_or
:
1714 case nir_intrinsic_ssbo_atomic_xor
:
1715 case nir_intrinsic_ssbo_atomic_exchange
:
1716 case nir_intrinsic_ssbo_atomic_comp_swap
:
1717 case nir_intrinsic_ssbo_atomic_fadd
:
1718 case nir_intrinsic_ssbo_atomic_fmin
:
1719 case nir_intrinsic_ssbo_atomic_fmax
:
1720 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
1721 return &instr
->src
[1];
1722 case nir_intrinsic_store_ssbo
:
1723 case nir_intrinsic_store_per_vertex_output
:
1724 return &instr
->src
[2];
1731 * Return the vertex index source for a load/store per_vertex intrinsic.
1734 nir_get_io_vertex_index_src(nir_intrinsic_instr
*instr
)
1736 switch (instr
->intrinsic
) {
1737 case nir_intrinsic_load_per_vertex_input
:
1738 case nir_intrinsic_load_per_vertex_output
:
1739 return &instr
->src
[0];
1740 case nir_intrinsic_store_per_vertex_output
:
1741 return &instr
->src
[1];
1748 * Return the numeric constant that identify a NULL pointer for each address
1751 const nir_const_value
*
1752 nir_address_format_null_value(nir_address_format addr_format
)
1754 const static nir_const_value null_values
[][NIR_MAX_VEC_COMPONENTS
] = {
1755 [nir_address_format_32bit_global
] = {{0}},
1756 [nir_address_format_64bit_global
] = {{0}},
1757 [nir_address_format_64bit_bounded_global
] = {{0}},
1758 [nir_address_format_32bit_index_offset
] = {{.u32
= ~0}, {.u32
= ~0}},
1759 [nir_address_format_32bit_index_offset_pack64
] = {{.u64
= ~0ull}},
1760 [nir_address_format_vec2_index_32bit_offset
] = {{.u32
= ~0}, {.u32
= ~0}, {.u32
= ~0}},
1761 [nir_address_format_32bit_offset
] = {{.u32
= ~0}},
1762 [nir_address_format_32bit_offset_as_64bit
] = {{.u64
= ~0ull}},
1763 [nir_address_format_logical
] = {{.u32
= ~0}},
1766 assert(addr_format
< ARRAY_SIZE(null_values
));
1767 return null_values
[addr_format
];
1771 nir_build_addr_ieq(nir_builder
*b
, nir_ssa_def
*addr0
, nir_ssa_def
*addr1
,
1772 nir_address_format addr_format
)
1774 switch (addr_format
) {
1775 case nir_address_format_32bit_global
:
1776 case nir_address_format_64bit_global
:
1777 case nir_address_format_64bit_bounded_global
:
1778 case nir_address_format_32bit_index_offset
:
1779 case nir_address_format_vec2_index_32bit_offset
:
1780 case nir_address_format_32bit_offset
:
1781 return nir_ball_iequal(b
, addr0
, addr1
);
1783 case nir_address_format_32bit_offset_as_64bit
:
1784 assert(addr0
->num_components
== 1 && addr1
->num_components
== 1);
1785 return nir_ieq(b
, nir_u2u32(b
, addr0
), nir_u2u32(b
, addr1
));
1787 case nir_address_format_32bit_index_offset_pack64
:
1788 assert(addr0
->num_components
== 1 && addr1
->num_components
== 1);
1789 return nir_ball_iequal(b
, nir_unpack_64_2x32(b
, addr0
), nir_unpack_64_2x32(b
, addr1
));
1791 case nir_address_format_logical
:
1792 unreachable("Unsupported address format");
1795 unreachable("Invalid address format");
1799 nir_build_addr_isub(nir_builder
*b
, nir_ssa_def
*addr0
, nir_ssa_def
*addr1
,
1800 nir_address_format addr_format
)
1802 switch (addr_format
) {
1803 case nir_address_format_32bit_global
:
1804 case nir_address_format_64bit_global
:
1805 case nir_address_format_32bit_offset
:
1806 case nir_address_format_32bit_index_offset_pack64
:
1807 assert(addr0
->num_components
== 1);
1808 assert(addr1
->num_components
== 1);
1809 return nir_isub(b
, addr0
, addr1
);
1811 case nir_address_format_32bit_offset_as_64bit
:
1812 assert(addr0
->num_components
== 1);
1813 assert(addr1
->num_components
== 1);
1814 return nir_u2u64(b
, nir_isub(b
, nir_u2u32(b
, addr0
), nir_u2u32(b
, addr1
)));
1816 case nir_address_format_64bit_bounded_global
:
1817 return nir_isub(b
, addr_to_global(b
, addr0
, addr_format
),
1818 addr_to_global(b
, addr1
, addr_format
));
1820 case nir_address_format_32bit_index_offset
:
1821 assert(addr0
->num_components
== 2);
1822 assert(addr1
->num_components
== 2);
1823 /* Assume the same buffer index. */
1824 return nir_isub(b
, nir_channel(b
, addr0
, 1), nir_channel(b
, addr1
, 1));
1826 case nir_address_format_vec2_index_32bit_offset
:
1827 assert(addr0
->num_components
== 3);
1828 assert(addr1
->num_components
== 3);
1829 /* Assume the same buffer index. */
1830 return nir_isub(b
, nir_channel(b
, addr0
, 2), nir_channel(b
, addr1
, 2));
1832 case nir_address_format_logical
:
1833 unreachable("Unsupported address format");
1836 unreachable("Invalid address format");
1840 is_input(nir_intrinsic_instr
*intrin
)
1842 return intrin
->intrinsic
== nir_intrinsic_load_input
||
1843 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
||
1844 intrin
->intrinsic
== nir_intrinsic_load_interpolated_input
||
1845 intrin
->intrinsic
== nir_intrinsic_load_fs_input_interp_deltas
;
1849 is_output(nir_intrinsic_instr
*intrin
)
1851 return intrin
->intrinsic
== nir_intrinsic_load_output
||
1852 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_output
||
1853 intrin
->intrinsic
== nir_intrinsic_store_output
||
1854 intrin
->intrinsic
== nir_intrinsic_store_per_vertex_output
;
1857 static bool is_dual_slot(nir_intrinsic_instr
*intrin
)
1859 if (intrin
->intrinsic
== nir_intrinsic_store_output
||
1860 intrin
->intrinsic
== nir_intrinsic_store_per_vertex_output
) {
1861 return nir_src_bit_size(intrin
->src
[0]) == 64 &&
1862 nir_src_num_components(intrin
->src
[0]) >= 3;
1865 return nir_dest_bit_size(intrin
->dest
) &&
1866 nir_dest_num_components(intrin
->dest
) >= 3;
1870 * This pass adds constant offsets to instr->const_index[0] for input/output
1871 * intrinsics, and resets the offset source to 0. Non-constant offsets remain
1872 * unchanged - since we don't know what part of a compound variable is
1873 * accessed, we allocate storage for the entire thing. For drivers that use
1874 * nir_lower_io_to_temporaries() before nir_lower_io(), this guarantees that
1875 * the offset source will be 0, so that they don't have to add it in manually.
1879 add_const_offset_to_base_block(nir_block
*block
, nir_builder
*b
,
1880 nir_variable_mode mode
)
1882 bool progress
= false;
1883 nir_foreach_instr_safe(instr
, block
) {
1884 if (instr
->type
!= nir_instr_type_intrinsic
)
1887 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
1889 if ((mode
== nir_var_shader_in
&& is_input(intrin
)) ||
1890 (mode
== nir_var_shader_out
&& is_output(intrin
))) {
1891 nir_src
*offset
= nir_get_io_offset_src(intrin
);
1893 if (nir_src_is_const(*offset
)) {
1894 unsigned off
= nir_src_as_uint(*offset
);
1896 nir_intrinsic_set_base(intrin
, nir_intrinsic_base(intrin
) + off
);
1898 nir_io_semantics sem
= nir_intrinsic_io_semantics(intrin
);
1899 sem
.location
+= off
;
1900 /* non-indirect indexing should reduce num_slots */
1901 sem
.num_slots
= is_dual_slot(intrin
) ? 2 : 1;
1902 nir_intrinsic_set_io_semantics(intrin
, sem
);
1904 b
->cursor
= nir_before_instr(&intrin
->instr
);
1905 nir_instr_rewrite_src(&intrin
->instr
, offset
,
1906 nir_src_for_ssa(nir_imm_int(b
, 0)));
1916 nir_io_add_const_offset_to_base(nir_shader
*nir
, nir_variable_mode mode
)
1918 bool progress
= false;
1920 nir_foreach_function(f
, nir
) {
1923 nir_builder_init(&b
, f
->impl
);
1924 nir_foreach_block(block
, f
->impl
) {
1925 progress
|= add_const_offset_to_base_block(block
, &b
, mode
);