nir: use proper array sizing define for vectors
[mesa.git] / src / compiler / nir / nir_opt_copy_propagate.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Connor Abbott (cwabbott0@gmail.com)
25 *
26 */
27
28 #include "nir.h"
29 #include <main/imports.h>
30
31 /**
32 * SSA-based copy propagation
33 */
34
35 static bool is_move(nir_alu_instr *instr)
36 {
37 assert(instr->src[0].src.is_ssa);
38
39 if (instr->op != nir_op_fmov &&
40 instr->op != nir_op_imov)
41 return false;
42
43 if (instr->dest.saturate)
44 return false;
45
46 /* we handle modifiers in a separate pass */
47
48 if (instr->src[0].abs || instr->src[0].negate)
49 return false;
50
51 return true;
52
53 }
54
55 static bool is_vec(nir_alu_instr *instr)
56 {
57 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
58 assert(instr->src[i].src.is_ssa);
59
60 /* we handle modifiers in a separate pass */
61 if (instr->src[i].abs || instr->src[i].negate)
62 return false;
63 }
64
65 return instr->op == nir_op_vec2 ||
66 instr->op == nir_op_vec3 ||
67 instr->op == nir_op_vec4;
68 }
69
70 static bool
71 is_swizzleless_move(nir_alu_instr *instr)
72 {
73 if (is_move(instr)) {
74 for (unsigned i = 0; i < 4; i++) {
75 if (!((instr->dest.write_mask >> i) & 1))
76 break;
77 if (instr->src[0].swizzle[i] != i)
78 return false;
79 }
80 return true;
81 } else if (is_vec(instr)) {
82 nir_ssa_def *def = NULL;
83 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
84 if (instr->src[i].swizzle[0] != i)
85 return false;
86
87 if (def == NULL) {
88 def = instr->src[i].src.ssa;
89 } else if (instr->src[i].src.ssa != def) {
90 return false;
91 }
92 }
93 return true;
94 } else {
95 return false;
96 }
97 }
98
99 static bool
100 copy_prop_src(nir_src *src, nir_instr *parent_instr, nir_if *parent_if,
101 unsigned num_components)
102 {
103 assert(src->is_ssa);
104
105 nir_instr *src_instr = src->ssa->parent_instr;
106 nir_ssa_def *copy_def;
107 if (src_instr->type == nir_instr_type_alu) {
108 nir_alu_instr *alu_instr = nir_instr_as_alu(src_instr);
109 if (!is_swizzleless_move(alu_instr))
110 return false;
111
112 if (alu_instr->src[0].src.ssa->num_components != num_components)
113 return false;
114
115 copy_def= alu_instr->src[0].src.ssa;
116 } else {
117 return false;
118 }
119
120 if (parent_instr) {
121 nir_instr_rewrite_src(parent_instr, src, nir_src_for_ssa(copy_def));
122 } else {
123 assert(src == &parent_if->condition);
124 nir_if_rewrite_condition(parent_if, nir_src_for_ssa(copy_def));
125 }
126
127 return true;
128 }
129
130 static bool
131 copy_prop_alu_src(nir_alu_instr *parent_alu_instr, unsigned index)
132 {
133 nir_alu_src *src = &parent_alu_instr->src[index];
134 assert(src->src.is_ssa);
135
136 nir_instr *src_instr = src->src.ssa->parent_instr;
137 if (src_instr->type != nir_instr_type_alu)
138 return false;
139
140 nir_alu_instr *alu_instr = nir_instr_as_alu(src_instr);
141 if (!is_move(alu_instr) && !is_vec(alu_instr))
142 return false;
143
144 nir_ssa_def *def;
145 unsigned new_swizzle[NIR_MAX_VEC_COMPONENTS] = {0, 0, 0, 0};
146
147 if (alu_instr->op == nir_op_fmov ||
148 alu_instr->op == nir_op_imov) {
149 for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
150 new_swizzle[i] = alu_instr->src[0].swizzle[src->swizzle[i]];
151 def = alu_instr->src[0].src.ssa;
152 } else {
153 def = NULL;
154
155 for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++) {
156 if (!nir_alu_instr_channel_used(parent_alu_instr, index, i))
157 continue;
158
159 nir_ssa_def *new_def = alu_instr->src[src->swizzle[i]].src.ssa;
160 if (def == NULL)
161 def = new_def;
162 else {
163 if (def != new_def)
164 return false;
165 }
166 new_swizzle[i] = alu_instr->src[src->swizzle[i]].swizzle[0];
167 }
168 }
169
170 for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
171 src->swizzle[i] = new_swizzle[i];
172
173 nir_instr_rewrite_src(&parent_alu_instr->instr, &src->src,
174 nir_src_for_ssa(def));
175
176 return true;
177 }
178
179 static bool
180 copy_prop_instr(nir_instr *instr)
181 {
182 bool progress = false;
183 switch (instr->type) {
184 case nir_instr_type_alu: {
185 nir_alu_instr *alu_instr = nir_instr_as_alu(instr);
186
187 for (unsigned i = 0; i < nir_op_infos[alu_instr->op].num_inputs; i++)
188 while (copy_prop_alu_src(alu_instr, i))
189 progress = true;
190
191 return progress;
192 }
193
194 case nir_instr_type_deref: {
195 nir_deref_instr *deref = nir_instr_as_deref(instr);
196
197 if (deref->deref_type != nir_deref_type_var) {
198 assert(deref->dest.is_ssa);
199 const unsigned comps = deref->dest.ssa.num_components;
200 while (copy_prop_src(&deref->parent, instr, NULL, comps))
201 progress = true;
202 }
203
204 if (deref->deref_type == nir_deref_type_array ||
205 deref->deref_type == nir_deref_type_ptr_as_array) {
206 while (copy_prop_src(&deref->arr.index, instr, NULL, 1))
207 progress = true;
208 }
209
210 return progress;
211 }
212
213 case nir_instr_type_tex: {
214 nir_tex_instr *tex = nir_instr_as_tex(instr);
215 for (unsigned i = 0; i < tex->num_srcs; i++) {
216 unsigned num_components = nir_tex_instr_src_size(tex, i);
217 while (copy_prop_src(&tex->src[i].src, instr, NULL, num_components))
218 progress = true;
219 }
220
221 return progress;
222 }
223
224 case nir_instr_type_intrinsic: {
225 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
226 for (unsigned i = 0;
227 i < nir_intrinsic_infos[intrin->intrinsic].num_srcs; i++) {
228 unsigned num_components = nir_intrinsic_src_components(intrin, i);
229
230 while (copy_prop_src(&intrin->src[i], instr, NULL, num_components))
231 progress = true;
232 }
233
234 return progress;
235 }
236
237 case nir_instr_type_phi: {
238 nir_phi_instr *phi = nir_instr_as_phi(instr);
239 assert(phi->dest.is_ssa);
240 unsigned num_components = phi->dest.ssa.num_components;
241 nir_foreach_phi_src(src, phi) {
242 while (copy_prop_src(&src->src, instr, NULL, num_components))
243 progress = true;
244 }
245
246 return progress;
247 }
248
249 default:
250 return false;
251 }
252 }
253
254 static bool
255 copy_prop_if(nir_if *if_stmt)
256 {
257 return copy_prop_src(&if_stmt->condition, NULL, if_stmt, 1);
258 }
259
260 static bool
261 nir_copy_prop_impl(nir_function_impl *impl)
262 {
263 bool progress = false;
264
265 nir_foreach_block(block, impl) {
266 nir_foreach_instr(instr, block) {
267 if (copy_prop_instr(instr))
268 progress = true;
269 }
270
271 nir_if *if_stmt = nir_block_get_following_if(block);
272 if (if_stmt && copy_prop_if(if_stmt))
273 progress = true;
274 }
275
276 if (progress) {
277 nir_metadata_preserve(impl, nir_metadata_block_index |
278 nir_metadata_dominance);
279 } else {
280 #ifndef NDEBUG
281 impl->valid_metadata &= ~nir_metadata_not_properly_reset;
282 #endif
283 }
284
285 return progress;
286 }
287
288 bool
289 nir_copy_prop(nir_shader *shader)
290 {
291 bool progress = false;
292
293 nir_foreach_function(function, shader) {
294 if (function->impl && nir_copy_prop_impl(function->impl))
295 progress = true;
296 }
297
298 return progress;
299 }