2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Jason Ekstrand (jason@jlekstrand.net)
31 * Implements Global Code Motion. A description of GCM can be found in
32 * "Global Code Motion; Global Value Numbering" by Cliff Click.
33 * Unfortunately, the algorithm presented in the paper is broken in a
34 * number of ways. The algorithm used here differs substantially from the
35 * one in the paper but it is, in my opinion, much easier to read and
39 struct gcm_block_info
{
40 /* Number of loops this block is inside */
43 /* The last instruction inserted into this block. This is used as we
44 * traverse the instructions and insert them back into the program to
45 * put them in the right order.
47 nir_instr
*last_instr
;
50 /* Flags used in the instr->pass_flags field for various instruction states */
52 GCM_INSTR_PINNED
= (1 << 0),
53 GCM_INSTR_SCHEDULED_EARLY
= (1 << 1),
54 GCM_INSTR_SCHEDULED_LATE
= (1 << 2),
55 GCM_INSTR_PLACED
= (1 << 3),
59 nir_function_impl
*impl
;
62 /* The list of non-pinned instructions. As we do the late scheduling,
63 * we pull non-pinned instructions out of their blocks and place them in
64 * this list. This saves us from having linked-list problems when we go
65 * to put instructions back in their blocks.
67 struct exec_list instrs
;
69 struct gcm_block_info
*blocks
;
72 /* Recursively walks the CFG and builds the block_info structure */
74 gcm_build_block_info(struct exec_list
*cf_list
, struct gcm_state
*state
,
77 foreach_list_typed(nir_cf_node
, node
, node
, cf_list
) {
79 case nir_cf_node_block
: {
80 nir_block
*block
= nir_cf_node_as_block(node
);
81 state
->blocks
[block
->index
].loop_depth
= loop_depth
;
84 case nir_cf_node_if
: {
85 nir_if
*if_stmt
= nir_cf_node_as_if(node
);
86 gcm_build_block_info(&if_stmt
->then_list
, state
, loop_depth
);
87 gcm_build_block_info(&if_stmt
->else_list
, state
, loop_depth
);
90 case nir_cf_node_loop
: {
91 nir_loop
*loop
= nir_cf_node_as_loop(node
);
92 gcm_build_block_info(&loop
->body
, state
, loop_depth
+ 1);
96 unreachable("Invalid CF node type");
101 /* Walks the instruction list and marks immovable instructions as pinned
103 * This function also serves to initialize the instr->pass_flags field.
104 * After this is completed, all instructions' pass_flags fields will be set
105 * to either GCM_INSTR_PINNED or 0.
108 gcm_pin_instructions_block(nir_block
*block
, struct gcm_state
*state
)
110 nir_foreach_instr_safe(instr
, block
) {
111 switch (instr
->type
) {
112 case nir_instr_type_alu
:
113 switch (nir_instr_as_alu(instr
)->op
) {
116 case nir_op_fddx_fine
:
117 case nir_op_fddy_fine
:
118 case nir_op_fddx_coarse
:
119 case nir_op_fddy_coarse
:
120 /* These can only go in uniform control flow; pin them for now */
121 instr
->pass_flags
= GCM_INSTR_PINNED
;
125 instr
->pass_flags
= 0;
130 case nir_instr_type_tex
:
131 switch (nir_instr_as_tex(instr
)->op
) {
135 /* These two take implicit derivatives so they need to be pinned */
136 instr
->pass_flags
= GCM_INSTR_PINNED
;
140 instr
->pass_flags
= 0;
145 case nir_instr_type_load_const
:
146 instr
->pass_flags
= 0;
149 case nir_instr_type_intrinsic
: {
150 const nir_intrinsic_info
*info
=
151 &nir_intrinsic_infos
[nir_instr_as_intrinsic(instr
)->intrinsic
];
153 if ((info
->flags
& NIR_INTRINSIC_CAN_ELIMINATE
) &&
154 (info
->flags
& NIR_INTRINSIC_CAN_REORDER
)) {
155 instr
->pass_flags
= 0;
157 instr
->pass_flags
= GCM_INSTR_PINNED
;
162 case nir_instr_type_jump
:
163 case nir_instr_type_ssa_undef
:
164 case nir_instr_type_phi
:
165 instr
->pass_flags
= GCM_INSTR_PINNED
;
169 unreachable("Invalid instruction type in GCM");
172 if (!(instr
->pass_flags
& GCM_INSTR_PINNED
)) {
173 /* If this is an unpinned instruction, go ahead and pull it out of
174 * the program and put it on the instrs list. This has a couple
175 * of benifits. First, it makes the scheduling algorithm more
176 * efficient because we can avoid walking over basic blocks and
177 * pinned instructions. Second, it keeps us from causing linked
178 * list confusion when we're trying to put everything in its
179 * proper place at the end of the pass.
181 * Note that we don't use nir_instr_remove here because that also
182 * cleans up uses and defs and we want to keep that information.
184 exec_node_remove(&instr
->node
);
185 exec_list_push_tail(&state
->instrs
, &instr
->node
);
193 gcm_schedule_early_instr(nir_instr
*instr
, struct gcm_state
*state
);
195 /** Update an instructions schedule for the given source
197 * This function is called iteratively as we walk the sources of an
198 * instruction. It ensures that the given source instruction has been
199 * scheduled and then update this instruction's block if the source
200 * instruction is lower down the tree.
203 gcm_schedule_early_src(nir_src
*src
, void *void_state
)
205 struct gcm_state
*state
= void_state
;
206 nir_instr
*instr
= state
->instr
;
210 gcm_schedule_early_instr(src
->ssa
->parent_instr
, void_state
);
212 /* While the index isn't a proper dominance depth, it does have the
213 * property that if A dominates B then A->index <= B->index. Since we
214 * know that this instruction must have been dominated by all of its
215 * sources at some point (even if it's gone through value-numbering),
216 * all of the sources must lie on the same branch of the dominance tree.
217 * Therefore, we can just go ahead and just compare indices.
219 if (instr
->block
->index
< src
->ssa
->parent_instr
->block
->index
)
220 instr
->block
= src
->ssa
->parent_instr
->block
;
222 /* We need to restore the state instruction because it may have been
223 * changed through the gcm_schedule_early_instr call above. Since we
224 * may still be iterating through sources and future calls to
225 * gcm_schedule_early_src for the same instruction will still need it.
227 state
->instr
= instr
;
232 /** Schedules an instruction early
234 * This function performs a recursive depth-first search starting at the
235 * given instruction and proceeding through the sources to schedule
236 * instructions as early as they can possibly go in the dominance tree.
237 * The instructions are "scheduled" by updating their instr->block field.
240 gcm_schedule_early_instr(nir_instr
*instr
, struct gcm_state
*state
)
242 if (instr
->pass_flags
& GCM_INSTR_SCHEDULED_EARLY
)
245 instr
->pass_flags
|= GCM_INSTR_SCHEDULED_EARLY
;
247 /* Pinned instructions are already scheduled so we don't need to do
248 * anything. Also, bailing here keeps us from ever following the
249 * sources of phi nodes which can be back-edges.
251 if (instr
->pass_flags
& GCM_INSTR_PINNED
)
254 /* Start with the instruction at the top. As we iterate over the
255 * sources, it will get moved down as needed.
257 instr
->block
= nir_start_block(state
->impl
);
258 state
->instr
= instr
;
260 nir_foreach_src(instr
, gcm_schedule_early_src
, state
);
264 gcm_schedule_late_instr(nir_instr
*instr
, struct gcm_state
*state
);
266 /** Schedules the instruction associated with the given SSA def late
268 * This function works by first walking all of the uses of the given SSA
269 * definition, ensuring that they are scheduled, and then computing the LCA
270 * (least common ancestor) of its uses. It then schedules this instruction
271 * as close to the LCA as possible while trying to stay out of loops.
274 gcm_schedule_late_def(nir_ssa_def
*def
, void *void_state
)
276 struct gcm_state
*state
= void_state
;
278 nir_block
*lca
= NULL
;
280 nir_foreach_use(use_src
, def
) {
281 nir_instr
*use_instr
= use_src
->parent_instr
;
283 gcm_schedule_late_instr(use_instr
, state
);
285 /* Phi instructions are a bit special. SSA definitions don't have to
286 * dominate the sources of the phi nodes that use them; instead, they
287 * have to dominate the predecessor block corresponding to the phi
288 * source. We handle this by looking through the sources, finding
289 * any that are usingg this SSA def, and using those blocks instead
290 * of the one the phi lives in.
292 if (use_instr
->type
== nir_instr_type_phi
) {
293 nir_phi_instr
*phi
= nir_instr_as_phi(use_instr
);
295 nir_foreach_phi_src(phi_src
, phi
) {
296 if (phi_src
->src
.ssa
== def
)
297 lca
= nir_dominance_lca(lca
, phi_src
->pred
);
300 lca
= nir_dominance_lca(lca
, use_instr
->block
);
304 nir_foreach_if_use(use_src
, def
) {
305 nir_if
*if_stmt
= use_src
->parent_if
;
307 /* For if statements, we consider the block to be the one immediately
308 * preceding the if CF node.
310 nir_block
*pred_block
=
311 nir_cf_node_as_block(nir_cf_node_prev(&if_stmt
->cf_node
));
313 lca
= nir_dominance_lca(lca
, pred_block
);
316 /* Some instructions may never be used. We'll just leave them scheduled
317 * early and let dead code clean them up.
322 /* We know have the LCA of all of the uses. If our invariants hold,
323 * this is dominated by the block that we chose when scheduling early.
324 * We now walk up the dominance tree and pick the lowest block that is
325 * as far outside loops as we can get.
327 nir_block
*best
= lca
;
328 while (lca
!= def
->parent_instr
->block
) {
330 if (state
->blocks
[lca
->index
].loop_depth
<
331 state
->blocks
[best
->index
].loop_depth
)
335 def
->parent_instr
->block
= best
;
340 /** Schedules an instruction late
342 * This function performs a depth-first search starting at the given
343 * instruction and proceeding through its uses to schedule instructions as
344 * late as they can reasonably go in the dominance tree. The instructions
345 * are "scheduled" by updating their instr->block field.
347 * The name of this function is actually a bit of a misnomer as it doesn't
348 * schedule them "as late as possible" as the paper implies. Instead, it
349 * first finds the lates possible place it can schedule the instruction and
350 * then possibly schedules it earlier than that. The actual location is as
351 * far down the tree as we can go while trying to stay out of loops.
354 gcm_schedule_late_instr(nir_instr
*instr
, struct gcm_state
*state
)
356 if (instr
->pass_flags
& GCM_INSTR_SCHEDULED_LATE
)
359 instr
->pass_flags
|= GCM_INSTR_SCHEDULED_LATE
;
361 /* Pinned instructions are already scheduled so we don't need to do
362 * anything. Also, bailing here keeps us from ever following phi nodes
363 * which can be back-edges.
365 if (instr
->pass_flags
& GCM_INSTR_PINNED
)
368 nir_foreach_ssa_def(instr
, gcm_schedule_late_def
, state
);
372 gcm_place_instr(nir_instr
*instr
, struct gcm_state
*state
);
375 gcm_place_instr_def(nir_ssa_def
*def
, void *state
)
377 nir_foreach_use(use_src
, def
)
378 gcm_place_instr(use_src
->parent_instr
, state
);
383 /** Places an instrution back into the program
385 * The earlier passes of GCM simply choose blocks for each instruction and
386 * otherwise leave them alone. This pass actually places the instructions
387 * into their chosen blocks.
389 * To do so, we use a standard post-order depth-first search linearization
390 * algorithm. We walk over the uses of the given instruction and ensure
391 * that they are placed and then place this instruction. Because we are
392 * working on multiple blocks at a time, we keep track of the last inserted
393 * instruction per-block in the state structure's block_info array. When
394 * we insert an instruction in a block we insert it before the last
395 * instruction inserted in that block rather than the last instruction
399 gcm_place_instr(nir_instr
*instr
, struct gcm_state
*state
)
401 if (instr
->pass_flags
& GCM_INSTR_PLACED
)
404 instr
->pass_flags
|= GCM_INSTR_PLACED
;
406 /* Phi nodes are our once source of back-edges. Since right now we are
407 * only doing scheduling within blocks, we don't need to worry about
408 * them since they are always at the top. Just skip them completely.
410 if (instr
->type
== nir_instr_type_phi
) {
411 assert(instr
->pass_flags
& GCM_INSTR_PINNED
);
415 nir_foreach_ssa_def(instr
, gcm_place_instr_def
, state
);
417 if (instr
->pass_flags
& GCM_INSTR_PINNED
) {
418 /* Pinned instructions have an implicit dependence on the pinned
419 * instructions that come after them in the block. Since the pinned
420 * instructions will naturally "chain" together, we only need to
421 * explicitly visit one of them.
423 for (nir_instr
*after
= nir_instr_next(instr
);
425 after
= nir_instr_next(after
)) {
426 if (after
->pass_flags
& GCM_INSTR_PINNED
) {
427 gcm_place_instr(after
, state
);
433 struct gcm_block_info
*block_info
= &state
->blocks
[instr
->block
->index
];
434 if (!(instr
->pass_flags
& GCM_INSTR_PINNED
)) {
435 exec_node_remove(&instr
->node
);
437 if (block_info
->last_instr
) {
438 exec_node_insert_node_before(&block_info
->last_instr
->node
,
441 /* Schedule it at the end of the block */
442 nir_instr
*jump_instr
= nir_block_last_instr(instr
->block
);
443 if (jump_instr
&& jump_instr
->type
== nir_instr_type_jump
) {
444 exec_node_insert_node_before(&jump_instr
->node
, &instr
->node
);
446 exec_list_push_tail(&instr
->block
->instr_list
, &instr
->node
);
451 block_info
->last_instr
= instr
;
455 opt_gcm_impl(nir_function_impl
*impl
)
457 struct gcm_state state
;
461 exec_list_make_empty(&state
.instrs
);
462 state
.blocks
= rzalloc_array(NULL
, struct gcm_block_info
, impl
->num_blocks
);
464 nir_metadata_require(impl
, nir_metadata_block_index
|
465 nir_metadata_dominance
);
467 gcm_build_block_info(&impl
->body
, &state
, 0);
469 nir_foreach_block(block
, impl
) {
470 gcm_pin_instructions_block(block
, &state
);
473 foreach_list_typed(nir_instr
, instr
, node
, &state
.instrs
)
474 gcm_schedule_early_instr(instr
, &state
);
476 foreach_list_typed(nir_instr
, instr
, node
, &state
.instrs
)
477 gcm_schedule_late_instr(instr
, &state
);
479 while (!exec_list_is_empty(&state
.instrs
)) {
480 nir_instr
*instr
= exec_node_data(nir_instr
,
481 state
.instrs
.tail_sentinel
.prev
, node
);
482 gcm_place_instr(instr
, &state
);
485 ralloc_free(state
.blocks
);
489 nir_opt_gcm(nir_shader
*shader
)
491 nir_foreach_function(function
, shader
) {
493 opt_gcm_impl(function
->impl
);