2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Jason Ekstrand (jason@jlekstrand.net)
29 #include "nir_control_flow.h"
32 * Implements a small peephole optimization that looks for
43 * and replaces it with:
51 * where the SSA defs are ALU operations or other cheap instructions (not
52 * texturing, for example).
54 * If the number of ALU operations in the branches is greater than the limit
55 * parameter, then the optimization is skipped. In limit=0 mode, the SSA defs
56 * must only be MOVs which we expect to get copy-propagated away once they're
57 * out of the inner blocks.
61 block_check_for_allowed_instrs(nir_block
*block
, unsigned *count
, bool alu_ok
)
63 nir_foreach_instr(instr
, block
) {
64 switch (instr
->type
) {
65 case nir_instr_type_intrinsic
: {
66 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
68 switch (intrin
->intrinsic
) {
69 case nir_intrinsic_load_deref
:
70 switch (nir_src_as_deref(intrin
->src
[0])->mode
) {
71 case nir_var_shader_in
:
80 case nir_intrinsic_load_uniform
:
92 case nir_instr_type_deref
:
93 case nir_instr_type_load_const
:
96 case nir_instr_type_alu
: {
97 nir_alu_instr
*mov
= nir_instr_as_alu(instr
);
111 /* It must be a move-like operation. */
118 if (!mov
->dest
.dest
.is_ssa
)
124 /* Can't handle saturate */
125 if (mov
->dest
.saturate
)
128 /* It cannot have any if-uses */
129 if (!list_empty(&mov
->dest
.dest
.ssa
.if_uses
))
132 /* The only uses of this definition must be phis in the successor */
133 nir_foreach_use(use
, &mov
->dest
.dest
.ssa
) {
134 if (use
->parent_instr
->type
!= nir_instr_type_phi
||
135 use
->parent_instr
->block
!= block
->successors
[0])
151 nir_opt_peephole_select_block(nir_block
*block
, nir_shader
*shader
,
154 if (nir_cf_node_is_first(&block
->cf_node
))
157 nir_cf_node
*prev_node
= nir_cf_node_prev(&block
->cf_node
);
158 if (prev_node
->type
!= nir_cf_node_if
)
161 nir_if
*if_stmt
= nir_cf_node_as_if(prev_node
);
162 nir_block
*then_block
= nir_if_first_then_block(if_stmt
);
163 nir_block
*else_block
= nir_if_first_else_block(if_stmt
);
165 /* We can only have one block in each side ... */
166 if (nir_if_last_then_block(if_stmt
) != then_block
||
167 nir_if_last_else_block(if_stmt
) != else_block
)
170 /* ... and those blocks must only contain "allowed" instructions. */
172 if (!block_check_for_allowed_instrs(then_block
, &count
, limit
!= 0) ||
173 !block_check_for_allowed_instrs(else_block
, &count
, limit
!= 0))
179 /* At this point, we know that the previous CFG node is an if-then
180 * statement containing only moves to phi nodes in this block. We can
181 * just remove that entire CF node and replace all of the phi nodes with
185 nir_block
*prev_block
= nir_cf_node_as_block(nir_cf_node_prev(prev_node
));
187 /* First, we move the remaining instructions from the blocks to the
188 * block before. We have already guaranteed that this is safe by
189 * calling block_check_for_allowed_instrs()
191 nir_foreach_instr_safe(instr
, then_block
) {
192 exec_node_remove(&instr
->node
);
193 instr
->block
= prev_block
;
194 exec_list_push_tail(&prev_block
->instr_list
, &instr
->node
);
197 nir_foreach_instr_safe(instr
, else_block
) {
198 exec_node_remove(&instr
->node
);
199 instr
->block
= prev_block
;
200 exec_list_push_tail(&prev_block
->instr_list
, &instr
->node
);
203 nir_foreach_instr_safe(instr
, block
) {
204 if (instr
->type
!= nir_instr_type_phi
)
207 nir_phi_instr
*phi
= nir_instr_as_phi(instr
);
208 nir_alu_instr
*sel
= nir_alu_instr_create(shader
, nir_op_bcsel
);
209 nir_src_copy(&sel
->src
[0].src
, &if_stmt
->condition
, sel
);
210 /* Splat the condition to all channels */
211 memset(sel
->src
[0].swizzle
, 0, sizeof sel
->src
[0].swizzle
);
213 assert(exec_list_length(&phi
->srcs
) == 2);
214 nir_foreach_phi_src(src
, phi
) {
215 assert(src
->pred
== then_block
|| src
->pred
== else_block
);
216 assert(src
->src
.is_ssa
);
218 unsigned idx
= src
->pred
== then_block
? 1 : 2;
219 nir_src_copy(&sel
->src
[idx
].src
, &src
->src
, sel
);
222 nir_ssa_dest_init(&sel
->instr
, &sel
->dest
.dest
,
223 phi
->dest
.ssa
.num_components
,
224 phi
->dest
.ssa
.bit_size
, phi
->dest
.ssa
.name
);
225 sel
->dest
.write_mask
= (1 << phi
->dest
.ssa
.num_components
) - 1;
227 nir_ssa_def_rewrite_uses(&phi
->dest
.ssa
,
228 nir_src_for_ssa(&sel
->dest
.dest
.ssa
));
230 nir_instr_insert_before(&phi
->instr
, &sel
->instr
);
231 nir_instr_remove(&phi
->instr
);
234 nir_cf_node_remove(&if_stmt
->cf_node
);
239 nir_opt_peephole_select_impl(nir_function_impl
*impl
, unsigned limit
)
241 nir_shader
*shader
= impl
->function
->shader
;
242 bool progress
= false;
244 nir_foreach_block_safe(block
, impl
) {
245 progress
|= nir_opt_peephole_select_block(block
, shader
, limit
);
249 nir_metadata_preserve(impl
, nir_metadata_none
);
255 nir_opt_peephole_select(nir_shader
*shader
, unsigned limit
)
257 bool progress
= false;
259 nir_foreach_function(function
, shader
) {
261 progress
|= nir_opt_peephole_select_impl(function
->impl
, limit
);