src/compiler/nir/nir_opt_peephole_select.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Jason Ekstrand (jason@jlekstrand.net)
  25  *
  26  */
  27
  28 #include "nir.h"
  29 #include "nir_control_flow.h"
  30
  31 /*
  32  * Implements a small peephole optimization that looks for
  33  *
  34  * if (cond) {
  35  *    <then SSA defs>
  36  * } else {
  37  *    <else SSA defs>
  38  * }
  39  * phi
  40  * ...
  41  * phi
  42  *
  43  * and replaces it with:
  44  *
  45  * <then SSA defs>
  46  * <else SSA defs>
  47  * bcsel
  48  * ...
  49  * bcsel
  50  *
  51  * where the SSA defs are ALU operations or other cheap instructions (not
  52  * texturing, for example).
  53  *
  54  * If the number of ALU operations in the branches is greater than the limit
  55  * parameter, then the optimization is skipped.  In limit=0 mode, the SSA defs
  56  * must only be MOVs which we expect to get copy-propagated away once they're
  57  * out of the inner blocks.
  58  */
  59
  60 static bool
  61 block_check_for_allowed_instrs(nir_block *block, unsigned *count,
  62                                bool alu_ok, bool indirect_load_ok,
  63                                bool expensive_alu_ok)
  64 {
  65    nir_foreach_instr(instr, block) {
  66       switch (instr->type) {
  67       case nir_instr_type_intrinsic: {
  68          nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
  69
  70          switch (intrin->intrinsic) {
  71          case nir_intrinsic_load_deref: {
  72             nir_deref_instr *const deref = nir_src_as_deref(intrin->src[0]);
  73
  74             switch (deref->mode) {
  75             case nir_var_shader_in:
  76             case nir_var_uniform:
  77                /* Don't try to remove flow control around an indirect load
  78                 * because that flow control may be trying to avoid invalid
  79                 * loads.
  80                 */
  81                if (!indirect_load_ok && nir_deref_instr_has_indirect(deref))
  82                   return false;
  83
  84                break;
  85
  86             default:
  87                return false;
  88             }
  89             break;
  90          }
  91
  92          case nir_intrinsic_load_uniform:
  93             if (!alu_ok)
  94                return false;
  95             break;
  96
  97          default:
  98             return false;
  99          }
 100
 101          break;
 102       }
 103
 104       case nir_instr_type_deref:
 105       case nir_instr_type_load_const:
 106          break;
 107
 108       case nir_instr_type_alu: {
 109          nir_alu_instr *mov = nir_instr_as_alu(instr);
 110          switch (mov->op) {
 111          case nir_op_fmov:
 112          case nir_op_imov:
 113          case nir_op_fneg:
 114          case nir_op_ineg:
 115          case nir_op_fabs:
 116          case nir_op_iabs:
 117          case nir_op_vec2:
 118          case nir_op_vec3:
 119          case nir_op_vec4:
 120             break;
 121
 122          case nir_op_fcos:
 123          case nir_op_fdiv:
 124          case nir_op_fexp2:
 125          case nir_op_flog2:
 126          case nir_op_fmod:
 127          case nir_op_fpow:
 128          case nir_op_frcp:
 129          case nir_op_frem:
 130          case nir_op_frsq:
 131          case nir_op_fsin:
 132          case nir_op_idiv:
 133          case nir_op_irem:
 134          case nir_op_udiv:
 135             if (!alu_ok || !expensive_alu_ok)
 136                return false;
 137
 138             break;
 139
 140          default:
 141             if (!alu_ok) {
 142                /* It must be a move-like operation. */
 143                return false;
 144             }
 145             break;
 146          }
 147
 148          /* It must be SSA */
 149          if (!mov->dest.dest.is_ssa)
 150             return false;
 151
 152          if (alu_ok) {
 153             (*count)++;
 154          } else {
 155             /* Can't handle saturate */
 156             if (mov->dest.saturate)
 157                return false;
 158
 159             /* It cannot have any if-uses */
 160             if (!list_empty(&mov->dest.dest.ssa.if_uses))
 161                return false;
 162
 163             /* The only uses of this definition must be phis in the successor */
 164             nir_foreach_use(use, &mov->dest.dest.ssa) {
 165                if (use->parent_instr->type != nir_instr_type_phi ||
 166                    use->parent_instr->block != block->successors[0])
 167                   return false;
 168             }
 169          }
 170          break;
 171       }
 172
 173       default:
 174          return false;
 175       }
 176    }
 177
 178    return true;
 179 }
 180
 181 static bool
 182 nir_opt_peephole_select_block(nir_block *block, nir_shader *shader,
 183                               unsigned limit, bool indirect_load_ok,
 184                               bool expensive_alu_ok)
 185 {
 186    if (nir_cf_node_is_first(&block->cf_node))
 187       return false;
 188
 189    nir_cf_node *prev_node = nir_cf_node_prev(&block->cf_node);
 190    if (prev_node->type != nir_cf_node_if)
 191       return false;
 192
 193    nir_if *if_stmt = nir_cf_node_as_if(prev_node);
 194
 195    if (if_stmt->control == nir_selection_control_dont_flatten)
 196       return false;
 197
 198    nir_block *then_block = nir_if_first_then_block(if_stmt);
 199    nir_block *else_block = nir_if_first_else_block(if_stmt);
 200
 201    /* We can only have one block in each side ... */
 202    if (nir_if_last_then_block(if_stmt) != then_block ||
 203        nir_if_last_else_block(if_stmt) != else_block)
 204       return false;
 205
 206    if (if_stmt->control == nir_selection_control_flatten) {
 207       /* Override driver defaults */
 208       indirect_load_ok = true;
 209       expensive_alu_ok = true;
 210    }
 211
 212    /* ... and those blocks must only contain "allowed" instructions. */
 213    unsigned count = 0;
 214    if (!block_check_for_allowed_instrs(then_block, &count, limit != 0,
 215                                        indirect_load_ok, expensive_alu_ok) ||
 216        !block_check_for_allowed_instrs(else_block, &count, limit != 0,
 217                                        indirect_load_ok, expensive_alu_ok))
 218       return false;
 219
 220    if (count > limit && if_stmt->control != nir_selection_control_flatten)
 221       return false;
 222
 223    /* At this point, we know that the previous CFG node is an if-then
 224     * statement containing only moves to phi nodes in this block.  We can
 225     * just remove that entire CF node and replace all of the phi nodes with
 226     * selects.
 227     */
 228
 229    nir_block *prev_block = nir_cf_node_as_block(nir_cf_node_prev(prev_node));
 230
 231    /* First, we move the remaining instructions from the blocks to the
 232     * block before.  We have already guaranteed that this is safe by
 233     * calling block_check_for_allowed_instrs()
 234     */
 235    nir_foreach_instr_safe(instr, then_block) {
 236       exec_node_remove(&instr->node);
 237       instr->block = prev_block;
 238       exec_list_push_tail(&prev_block->instr_list, &instr->node);
 239    }
 240
 241    nir_foreach_instr_safe(instr, else_block) {
 242       exec_node_remove(&instr->node);
 243       instr->block = prev_block;
 244       exec_list_push_tail(&prev_block->instr_list, &instr->node);
 245    }
 246
 247    nir_foreach_instr_safe(instr, block) {
 248       if (instr->type != nir_instr_type_phi)
 249          break;
 250
 251       nir_phi_instr *phi = nir_instr_as_phi(instr);
 252       nir_alu_instr *sel = nir_alu_instr_create(shader, nir_op_bcsel);
 253       nir_src_copy(&sel->src[0].src, &if_stmt->condition, sel);
 254       /* Splat the condition to all channels */
 255       memset(sel->src[0].swizzle, 0, sizeof sel->src[0].swizzle);
 256
 257       assert(exec_list_length(&phi->srcs) == 2);
 258       nir_foreach_phi_src(src, phi) {
 259          assert(src->pred == then_block || src->pred == else_block);
 260          assert(src->src.is_ssa);
 261
 262          unsigned idx = src->pred == then_block ? 1 : 2;
 263          nir_src_copy(&sel->src[idx].src, &src->src, sel);
 264       }
 265
 266       nir_ssa_dest_init(&sel->instr, &sel->dest.dest,
 267                         phi->dest.ssa.num_components,
 268                         phi->dest.ssa.bit_size, phi->dest.ssa.name);
 269       sel->dest.write_mask = (1 << phi->dest.ssa.num_components) - 1;
 270
 271       nir_ssa_def_rewrite_uses(&phi->dest.ssa,
 272                                nir_src_for_ssa(&sel->dest.dest.ssa));
 273
 274       nir_instr_insert_before(&phi->instr, &sel->instr);
 275       nir_instr_remove(&phi->instr);
 276    }
 277
 278    nir_cf_node_remove(&if_stmt->cf_node);
 279    return true;
 280 }
 281
 282 static bool
 283 nir_opt_peephole_select_impl(nir_function_impl *impl, unsigned limit,
 284                              bool indirect_load_ok, bool expensive_alu_ok)
 285 {
 286    nir_shader *shader = impl->function->shader;
 287    bool progress = false;
 288
 289    nir_foreach_block_safe(block, impl) {
 290       progress |= nir_opt_peephole_select_block(block, shader, limit,
 291                                                 indirect_load_ok,
 292                                                 expensive_alu_ok);
 293    }
 294
 295    if (progress) {
 296       nir_metadata_preserve(impl, nir_metadata_none);
 297    } else {
 298 #ifndef NDEBUG
 299       impl->valid_metadata &= ~nir_metadata_not_properly_reset;
 300 #endif
 301    }
 302
 303    return progress;
 304 }
 305
 306 bool
 307 nir_opt_peephole_select(nir_shader *shader, unsigned limit,
 308                         bool indirect_load_ok, bool expensive_alu_ok)
 309 {
 310    bool progress = false;
 311
 312    nir_foreach_function(function, shader) {
 313       if (function->impl)
 314          progress |= nir_opt_peephole_select_impl(function->impl, limit,
 315                                                   indirect_load_ok,
 316                                                   expensive_alu_ok);
 317    }
 318
 319    return progress;
 320 }