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26 #include "util/u_dynarray.h"
30 * Implements basic-block-level prepass instruction scheduling in NIR to
31 * manage register pressure.
33 * This is based on the Goodman/Hsu paper (1988, cached copy at
34 * https://people.freedesktop.org/~anholt/scheduling-goodman-hsu.pdf). We
35 * make up the DDG for NIR (which can be mostly done using the NIR def/use
36 * chains for SSA instructions, plus some edges for ordering register writes
37 * vs reads, and some more for ordering intrinsics). Then we pick heads off
38 * of the DDG using their heuristic to emit the NIR instructions back into the
39 * block in their new order.
41 * The hard case for prepass scheduling on GPUs seems to always be consuming
42 * texture/ubo results. The register pressure heuristic doesn't want to pick
43 * an instr that starts consuming texture results because it usually won't be
44 * the only usage, so that instruction will increase pressure.
46 * If you try to force consumption of tex results always, then in a case where
47 * single sample is used for many outputs, you'll end up picking every other
48 * user and expanding register pressure. The partially_evaluated_path flag
49 * helps tremendously, in that if you happen for whatever reason to pick a
50 * texture sample's output, then you'll try to finish off that sample. Future
51 * work may include doing some local search before locking in a choice, to try
52 * to more reliably find the case where just a few choices going against the
53 * heuristic can manage to free the whole vector.
59 * Represents a node in the DDG for a NIR instruction.
62 struct dag_node dag
; /* must be first for our u_dynarray_foreach */
64 bool partially_evaluated_path
;
66 /* Approximate estimate of the delay between starting this instruction and
67 * its results being available.
69 * Accuracy is not too important, given that we're prepass scheduling here
70 * and just trying to reduce excess dependencies introduced by a register
71 * allocator by stretching out the live intervals of expensive
76 /* Cost of the maximum-delay path from this node to the leaves. */
79 /* scoreboard->time value when this instruction can be scheduled without
80 * any stalls expected.
90 /* Mapping from nir_register * or nir_ssa_def * to a struct set of
91 * instructions remaining to be scheduled using the register.
93 struct hash_table
*remaining_uses
;
95 /* Map from nir_instr to nir_schedule_node * */
96 struct hash_table
*instr_map
;
98 /* Set of nir_register * or nir_ssa_def * that have had any instruction
101 struct set
*live_values
;
103 /* An abstract approximation of the number of nir_scheduler_node->delay
104 * units since the start of the shader.
108 /* Number of channels currently used by the NIR instructions that have been
113 /* Number of channels that may be in use before we switch to the
114 * pressure-prioritizing scheduling heuristic.
117 } nir_schedule_scoreboard
;
119 /* When walking the instructions in reverse, we use this flag to swap
120 * before/after in add_dep().
122 enum direction
{ F
, R
};
125 nir_schedule_scoreboard
*scoreboard
;
127 /* Map from nir_register to nir_schedule_node * */
128 struct hash_table
*reg_map
;
130 /* Scheduler nodes for last instruction involved in some class of dependency.
132 nir_schedule_node
*load_input
;
133 nir_schedule_node
*store_shared
;
134 nir_schedule_node
*unknown_intrinsic
;
135 nir_schedule_node
*discard
;
136 nir_schedule_node
*jump
;
142 _mesa_hash_table_search_data(struct hash_table
*ht
, void *key
)
144 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, key
);
150 static nir_schedule_node
*
151 nir_schedule_get_node(struct hash_table
*instr_map
, nir_instr
*instr
)
153 return _mesa_hash_table_search_data(instr_map
, instr
);
157 nir_schedule_scoreboard_get_src(nir_schedule_scoreboard
*scoreboard
, nir_src
*src
)
160 return _mesa_hash_table_search_data(scoreboard
->remaining_uses
, src
->ssa
);
162 return _mesa_hash_table_search_data(scoreboard
->remaining_uses
,
168 nir_schedule_def_pressure(nir_ssa_def
*def
)
170 return def
->num_components
;
174 nir_schedule_src_pressure(nir_src
*src
)
177 return nir_schedule_def_pressure(src
->ssa
);
179 return src
->reg
.reg
->num_components
;
183 nir_schedule_dest_pressure(nir_dest
*dest
)
186 return nir_schedule_def_pressure(&dest
->ssa
);
188 return dest
->reg
.reg
->num_components
;
192 * Adds a dependency such that @after must appear in the final program after
195 * We add @before as a child of @after, so that DAG heads are the outputs of
196 * the program and we make our scheduling decisions bottom to top.
199 add_dep(nir_deps_state
*state
,
200 nir_schedule_node
*before
,
201 nir_schedule_node
*after
)
203 if (!before
|| !after
)
206 assert(before
!= after
);
209 dag_add_edge(&before
->dag
, &after
->dag
, NULL
);
211 dag_add_edge(&after
->dag
, &before
->dag
, NULL
);
216 add_read_dep(nir_deps_state
*state
,
217 nir_schedule_node
*before
,
218 nir_schedule_node
*after
)
220 add_dep(state
, before
, after
);
224 add_write_dep(nir_deps_state
*state
,
225 nir_schedule_node
**before
,
226 nir_schedule_node
*after
)
228 add_dep(state
, *before
, after
);
233 nir_schedule_reg_src_deps(nir_src
*src
, void *in_state
)
235 nir_deps_state
*state
= in_state
;
240 struct hash_entry
*entry
= _mesa_hash_table_search(state
->reg_map
,
244 nir_schedule_node
*dst_n
= entry
->data
;
246 nir_schedule_node
*src_n
=
247 nir_schedule_get_node(state
->scoreboard
->instr_map
,
250 add_dep(state
, dst_n
, src_n
);
256 nir_schedule_reg_dest_deps(nir_dest
*dest
, void *in_state
)
258 nir_deps_state
*state
= in_state
;
263 nir_schedule_node
*dest_n
=
264 nir_schedule_get_node(state
->scoreboard
->instr_map
,
265 dest
->reg
.parent_instr
);
267 struct hash_entry
*entry
= _mesa_hash_table_search(state
->reg_map
,
270 _mesa_hash_table_insert(state
->reg_map
, dest
->reg
.reg
, dest_n
);
273 nir_schedule_node
**before
= (nir_schedule_node
**)&entry
->data
;
275 add_write_dep(state
, before
, dest_n
);
281 nir_schedule_ssa_deps(nir_ssa_def
*def
, void *in_state
)
283 nir_deps_state
*state
= in_state
;
284 struct hash_table
*instr_map
= state
->scoreboard
->instr_map
;
285 nir_schedule_node
*def_n
= nir_schedule_get_node(instr_map
, def
->parent_instr
);
287 nir_foreach_use(src
, def
) {
288 nir_schedule_node
*use_n
= nir_schedule_get_node(instr_map
,
291 add_read_dep(state
, def_n
, use_n
);
298 nir_schedule_intrinsic_deps(nir_deps_state
*state
,
299 nir_intrinsic_instr
*instr
)
301 nir_schedule_node
*n
= nir_schedule_get_node(state
->scoreboard
->instr_map
,
304 switch (instr
->intrinsic
) {
305 case nir_intrinsic_load_uniform
:
306 case nir_intrinsic_load_ubo
:
307 case nir_intrinsic_load_front_face
:
310 case nir_intrinsic_discard
:
311 case nir_intrinsic_discard_if
:
312 /* We are adding two dependencies:
314 * * A individual one that we could use to add a read_dep while handling
317 * * Include it on the unknown intrinsic set, as we want discard to be
318 * serialized in in the same order relative to intervening stores or
319 * atomic accesses to SSBOs and images
321 add_write_dep(state
, &state
->discard
, n
);
322 add_write_dep(state
, &state
->unknown_intrinsic
, n
);
325 case nir_intrinsic_store_output
:
326 /* For some non-FS shader stages, or for some hardware, output stores
327 * affect the same shared memory as input loads.
329 if (state
->scoreboard
->shader
->info
.stage
!= MESA_SHADER_FRAGMENT
)
330 add_write_dep(state
, &state
->load_input
, n
);
332 /* Make sure that preceding discards stay before the store_output */
333 add_read_dep(state
, state
->discard
, n
);
337 case nir_intrinsic_load_input
:
338 case nir_intrinsic_load_per_vertex_input
:
339 add_read_dep(state
, state
->load_input
, n
);
342 case nir_intrinsic_load_shared
:
343 /* Don't move load_shared beyond a following store_shared, as it could
346 add_read_dep(state
, state
->store_shared
, n
);
349 case nir_intrinsic_store_shared
:
350 add_write_dep(state
, &state
->store_shared
, n
);
353 case nir_intrinsic_control_barrier
:
354 case nir_intrinsic_memory_barrier_shared
:
355 add_write_dep(state
, &state
->store_shared
, n
);
357 /* Serialize against ssbos/atomics/etc. */
358 add_write_dep(state
, &state
->unknown_intrinsic
, n
);
362 /* Attempt to handle other intrinsics that we haven't individually
363 * categorized by serializing them in the same order relative to each
366 add_write_dep(state
, &state
->unknown_intrinsic
, n
);
372 * Common code for dependencies that need to be tracked both forward and
375 * This is for things like "all reads of r4 have to happen between the r4
376 * writes that surround them".
379 nir_schedule_calculate_deps(nir_deps_state
*state
, nir_schedule_node
*n
)
381 nir_instr
*instr
= n
->instr
;
383 /* For NIR SSA defs, we only need to do a single pass of making the uses
387 nir_foreach_ssa_def(instr
, nir_schedule_ssa_deps
, state
);
389 /* For NIR regs, track the last writer in the scheduler state so that we
390 * can keep the writes in order and let reads get reordered only between
393 nir_foreach_src(instr
, nir_schedule_reg_src_deps
, state
);
395 nir_foreach_dest(instr
, nir_schedule_reg_dest_deps
, state
);
397 /* Make sure any other instructions keep their positions relative to
400 if (instr
->type
!= nir_instr_type_jump
)
401 add_read_dep(state
, state
->jump
, n
);
403 switch (instr
->type
) {
404 case nir_instr_type_ssa_undef
:
405 case nir_instr_type_load_const
:
406 case nir_instr_type_alu
:
407 case nir_instr_type_deref
:
410 case nir_instr_type_tex
:
411 /* Don't move texture ops before a discard, as that could increase
412 * memory bandwidth for reading the discarded samples.
414 add_read_dep(state
, state
->discard
, n
);
417 case nir_instr_type_jump
:
418 add_write_dep(state
, &state
->jump
, n
);
421 case nir_instr_type_call
:
422 unreachable("Calls should have been lowered");
425 case nir_instr_type_parallel_copy
:
426 unreachable("Parallel copies should have been lowered");
429 case nir_instr_type_phi
:
430 unreachable("nir_schedule() should be called after lowering from SSA");
433 case nir_instr_type_intrinsic
:
434 nir_schedule_intrinsic_deps(state
, nir_instr_as_intrinsic(instr
));
440 calculate_forward_deps(nir_schedule_scoreboard
*scoreboard
, nir_block
*block
)
442 nir_deps_state state
= {
443 .scoreboard
= scoreboard
,
445 .reg_map
= _mesa_pointer_hash_table_create(NULL
),
448 nir_foreach_instr(instr
, block
) {
449 nir_schedule_node
*node
= nir_schedule_get_node(scoreboard
->instr_map
,
451 nir_schedule_calculate_deps(&state
, node
);
454 ralloc_free(state
.reg_map
);
458 calculate_reverse_deps(nir_schedule_scoreboard
*scoreboard
, nir_block
*block
)
460 nir_deps_state state
= {
461 .scoreboard
= scoreboard
,
463 .reg_map
= _mesa_pointer_hash_table_create(NULL
),
466 nir_foreach_instr_reverse(instr
, block
) {
467 nir_schedule_node
*node
= nir_schedule_get_node(scoreboard
->instr_map
,
469 nir_schedule_calculate_deps(&state
, node
);
472 ralloc_free(state
.reg_map
);
476 nir_schedule_scoreboard
*scoreboard
;
478 } nir_schedule_regs_freed_state
;
481 nir_schedule_regs_freed_src_cb(nir_src
*src
, void *in_state
)
483 nir_schedule_regs_freed_state
*state
= in_state
;
484 nir_schedule_scoreboard
*scoreboard
= state
->scoreboard
;
485 struct set
*remaining_uses
= nir_schedule_scoreboard_get_src(scoreboard
, src
);
487 if (remaining_uses
->entries
== 1 &&
488 _mesa_set_search(remaining_uses
, src
->parent_instr
)) {
489 state
->regs_freed
+= nir_schedule_src_pressure(src
);
496 nir_schedule_regs_freed_def_cb(nir_ssa_def
*def
, void *in_state
)
498 nir_schedule_regs_freed_state
*state
= in_state
;
500 state
->regs_freed
-= nir_schedule_def_pressure(def
);
506 nir_schedule_regs_freed_dest_cb(nir_dest
*dest
, void *in_state
)
508 nir_schedule_regs_freed_state
*state
= in_state
;
509 nir_schedule_scoreboard
*scoreboard
= state
->scoreboard
;
514 nir_register
*reg
= dest
->reg
.reg
;
516 /* Only the first def of a reg counts against register pressure. */
517 if (!_mesa_set_search(scoreboard
->live_values
, reg
))
518 state
->regs_freed
-= nir_schedule_dest_pressure(dest
);
524 nir_schedule_regs_freed(nir_schedule_scoreboard
*scoreboard
, nir_schedule_node
*n
)
526 nir_schedule_regs_freed_state state
= {
527 .scoreboard
= scoreboard
,
530 nir_foreach_src(n
->instr
, nir_schedule_regs_freed_src_cb
, &state
);
532 nir_foreach_ssa_def(n
->instr
, nir_schedule_regs_freed_def_cb
, &state
);
534 nir_foreach_dest(n
->instr
, nir_schedule_regs_freed_dest_cb
, &state
);
536 return state
.regs_freed
;
540 * Chooses an instruction to schedule using the Goodman/Hsu (1988) CSP (Code
541 * Scheduling for Parallelism) heuristic.
543 * Picks an instruction on the critical that's ready to execute without
544 * stalls, if possible, otherwise picks the instruction on the critical path.
546 static nir_schedule_node
*
547 nir_schedule_choose_instruction_csp(nir_schedule_scoreboard
*scoreboard
)
549 nir_schedule_node
*chosen
= NULL
;
551 /* Find the leader in the ready (shouldn't-stall) set with the maximum
554 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
555 if (scoreboard
->time
< n
->ready_time
)
558 if (!chosen
|| chosen
->max_delay
< n
->max_delay
)
563 fprintf(stderr
, "chose (ready): ");
564 nir_print_instr(chosen
->instr
, stderr
);
565 fprintf(stderr
, "\n");
571 /* Otherwise, choose the leader with the maximum cost. */
572 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
573 if (!chosen
|| chosen
->max_delay
< n
->max_delay
)
577 fprintf(stderr
, "chose (leader): ");
578 nir_print_instr(chosen
->instr
, stderr
);
579 fprintf(stderr
, "\n");
586 * Chooses an instruction to schedule using the Goodman/Hsu (1988) CSR (Code
587 * Scheduling for Register pressure) heuristic.
589 static nir_schedule_node
*
590 nir_schedule_choose_instruction_csr(nir_schedule_scoreboard
*scoreboard
)
592 nir_schedule_node
*chosen
= NULL
;
594 /* Find a ready inst with regs freed and pick the one with max cost. */
595 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
596 if (n
->ready_time
> scoreboard
->time
)
599 int regs_freed
= nir_schedule_regs_freed(scoreboard
, n
);
601 if (regs_freed
> 0 && (!chosen
|| chosen
->max_delay
< n
->max_delay
)) {
607 fprintf(stderr
, "chose (freed+ready): ");
608 nir_print_instr(chosen
->instr
, stderr
);
609 fprintf(stderr
, "\n");
615 /* Find a leader with regs freed and pick the one with max cost. */
616 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
617 int regs_freed
= nir_schedule_regs_freed(scoreboard
, n
);
619 if (regs_freed
> 0 && (!chosen
|| chosen
->max_delay
< n
->max_delay
)) {
625 fprintf(stderr
, "chose (regs freed): ");
626 nir_print_instr(chosen
->instr
, stderr
);
627 fprintf(stderr
, "\n");
633 /* Find a partially evaluated path and try to finish it off */
634 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
635 if (n
->partially_evaluated_path
&&
636 (!chosen
|| chosen
->max_delay
< n
->max_delay
)) {
642 fprintf(stderr
, "chose (partial path): ");
643 nir_print_instr(chosen
->instr
, stderr
);
644 fprintf(stderr
, "\n");
650 /* Contra the paper, pick a leader with no effect on used regs. This may
651 * open up new opportunities, as otherwise a single-operand instr consuming
652 * a value will tend to block finding freeing that value. This had a
653 * massive effect on reducing spilling on V3D.
655 * XXX: Should this prioritize ready?
657 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
658 if (nir_schedule_regs_freed(scoreboard
, n
) != 0)
661 if (!chosen
|| chosen
->max_delay
< n
->max_delay
)
666 fprintf(stderr
, "chose (regs no-op): ");
667 nir_print_instr(chosen
->instr
, stderr
);
668 fprintf(stderr
, "\n");
674 /* Pick the max delay of the remaining ready set. */
675 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
676 if (n
->ready_time
> scoreboard
->time
)
678 if (!chosen
|| chosen
->max_delay
< n
->max_delay
)
683 fprintf(stderr
, "chose (ready max delay): ");
684 nir_print_instr(chosen
->instr
, stderr
);
685 fprintf(stderr
, "\n");
690 /* Pick the max delay of the remaining leaders. */
691 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
692 if (!chosen
|| chosen
->max_delay
< n
->max_delay
)
697 fprintf(stderr
, "chose (max delay): ");
698 nir_print_instr(chosen
->instr
, stderr
);
699 fprintf(stderr
, "\n");
706 dump_state(nir_schedule_scoreboard
*scoreboard
)
708 list_for_each_entry(nir_schedule_node
, n
, &scoreboard
->dag
->heads
, dag
.link
) {
709 fprintf(stderr
, "maxdel %5d ", n
->max_delay
);
710 nir_print_instr(n
->instr
, stderr
);
711 fprintf(stderr
, "\n");
713 util_dynarray_foreach(&n
->dag
.edges
, struct dag_edge
, edge
) {
714 nir_schedule_node
*child
= (nir_schedule_node
*)edge
->child
;
716 fprintf(stderr
, " -> (%d parents) ", child
->dag
.parent_count
);
717 nir_print_instr(child
->instr
, stderr
);
718 fprintf(stderr
, "\n");
724 nir_schedule_mark_use(nir_schedule_scoreboard
*scoreboard
,
726 nir_instr
*reg_or_def_parent
,
729 /* Make the value live if it's the first time it's been used. */
730 if (!_mesa_set_search(scoreboard
->live_values
, reg_or_def
)) {
731 _mesa_set_add(scoreboard
->live_values
, reg_or_def
);
732 scoreboard
->pressure
+= pressure
;
735 /* Make the value dead if it's the last remaining use. Be careful when one
736 * instruction uses a value twice to not decrement pressure twice.
738 struct set
*remaining_uses
=
739 _mesa_hash_table_search_data(scoreboard
->remaining_uses
, reg_or_def
);
740 struct set_entry
*entry
= _mesa_set_search(remaining_uses
, reg_or_def_parent
);
742 _mesa_set_remove(remaining_uses
, entry
);
744 if (remaining_uses
->entries
== 0)
745 scoreboard
->pressure
-= pressure
;
750 nir_schedule_mark_src_scheduled(nir_src
*src
, void *state
)
752 nir_schedule_scoreboard
*scoreboard
= state
;
753 struct set
*remaining_uses
= nir_schedule_scoreboard_get_src(scoreboard
, src
);
755 struct set_entry
*entry
= _mesa_set_search(remaining_uses
,
758 /* Once we've used an SSA value in one instruction, bump the priority of
759 * the other uses so the SSA value can get fully consumed.
761 * We don't do this for registers, and it's would be a hassle and it's
762 * unclear if that would help or not. Also, skip it for constants, as
763 * they're often folded as immediates into backend instructions and have
764 * many unrelated instructions all referencing the same value (0).
767 src
->ssa
->parent_instr
->type
!= nir_instr_type_load_const
) {
768 nir_foreach_use(other_src
, src
->ssa
) {
769 if (other_src
->parent_instr
== src
->parent_instr
)
772 nir_schedule_node
*n
=
773 nir_schedule_get_node(scoreboard
->instr_map
,
774 other_src
->parent_instr
);
776 if (n
&& !n
->partially_evaluated_path
) {
778 fprintf(stderr
, " New partially evaluated path: ");
779 nir_print_instr(n
->instr
, stderr
);
780 fprintf(stderr
, "\n");
783 n
->partially_evaluated_path
= true;
789 nir_schedule_mark_use(scoreboard
,
790 src
->is_ssa
? (void *)src
->ssa
: (void *)src
->reg
.reg
,
792 nir_schedule_src_pressure(src
));
798 nir_schedule_mark_def_scheduled(nir_ssa_def
*def
, void *state
)
800 nir_schedule_scoreboard
*scoreboard
= state
;
802 nir_schedule_mark_use(scoreboard
, def
, def
->parent_instr
,
803 nir_schedule_def_pressure(def
));
809 nir_schedule_mark_dest_scheduled(nir_dest
*dest
, void *state
)
811 nir_schedule_scoreboard
*scoreboard
= state
;
813 /* SSA defs were handled in nir_schedule_mark_def_scheduled()
818 /* XXX: This is not actually accurate for regs -- the last use of a reg may
819 * have a live interval that extends across control flow. We should
820 * calculate the live ranges of regs, and have scheduler nodes for the CF
821 * nodes that also "use" the reg.
823 nir_schedule_mark_use(scoreboard
, dest
->reg
.reg
,
824 dest
->reg
.parent_instr
,
825 nir_schedule_dest_pressure(dest
));
831 nir_schedule_mark_node_scheduled(nir_schedule_scoreboard
*scoreboard
,
832 nir_schedule_node
*n
)
834 nir_foreach_src(n
->instr
, nir_schedule_mark_src_scheduled
, scoreboard
);
835 nir_foreach_ssa_def(n
->instr
, nir_schedule_mark_def_scheduled
, scoreboard
);
836 nir_foreach_dest(n
->instr
, nir_schedule_mark_dest_scheduled
, scoreboard
);
838 util_dynarray_foreach(&n
->dag
.edges
, struct dag_edge
, edge
) {
839 nir_schedule_node
*child
= (nir_schedule_node
*)edge
->child
;
841 child
->ready_time
= MAX2(child
->ready_time
,
842 scoreboard
->time
+ n
->delay
);
844 if (child
->dag
.parent_count
== 1) {
846 fprintf(stderr
, " New DAG head: ");
847 nir_print_instr(child
->instr
, stderr
);
848 fprintf(stderr
, "\n");
853 dag_prune_head(scoreboard
->dag
, &n
->dag
);
855 scoreboard
->time
= MAX2(n
->ready_time
, scoreboard
->time
);
860 nir_schedule_instructions(nir_schedule_scoreboard
*scoreboard
, nir_block
*block
)
862 while (!list_is_empty(&scoreboard
->dag
->heads
)) {
864 fprintf(stderr
, "current list:\n");
865 dump_state(scoreboard
);
868 nir_schedule_node
*chosen
;
869 if (scoreboard
->pressure
< scoreboard
->threshold
)
870 chosen
= nir_schedule_choose_instruction_csp(scoreboard
);
872 chosen
= nir_schedule_choose_instruction_csr(scoreboard
);
874 /* Now that we've scheduled a new instruction, some of its children may
875 * be promoted to the list of instructions ready to be scheduled.
877 nir_schedule_mark_node_scheduled(scoreboard
, chosen
);
879 /* Move the instruction to the end (so our first chosen instructions are
880 * the start of the program).
882 exec_node_remove(&chosen
->instr
->node
);
883 exec_list_push_tail(&block
->instr_list
, &chosen
->instr
->node
);
886 fprintf(stderr
, "\n");
891 nir_schedule_get_delay(nir_instr
*instr
)
893 switch (instr
->type
) {
894 case nir_instr_type_ssa_undef
:
895 case nir_instr_type_load_const
:
896 case nir_instr_type_alu
:
897 case nir_instr_type_deref
:
898 case nir_instr_type_jump
:
899 case nir_instr_type_parallel_copy
:
900 case nir_instr_type_call
:
901 case nir_instr_type_phi
:
904 case nir_instr_type_intrinsic
:
905 /* XXX: Pick a large number for UBO/SSBO/image/shared loads */
908 case nir_instr_type_tex
:
909 /* Pick some large number to try to fetch textures early and sample them
919 nir_schedule_dag_max_delay_cb(struct dag_node
*node
, void *state
)
921 nir_schedule_node
*n
= (nir_schedule_node
*)node
;
922 uint32_t max_delay
= 0;
924 util_dynarray_foreach(&n
->dag
.edges
, struct dag_edge
, edge
) {
925 nir_schedule_node
*child
= (nir_schedule_node
*)edge
->child
;
926 max_delay
= MAX2(child
->max_delay
, max_delay
);
929 n
->max_delay
= MAX2(n
->max_delay
, max_delay
+ n
->delay
);
933 nir_schedule_block(nir_schedule_scoreboard
*scoreboard
, nir_block
*block
)
935 void *mem_ctx
= ralloc_context(NULL
);
936 scoreboard
->instr_map
= _mesa_pointer_hash_table_create(mem_ctx
);
938 scoreboard
->dag
= dag_create(mem_ctx
);
940 nir_foreach_instr(instr
, block
) {
941 nir_schedule_node
*n
=
942 rzalloc(mem_ctx
, nir_schedule_node
);
945 n
->delay
= nir_schedule_get_delay(instr
);
946 dag_init_node(scoreboard
->dag
, &n
->dag
);
948 _mesa_hash_table_insert(scoreboard
->instr_map
, instr
, n
);
951 calculate_forward_deps(scoreboard
, block
);
952 calculate_reverse_deps(scoreboard
, block
);
954 dag_traverse_bottom_up(scoreboard
->dag
, nir_schedule_dag_max_delay_cb
, NULL
);
956 nir_schedule_instructions(scoreboard
, block
);
958 ralloc_free(mem_ctx
);
959 scoreboard
->instr_map
= NULL
;
963 nir_schedule_ssa_def_init_scoreboard(nir_ssa_def
*def
, void *state
)
965 nir_schedule_scoreboard
*scoreboard
= state
;
966 struct set
*def_uses
= _mesa_pointer_set_create(scoreboard
);
968 _mesa_hash_table_insert(scoreboard
->remaining_uses
, def
, def_uses
);
970 _mesa_set_add(def_uses
, def
->parent_instr
);
972 nir_foreach_use(src
, def
) {
973 _mesa_set_add(def_uses
, src
->parent_instr
);
976 /* XXX: Handle if uses */
981 static nir_schedule_scoreboard
*
982 nir_schedule_get_scoreboard(nir_shader
*shader
, int threshold
)
984 nir_schedule_scoreboard
*scoreboard
= rzalloc(NULL
, nir_schedule_scoreboard
);
986 scoreboard
->shader
= shader
;
987 scoreboard
->live_values
= _mesa_pointer_set_create(scoreboard
);
988 scoreboard
->remaining_uses
= _mesa_pointer_hash_table_create(scoreboard
);
989 scoreboard
->threshold
= threshold
;
990 scoreboard
->pressure
= 0;
992 nir_foreach_function(function
, shader
) {
993 nir_foreach_register(reg
, &function
->impl
->registers
) {
994 struct set
*register_uses
=
995 _mesa_pointer_set_create(scoreboard
);
997 _mesa_hash_table_insert(scoreboard
->remaining_uses
, reg
, register_uses
);
999 nir_foreach_use(src
, reg
) {
1000 _mesa_set_add(register_uses
, src
->parent_instr
);
1003 /* XXX: Handle if uses */
1005 nir_foreach_def(dest
, reg
) {
1006 _mesa_set_add(register_uses
, dest
->reg
.parent_instr
);
1010 nir_foreach_block(block
, function
->impl
) {
1011 nir_foreach_instr(instr
, block
) {
1012 nir_foreach_ssa_def(instr
, nir_schedule_ssa_def_init_scoreboard
,
1016 /* XXX: We're ignoring if uses, which may prioritize scheduling other
1017 * uses of the if src even when it doesn't help. That's not many
1018 * values, though, so meh.
1027 nir_schedule_validate_uses(nir_schedule_scoreboard
*scoreboard
)
1033 bool any_uses
= false;
1035 hash_table_foreach(scoreboard
->remaining_uses
, entry
) {
1036 struct set
*remaining_uses
= entry
->data
;
1038 set_foreach(remaining_uses
, instr_entry
) {
1040 fprintf(stderr
, "Tracked uses remain after scheduling. "
1041 "Affected instructions: \n");
1044 nir_print_instr(instr_entry
->key
, stderr
);
1045 fprintf(stderr
, "\n");
1053 * Schedules the NIR instructions to try to decrease stalls (for example,
1054 * delaying texture reads) while managing register pressure.
1056 * The threshold represents "number of NIR register/SSA def channels live
1057 * before switching the scheduling heuristic to reduce register pressure",
1058 * since most of our GPU architectures are scalar (extending to vector with a
1059 * flag wouldn't be hard). This number should be a bit below the number of
1060 * registers available (counting any that may be occupied by system value
1061 * payload values, for example), since the heuristic may not always be able to
1062 * free a register immediately. The amount below the limit is up to you to
1066 nir_schedule(nir_shader
*shader
, int threshold
)
1068 nir_schedule_scoreboard
*scoreboard
= nir_schedule_get_scoreboard(shader
,
1072 fprintf(stderr
, "NIR shader before scheduling:\n");
1073 nir_print_shader(shader
, stderr
);
1076 nir_foreach_function(function
, shader
) {
1077 if (!function
->impl
)
1080 nir_foreach_block(block
, function
->impl
) {
1081 nir_schedule_block(scoreboard
, block
);
1085 nir_schedule_validate_uses(scoreboard
);
1087 ralloc_free(scoreboard
);