src/compiler/nir/tests/builder_tests.cpp

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <gtest/gtest.h>
  25
  26 #include "nir.h"
  27 #include "nir_builder.h"
  28
  29 namespace {
  30
  31 class nir_builder_test : public ::testing::Test {
  32 private:
  33    const glsl_type *type_for_def(nir_ssa_def *def)
  34    {
  35       switch (def->bit_size) {
  36       case 8:  return glsl_type::u8vec(def->num_components);
  37       case 16: return glsl_type::u16vec(def->num_components);
  38       case 32: return glsl_type::uvec(def->num_components);
  39       case 64: return glsl_type::u64vec(def->num_components);
  40       default: unreachable("Invalid bit size");
  41       }
  42    }
  43
  44 protected:
  45    nir_builder_test();
  46    ~nir_builder_test();
  47
  48    void store_test_val(nir_ssa_def *val)
  49    {
  50       nir_variable *var = nir_variable_create(b->shader, nir_var_mem_ssbo,
  51                                               type_for_def(val), NULL);
  52       nir_intrinsic_instr *store =
  53          nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_deref);
  54       store->num_components = val->num_components;
  55       store->src[0] = nir_src_for_ssa(&nir_build_deref_var(b, var)->dest.ssa);
  56       store->src[1] = nir_src_for_ssa(val);
  57       nir_intrinsic_set_write_mask(store, ((1 << val->num_components) - 1));
  58       nir_builder_instr_insert(b, &store->instr);
  59
  60       stores.push_back(store);
  61    }
  62
  63    nir_ssa_def *test_val(unsigned idx)
  64    {
  65       return stores[idx]->src[1].ssa;
  66    }
  67
  68    std::vector<nir_intrinsic_instr *> stores;
  69
  70    void *mem_ctx;
  71    void *lin_ctx;
  72
  73    nir_builder *b;
  74 };
  75
  76 nir_builder_test::nir_builder_test()
  77 {
  78    glsl_type_singleton_init_or_ref();
  79
  80    mem_ctx = ralloc_context(NULL);
  81    lin_ctx = linear_alloc_parent(mem_ctx, 0);
  82    static const nir_shader_compiler_options options = { };
  83    b = rzalloc(mem_ctx, nir_builder);
  84    nir_builder_init_simple_shader(b, mem_ctx, MESA_SHADER_COMPUTE, &options);
  85 }
  86
  87 nir_builder_test::~nir_builder_test()
  88 {
  89    if (HasFailure()) {
  90       printf("\nShader from the failed test:\n\n");
  91       nir_print_shader(b->shader, stdout);
  92    }
  93
  94    ralloc_free(mem_ctx);
  95
  96    glsl_type_singleton_decref();
  97 }
  98
  99 /* Allow grouping the tests while still sharing the helpers. */
 100 class nir_extract_bits_test : public nir_builder_test {};
 101
 102 } // namespace
 103
 104 // TODO: Re-enable this once we get vec8 support in NIR
 105 TEST_F(nir_extract_bits_test, DISABLED_unaligned8)
 106 {
 107    nir_ssa_def *srcs[] = {
 108       nir_imm_int(b, 0x03020100),
 109       nir_imm_ivec2(b, 0x07060504, 0x0b0a0908),
 110    };
 111
 112    store_test_val(nir_extract_bits(b, srcs, 2, 24, 1, 64));
 113
 114    NIR_PASS_V(b->shader, nir_opt_constant_folding);
 115
 116    nir_src val = nir_src_for_ssa(test_val(0));
 117
 118    ASSERT_EQ(nir_src_as_uint(val), 0x0a09080706050403);
 119 }
 120
 121 TEST_F(nir_extract_bits_test, unaligned16_disabled)
 122 {
 123    nir_ssa_def *srcs[] = {
 124       nir_imm_int(b, 0x03020100),
 125       nir_imm_ivec2(b, 0x07060504, 0x0b0a0908),
 126    };
 127
 128    store_test_val(nir_extract_bits(b, srcs, 2, 16, 1, 64));
 129
 130    NIR_PASS_V(b->shader, nir_opt_constant_folding);
 131
 132    nir_src val = nir_src_for_ssa(test_val(0));
 133
 134    ASSERT_EQ(nir_src_as_uint(val), 0x0908070605040302);
 135 }
 136
 137 TEST_F(nir_extract_bits_test, mixed_bit_sizes)
 138 {
 139    nir_ssa_def *srcs[] = {
 140       nir_imm_int(b, 0x03020100),
 141       nir_imm_intN_t(b, 0x04, 8),
 142       nir_imm_intN_t(b, 0x08070605, 32),
 143       nir_vec2(b, nir_imm_intN_t(b, 0x0a09, 16),
 144                   nir_imm_intN_t(b, 0x0c0b, 16)),
 145    };
 146
 147    store_test_val(nir_extract_bits(b, srcs, 4, 24, 2, 32));
 148
 149    NIR_PASS_V(b->shader, nir_opt_constant_folding);
 150
 151    nir_src val = nir_src_for_ssa(test_val(0));
 152
 153    ASSERT_EQ(nir_src_comp_as_uint(val, 0), 0x06050403);
 154    ASSERT_EQ(nir_src_comp_as_uint(val, 1), 0x0a090807);
 155 }