2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "vtn_private.h"
27 vtn_build_subgroup_instr(struct vtn_builder
*b
,
28 nir_intrinsic_op nir_op
,
29 struct vtn_ssa_value
*dst
,
30 struct vtn_ssa_value
*src0
,
35 /* Some of the subgroup operations take an index. SPIR-V allows this to be
36 * any integer type. To make things simpler for drivers, we only support
39 if (index
&& index
->bit_size
!= 32)
40 index
= nir_u2u32(&b
->nb
, index
);
42 vtn_assert(dst
->type
== src0
->type
);
43 if (!glsl_type_is_vector_or_scalar(dst
->type
)) {
44 for (unsigned i
= 0; i
< glsl_get_length(dst
->type
); i
++) {
45 vtn_build_subgroup_instr(b
, nir_op
, dst
->elems
[i
],
46 src0
->elems
[i
], index
,
47 const_idx0
, const_idx1
);
52 nir_intrinsic_instr
*intrin
=
53 nir_intrinsic_instr_create(b
->nb
.shader
, nir_op
);
54 nir_ssa_dest_init_for_type(&intrin
->instr
, &intrin
->dest
,
56 intrin
->num_components
= intrin
->dest
.ssa
.num_components
;
58 intrin
->src
[0] = nir_src_for_ssa(src0
->def
);
60 intrin
->src
[1] = nir_src_for_ssa(index
);
62 intrin
->const_index
[0] = const_idx0
;
63 intrin
->const_index
[1] = const_idx1
;
65 nir_builder_instr_insert(&b
->nb
, &intrin
->instr
);
67 dst
->def
= &intrin
->dest
.ssa
;
71 vtn_handle_subgroup(struct vtn_builder
*b
, SpvOp opcode
,
72 const uint32_t *w
, unsigned count
)
74 struct vtn_value
*val
= vtn_push_value(b
, w
[2], vtn_value_type_ssa
);
76 val
->ssa
= vtn_create_ssa_value(b
, val
->type
->type
);
79 case SpvOpGroupNonUniformElect
: {
80 vtn_fail_if(val
->type
->type
!= glsl_bool_type(),
81 "OpGroupNonUniformElect must return a Bool");
82 nir_intrinsic_instr
*elect
=
83 nir_intrinsic_instr_create(b
->nb
.shader
, nir_intrinsic_elect
);
84 nir_ssa_dest_init_for_type(&elect
->instr
, &elect
->dest
,
85 val
->type
->type
, NULL
);
86 nir_builder_instr_insert(&b
->nb
, &elect
->instr
);
87 val
->ssa
->def
= &elect
->dest
.ssa
;
91 case SpvOpGroupNonUniformBallot
: ++w
;
92 case SpvOpSubgroupBallotKHR
: {
93 vtn_fail_if(val
->type
->type
!= glsl_vector_type(GLSL_TYPE_UINT
, 4),
94 "OpGroupNonUniformBallot must return a uvec4");
95 nir_intrinsic_instr
*ballot
=
96 nir_intrinsic_instr_create(b
->nb
.shader
, nir_intrinsic_ballot
);
97 ballot
->src
[0] = nir_src_for_ssa(vtn_ssa_value(b
, w
[3])->def
);
98 nir_ssa_dest_init(&ballot
->instr
, &ballot
->dest
, 4, 32, NULL
);
99 ballot
->num_components
= 4;
100 nir_builder_instr_insert(&b
->nb
, &ballot
->instr
);
101 val
->ssa
->def
= &ballot
->dest
.ssa
;
105 case SpvOpGroupNonUniformInverseBallot
: {
106 /* This one is just a BallotBitfieldExtract with subgroup invocation.
107 * We could add a NIR intrinsic but it's easier to just lower it on the
110 nir_intrinsic_instr
*intrin
=
111 nir_intrinsic_instr_create(b
->nb
.shader
,
112 nir_intrinsic_ballot_bitfield_extract
);
114 intrin
->src
[0] = nir_src_for_ssa(vtn_ssa_value(b
, w
[4])->def
);
115 intrin
->src
[1] = nir_src_for_ssa(nir_load_subgroup_invocation(&b
->nb
));
117 nir_ssa_dest_init_for_type(&intrin
->instr
, &intrin
->dest
,
118 val
->type
->type
, NULL
);
119 nir_builder_instr_insert(&b
->nb
, &intrin
->instr
);
121 val
->ssa
->def
= &intrin
->dest
.ssa
;
125 case SpvOpGroupNonUniformBallotBitExtract
:
126 case SpvOpGroupNonUniformBallotBitCount
:
127 case SpvOpGroupNonUniformBallotFindLSB
:
128 case SpvOpGroupNonUniformBallotFindMSB
: {
129 nir_ssa_def
*src0
, *src1
= NULL
;
132 case SpvOpGroupNonUniformBallotBitExtract
:
133 op
= nir_intrinsic_ballot_bitfield_extract
;
134 src0
= vtn_ssa_value(b
, w
[4])->def
;
135 src1
= vtn_ssa_value(b
, w
[5])->def
;
137 case SpvOpGroupNonUniformBallotBitCount
:
138 switch ((SpvGroupOperation
)w
[4]) {
139 case SpvGroupOperationReduce
:
140 op
= nir_intrinsic_ballot_bit_count_reduce
;
142 case SpvGroupOperationInclusiveScan
:
143 op
= nir_intrinsic_ballot_bit_count_inclusive
;
145 case SpvGroupOperationExclusiveScan
:
146 op
= nir_intrinsic_ballot_bit_count_exclusive
;
149 unreachable("Invalid group operation");
151 src0
= vtn_ssa_value(b
, w
[5])->def
;
153 case SpvOpGroupNonUniformBallotFindLSB
:
154 op
= nir_intrinsic_ballot_find_lsb
;
155 src0
= vtn_ssa_value(b
, w
[4])->def
;
157 case SpvOpGroupNonUniformBallotFindMSB
:
158 op
= nir_intrinsic_ballot_find_msb
;
159 src0
= vtn_ssa_value(b
, w
[4])->def
;
162 unreachable("Unhandled opcode");
165 nir_intrinsic_instr
*intrin
=
166 nir_intrinsic_instr_create(b
->nb
.shader
, op
);
168 intrin
->src
[0] = nir_src_for_ssa(src0
);
170 intrin
->src
[1] = nir_src_for_ssa(src1
);
172 nir_ssa_dest_init_for_type(&intrin
->instr
, &intrin
->dest
,
173 val
->type
->type
, NULL
);
174 nir_builder_instr_insert(&b
->nb
, &intrin
->instr
);
176 val
->ssa
->def
= &intrin
->dest
.ssa
;
180 case SpvOpGroupNonUniformBroadcastFirst
: ++w
;
181 case SpvOpSubgroupFirstInvocationKHR
:
182 vtn_build_subgroup_instr(b
, nir_intrinsic_read_first_invocation
,
183 val
->ssa
, vtn_ssa_value(b
, w
[3]), NULL
, 0, 0);
186 case SpvOpGroupNonUniformBroadcast
: ++w
;
187 case SpvOpSubgroupReadInvocationKHR
:
188 vtn_build_subgroup_instr(b
, nir_intrinsic_read_invocation
,
189 val
->ssa
, vtn_ssa_value(b
, w
[3]),
190 vtn_ssa_value(b
, w
[4])->def
, 0, 0);
193 case SpvOpGroupNonUniformAll
:
194 case SpvOpGroupNonUniformAny
:
195 case SpvOpGroupNonUniformAllEqual
:
196 case SpvOpSubgroupAllKHR
:
197 case SpvOpSubgroupAnyKHR
:
198 case SpvOpSubgroupAllEqualKHR
: {
199 vtn_fail_if(val
->type
->type
!= glsl_bool_type(),
200 "OpGroupNonUniform(All|Any|AllEqual) must return a bool");
203 case SpvOpGroupNonUniformAll
:
204 case SpvOpSubgroupAllKHR
:
205 op
= nir_intrinsic_vote_all
;
207 case SpvOpGroupNonUniformAny
:
208 case SpvOpSubgroupAnyKHR
:
209 op
= nir_intrinsic_vote_any
;
211 case SpvOpGroupNonUniformAllEqual
:
212 case SpvOpSubgroupAllEqualKHR
: {
213 switch (glsl_get_base_type(val
->type
->type
)) {
214 case GLSL_TYPE_FLOAT
:
215 case GLSL_TYPE_DOUBLE
:
216 op
= nir_intrinsic_vote_feq
;
220 case GLSL_TYPE_UINT64
:
221 case GLSL_TYPE_INT64
:
223 op
= nir_intrinsic_vote_ieq
;
226 unreachable("Unhandled type");
231 unreachable("Unhandled opcode");
235 if (opcode
== SpvOpGroupNonUniformAll
||
236 opcode
== SpvOpGroupNonUniformAny
||
237 opcode
== SpvOpGroupNonUniformAllEqual
) {
238 src0
= vtn_ssa_value(b
, w
[4])->def
;
240 src0
= vtn_ssa_value(b
, w
[3])->def
;
242 nir_intrinsic_instr
*intrin
=
243 nir_intrinsic_instr_create(b
->nb
.shader
, op
);
244 intrin
->num_components
= src0
->num_components
;
245 intrin
->src
[0] = nir_src_for_ssa(src0
);
246 nir_ssa_dest_init_for_type(&intrin
->instr
, &intrin
->dest
,
247 val
->type
->type
, NULL
);
248 nir_builder_instr_insert(&b
->nb
, &intrin
->instr
);
250 val
->ssa
->def
= &intrin
->dest
.ssa
;
254 case SpvOpGroupNonUniformShuffle
:
255 case SpvOpGroupNonUniformShuffleXor
:
256 case SpvOpGroupNonUniformShuffleUp
:
257 case SpvOpGroupNonUniformShuffleDown
: {
260 case SpvOpGroupNonUniformShuffle
:
261 op
= nir_intrinsic_shuffle
;
263 case SpvOpGroupNonUniformShuffleXor
:
264 op
= nir_intrinsic_shuffle_xor
;
266 case SpvOpGroupNonUniformShuffleUp
:
267 op
= nir_intrinsic_shuffle_up
;
269 case SpvOpGroupNonUniformShuffleDown
:
270 op
= nir_intrinsic_shuffle_down
;
273 unreachable("Invalid opcode");
275 vtn_build_subgroup_instr(b
, op
, val
->ssa
, vtn_ssa_value(b
, w
[4]),
276 vtn_ssa_value(b
, w
[5])->def
, 0, 0);
280 case SpvOpGroupNonUniformQuadBroadcast
:
281 vtn_build_subgroup_instr(b
, nir_intrinsic_quad_broadcast
,
282 val
->ssa
, vtn_ssa_value(b
, w
[4]),
283 vtn_ssa_value(b
, w
[5])->def
, 0, 0);
286 case SpvOpGroupNonUniformQuadSwap
: {
287 unsigned direction
= vtn_constant_uint(b
, w
[5]);
291 op
= nir_intrinsic_quad_swap_horizontal
;
294 op
= nir_intrinsic_quad_swap_vertical
;
297 op
= nir_intrinsic_quad_swap_diagonal
;
300 vtn_fail("Invalid constant value in OpGroupNonUniformQuadSwap");
302 vtn_build_subgroup_instr(b
, op
, val
->ssa
, vtn_ssa_value(b
, w
[4]),
307 case SpvOpGroupNonUniformIAdd
:
308 case SpvOpGroupNonUniformFAdd
:
309 case SpvOpGroupNonUniformIMul
:
310 case SpvOpGroupNonUniformFMul
:
311 case SpvOpGroupNonUniformSMin
:
312 case SpvOpGroupNonUniformUMin
:
313 case SpvOpGroupNonUniformFMin
:
314 case SpvOpGroupNonUniformSMax
:
315 case SpvOpGroupNonUniformUMax
:
316 case SpvOpGroupNonUniformFMax
:
317 case SpvOpGroupNonUniformBitwiseAnd
:
318 case SpvOpGroupNonUniformBitwiseOr
:
319 case SpvOpGroupNonUniformBitwiseXor
:
320 case SpvOpGroupNonUniformLogicalAnd
:
321 case SpvOpGroupNonUniformLogicalOr
:
322 case SpvOpGroupNonUniformLogicalXor
: {
325 case SpvOpGroupNonUniformIAdd
:
326 reduction_op
= nir_op_iadd
;
328 case SpvOpGroupNonUniformFAdd
:
329 reduction_op
= nir_op_fadd
;
331 case SpvOpGroupNonUniformIMul
:
332 reduction_op
= nir_op_imul
;
334 case SpvOpGroupNonUniformFMul
:
335 reduction_op
= nir_op_fmul
;
337 case SpvOpGroupNonUniformSMin
:
338 reduction_op
= nir_op_imin
;
340 case SpvOpGroupNonUniformUMin
:
341 reduction_op
= nir_op_umin
;
343 case SpvOpGroupNonUniformFMin
:
344 reduction_op
= nir_op_fmin
;
346 case SpvOpGroupNonUniformSMax
:
347 reduction_op
= nir_op_imax
;
349 case SpvOpGroupNonUniformUMax
:
350 reduction_op
= nir_op_umax
;
352 case SpvOpGroupNonUniformFMax
:
353 reduction_op
= nir_op_fmax
;
355 case SpvOpGroupNonUniformBitwiseAnd
:
356 case SpvOpGroupNonUniformLogicalAnd
:
357 reduction_op
= nir_op_iand
;
359 case SpvOpGroupNonUniformBitwiseOr
:
360 case SpvOpGroupNonUniformLogicalOr
:
361 reduction_op
= nir_op_ior
;
363 case SpvOpGroupNonUniformBitwiseXor
:
364 case SpvOpGroupNonUniformLogicalXor
:
365 reduction_op
= nir_op_ixor
;
368 unreachable("Invalid reduction operation");
372 unsigned cluster_size
= 0;
373 switch ((SpvGroupOperation
)w
[4]) {
374 case SpvGroupOperationReduce
:
375 op
= nir_intrinsic_reduce
;
377 case SpvGroupOperationInclusiveScan
:
378 op
= nir_intrinsic_inclusive_scan
;
380 case SpvGroupOperationExclusiveScan
:
381 op
= nir_intrinsic_exclusive_scan
;
383 case SpvGroupOperationClusteredReduce
:
384 op
= nir_intrinsic_reduce
;
386 cluster_size
= vtn_constant_uint(b
, w
[6]);
389 unreachable("Invalid group operation");
392 vtn_build_subgroup_instr(b
, op
, val
->ssa
, vtn_ssa_value(b
, w
[5]),
393 NULL
, reduction_op
, cluster_size
);
398 unreachable("Invalid SPIR-V opcode");