2 Copyright (c) 2013, IIT Madras
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
7 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
15 `include "core_parameters.bsv"
16 import defined_types::*;
27 Instruction_type inst_type;
28 Bit#(`Reg_width) immediate_value;
30 Access_type mem_access;
33 Bit#(`PERFMONITORS) perf;
34 } Decoded_data deriving(Bits,Eq,FShow);
37 function Decoded_data fn_decode(Bit#(32) instruction, Trap_type exception, Bit#(`Reg_width) misa, Bit#(`PERFMONITORS) perfmonitors);
38 Bit#(5) rs1=instruction[19:15];
39 Bit#(5) rs2=instruction[24:20];
40 Bit#(5) rs3=instruction[31:27];
41 Bit#(5) rd=instruction[11:7];
42 Bit#(5) opcode = instruction[6:2];
43 Bit#(7) funct7 = instruction[31:25];
44 Bit#(3) funct3 = instruction[14:12];
47 Access_type mem_access=Load;
49 if(opcode[3]=='b1 && opcode[1]=='b1)
53 if(opcode[3]=='b1 && opcode[1]==0)
56 Operand_type rs1type=IntegerRF;
57 Operand_type rs2type=IntegerRF;
58 Operand_type rdtype=IntegerRF;
60 Bit#(`Reg_width) immediate_value=signExtend(instruction[31:20]);
61 if(opcode==`LUI_op|| opcode==`AUIPC_op)
62 immediate_value=signExtend({instruction[31:12],12'd0});
63 else if(opcode==`JAL_op)
64 immediate_value=signExtend({instruction[31],instruction[19:12],instruction[20],instruction[30:21],1'b0});
65 else if(opcode==`JALR_op)
66 immediate_value=signExtend({instruction[31:21],1'b0});
67 else if (opcode==`BRANCH_op) // Branch instructions
68 immediate_value=signExtend({instruction[31],instruction[7],instruction[30:25],instruction[11:8],1'b0});
69 else if (opcode==`STORE_op `ifdef spfpu || opcode==`FSTORE_op `endif ) // Store operations
70 immediate_value=signExtend({instruction[31:25],instruction[11:7]});
71 else if(opcode==`CSR_op)
72 immediate_value[16:12]=instruction[19:15];
73 else if(opcode==`ATOMIC_op)
76 if(opcode==`LUI_op || opcode==`JAL_op || opcode==`AUIPC_op || (opcode==`CSR_op && funct3[2]==1))
78 if(opcode==`CSR_op || opcode[4:2]=='b000 // CSR or ( (F)Load or FENCE )
79 || opcode==`LUI_op || opcode==`JAL_op || opcode[4:2]=='b001 // LUI or JAL or (AUIPC or IMMediate Arith)
80 || opcode==`JALR_op || (opcode[4:2]=='b101 && funct7[5]==1)) // JALR or Floating conversion operations.
82 if(opcode==`BRANCH_op || opcode[4:1]=='b0100)
85 if(opcode==`JAL_op || opcode==`AUIPC_op)
88 else if(opcode[4:2]=='b100 || (opcode[4:2]=='b101 && // (F(N)MADD or F(N)SUB)
89 (funct7[6:3]!='b1101 && funct7[6:3]!='b1111))) // some of the conversion operations
93 if(opcode==`JAL_op || opcode==`JALR_op || opcode==`LUI_op|| opcode[4:2]=='b001 // JAL or JALR or (AUIPC or IMM Arith)
94 || opcode[4:1]==0) // (F)Load or
97 else if((opcode[4:2]=='b101 && funct7[5]!='b1) || opcode==`FSTORE_op || opcode[4:2]=='b100) // All convert + FSQRToperations do not need rs2
100 if(opcode==`FLOAD_op || (opcode[4:2]=='b101 &&
101 funct7[6:3]!='b1010 && funct7[6:3]!='b1100 && funct7[6:3]!='b1110 ) || opcode[4:2]=='b100)
105 if(opcode==`IMM_ARITHW_op || opcode==`MULDIVW_op || opcode==`ARITHW_op || (opcode[4:3]=='b10 && funct7[0]==0)
106 || (opcode[4:1]=='b0101 && funct3[0]==0))
109 Instruction_type inst_type=NOP;
111 if(opcode[4:3]=='b10)begin
112 inst_type=funct7[0]==0?FLOATING:DFLOATING;
115 if(opcode[4:3]=='b11)begin
118 'b001:inst_type=JALR;
119 'b000:inst_type=BRANCH;
120 'b100:inst_type=SYSTEM_INSTR;
123 else if(opcode[4:3]=='b01)begin
125 'b000,'b011,'b001:inst_type=MEMORY; // STORE or FSTORE or ATOMIC
126 'b101:inst_type=ALU; // LUI
127 'b100,'b110:inst_type=(funct7[0]==1)?(funct3[2]==0)?MUL:DIV:ALU;
130 else if(opcode[4:3]=='b00)begin
132 'b000,'b001:inst_type=MEMORY; //
133 'b101,'b100,'b110:inst_type=ALU; //AUIPC IMM WORD
134 'b011:inst_type=(funct3[0]==0)?FENCE:FENCEI;
138 Trap_type ex=tagged None;
139 if(exception matches tagged None)begin
140 if( `ifdef spfpu (inst_type==FLOATING && misa[5]==0) `ifdef dpfpu || (inst_type==DFLOATING && misa[3]==0) `endif || `endif
141 (inst_type==MUL && misa[12]==0) || (inst_type==DIV && misa[12]==0)
142 `ifdef atomic || (inst_type==MEMORY && mem_access==Atomic && misa[0]==0) `endif )
143 ex=tagged Exception Illegal_inst;
145 if(inst_type==JAL && immediate_value==0)
146 ex=tagged Exception Endsimulation;
148 if(instruction[1:0]!='b11)
149 ex=tagged Exception Illegal_inst;
151 ex=tagged Exception Illegal_inst;
157 if(opcode==`ATOMIC_op)begin
158 if((instruction[27] | instruction[28]) == 1)
159 fn={instruction[29:27],1'b1};
161 fn={instruction[31:29],instruction[27]};
163 else if(opcode==`BRANCH_op)begin
165 fn={2'b0,1,funct3[0]};
169 else if(opcode==`JAL_op || opcode==`JALR_op || opcode==`LOAD_op `ifdef spfpu || opcode==`FLOAD_op `endif
170 || opcode==`STORE_op `ifdef spfpu || opcode==`FSTORE_op `endif || opcode==`AUIPC_op || opcode==`LUI_op)
172 else if(opcode==`IMM_ARITHW_op || opcode==`IMM_ARITH_op)begin
176 'b101: if(funct7[5]==1) 'b1011; else 'b0101;
177 default:{1'b0,funct3};
180 else if(opcode==`ARITHW_op || opcode==`ARITH_op)begin
182 'b000:if(funct7[5]==1) 'b1010; else 'b0000;
185 'b101:if (funct7[5]==1) 'b1011;else 'b0101;
186 default:{1'b0,funct3};
189 else if(opcode[4:3]=='b10)
191 if(inst_type==BRANCH)
192 perfmonitors[`COND_BRANCH]=1;
194 if(inst_type==FLOATING)
195 perfmonitors[`SPFPU_INST]=1;
198 if(inst_type==DFLOATING)
199 perfmonitors[`DPFPU_INST]=1;
201 if(inst_type==JAL || inst_type==JALR)
202 perfmonitors[`UNCOND_JUMPS]=1;
203 if(inst_type==MEMORY)
204 perfmonitors[`MEMORY_INSTRUCTIONS]=1;
205 if(inst_type==MUL || inst_type==DIV)
206 perfmonitors[`MULDIV_INSTRUCTIONS]=1;
208 return (Decoded_data{fn:fn,rs1:rs1,rs2:rs2,rs3:rs3,rd:rd,
209 rs1type:rs1type,rs2type:rs2type,rdtype:rdtype,
210 inst_type:inst_type,immediate_value:immediate_value,
211 word32:word32,mem_access:mem_access,exception:ex,
212 funct3:funct3,perf:perfmonitors});