src/core/defined_parameters.bsv

   1 `define RegFileSize 32 // describes the size of ht register file in the processor.
   2 `ifdef spfpu
   3         `define FLEN 32
   4 `endif
   5 `ifdef dpfpu
   6         `define FLEN 64
   7 `endif
   8 //`define fpu_hierarchical //Define this if you want hierarchical modules in verilog
   9
  10 //`define MMU
  11 `define PRFDEPTH 6
  12 `define USERSPACE 0
  13 `ifdef RV64
  14         `define Burst_length_bits 8
  15         `define byte_offset 2
  16         `define Reg_width 64 // the register data width of the processor.
  17         `define ADDR 64 // the address width
  18         `define DCACHE_ADDR 64
  19         `define DCACHE_BLOCK_SIZE 4
  20         `define DCACHE_WORD_SIZE 8
  21 /////////////////////////////MMU parameters///////////////////////////////////
  22 `define VADDR   39
  23 `define PADDR   32
  24 `define OFFSET  12
  25 `define ASID            8
  26 ///////////////////////////////////////////////////////////////////////////////
  27 ///////////////////////////////////////////////////////////////////////////////
  28         // TLM2 Request Response definitions for Processor to Bus connection
  29         `define TLM_PRM_CPU_REQ 4, 64, 64, 5, Bit #(0)
  30         `define TLM_PRM_CPU_RSP 4, 64, 64, 5, Bit #(0)
  31
  32         // TLM2 Request Response definitions for Memory to Bus connection
  33         `define TLM_PRM_MEM_REQ 4, 64, 64, 5, Bit #(0)
  34         `define TLM_PRM_MEM_RSP 4, 64, 64, 5, Bit #(0)
  35
  36         // Axi Request Response definitions for Processor as a Master
  37         `define AXI_PRM_CPU     4, 64, 64, 5, Bit #(0)  // Fabric Interface
  38         `define AXI_XTR_CPU TLMRequest #(`TLM_PRM_CPU_REQ), TLMResponse #(`TLM_PRM_CPU_RSP), `AXI_PRM_CPU // Transactor Interface
  39
  40         // Axi Request Response definitions for Memory as a Slave
  41         `define AXI_PRM_MEM     4, 64, 64, 5, Bit #(0)  // Fabric Interface
  42         `define AXI_XTR_MEM TLMRequest #(`TLM_PRM_MEM_REQ), TLMResponse #(`TLM_PRM_MEM_RSP), `AXI_PRM_MEM // Transactor Interface
  43 ///////////////////////////////////////////////////////////////////////////////
  44 `else
  45         `define byte_offset 1
  46         `define Reg_width 32 // the register data width of the processor.
  47         `define Addr_width 32 // the address width
  48         `define DCACHE_ADDR 32
  49         `define DCACHE_BLOCK_SIZE 8
  50         `define DCACHE_WORD_SIZE 4
  51 ///////////////////////////////////////////////////////////////////////////////
  52         // TLM2 Request Response definitions for Processor to Bus connection
  53         `define TLM_PRM_CPU_REQ 4, 32, 32, 5, Bit #(0)
  54         `define TLM_PRM_CPU_RSP 4, 32, 32, 5, Bit #(0)
  55
  56         // TLM2 Request Response definitions for Memory to Bus connection
  57         `define TLM_PRM_MEM_REQ 4, 32, 32, 5, Bit #(0)
  58         `define TLM_PRM_MEM_RSP 4, 32, 32, 5, Bit #(0)
  59
  60         // Axi Request Response definitions for Processor as a Master
  61         `define AXI_PRM_CPU     4, 32, 32, 5, Bit #(0)  // Fabric Interface
  62         `define AXI_XTR_CPU TLMRequest #(`TLM_PRM_CPU_REQ), TLMResponse #(`TLM_PRM_CPU_RSP), `AXI_PRM_CPU // Transactor Interface
  63
  64         // Axi Request Response definitions for Memory as a Slave
  65         `define AXI_PRM_MEM     4, 32, 32, 5, Bit #(0)  // Fabric Interface
  66         `define AXI_XTR_MEM TLMRequest #(`TLM_PRM_MEM_REQ), TLMResponse #(`TLM_PRM_MEM_RSP), `AXI_PRM_MEM // Transactor Interface
  67 ///////////////////////////////////////////////////////////////////////////////
  68 `endif
  69
  70 `define Loop 1
  71 `define BAUD_RATE 130
  72 `ifdef verilog
  73         `define Addr_space 22   //since we are leaving off the lower 2 bits of address(byte addressable memory), we have to
  74 `else
  75         `define Addr_space 30
  76 `endif
  77 `ifdef simulate
  78   `define BAUD_RATE 5 //130 //
  79 `endif
  80 `define INTERRUPT_PINS 64
  81
  82 // Branch_predictor_paramters
  83 /////////////////////////// CACHE RELATED PARAMETERS ////////////////////////////////
  84 `define DCACHE_WAYS 4
  85 `define DCACHE_SETS 512
  86
  87 `define ICACHE_WAYS 4                   // way_bits =2
  88 `define ICACHE_BLOCK_SIZE 8     // word_bits = 3
  89 `define ICACHE_SETS 512                 // set_bits     =7
  90 `define ICACHE_WORD_SIZE 4              // byte_bits=2
  91 `define ICACHE_TAG_BITS 20              // tag_bits = 52
  92 `define DCACHE_TAG_BITS 20              // tag_bits = 52
  93 `define BTB_DEPTH                       256
  94 `define RAS_DEPTH                       8
  95 /////////////////////////////////////////////////////////////////////////////////////
  96 `ifdef RV64
  97         `define MISA_BITS   'h141129 //'h082C849//// 'h40101121 // A + F + I + M + U
  98         `define MXL_BITS                'h2
  99 `else
 100         `define MISA_BITS   'h082C849 // 'h40101121 // A + F + I + M + U
 101         `define MXL_BITS                'h1
 102 `endif
 103 `define MTVEC_DEFAULT       'h00000000
 104 `define STVEC_DEFAULT       'h00000000
 105 `define UTVEC_DEFAULT       'h00000000
 106 /////////////////////////// Register Mapping for Machine Mode Regs /////////////////
 107 `define MSTATUS                 'h00 //'h300 // Machine Status register
 108 `define MISA                            'h01 //'h301 // ISA and extensions
 109 `define MEDELEG                 'h02 //'h302 // Machine exception delegation
 110 `define MIDELEG                 'h03 //'h303 // Machine interrupt delegation
 111 `define MIE                                     'h04 //'h304 // Machine interrupt enable
 112 `define MTVEC                           'h05 //'h305 // Machine trap-handler base address
 113 `define MCOUNTEREN              'h06 //'h306 // Machine counter setup register
 114 `define MHPMEVENTSTART  'h23 //'h323 // statr of event selectors
 115 `define MHPMEVENTEND            'h26 //'h326 // end of event selectors
 116 `define MSCRATCH                        'h40 //'h340 // Scratch rgister for machine trap hanglers
 117 `define MEPC                            'h41 //'h341 // Machine exception program counter
 118 `define MCAUSE                          'h42 //'h342 // Machine trap cause
 119 `define MTVAL                           'h43 //'h343 // Machine bad address
 120 `define MIP                                     'h44 //'h344 // Machine interrupt pending
 121 `define MPOWERCONTROL   'h45 //'h345 // 2 bits to control the power switches.
 122 `define PMPCFG0                 'hA0 //'h3A0 //
 123 `ifndef RV64
 124         `define PMPCFG1                 'hA1 //'h3A1 // Physical Memory Protection Configuration Registers
 125 `endif
 126 `define PMPCFG2                 'hA2 //'h3A2 // Physical Memory Protection Configuration Registers
 127 `ifndef RV64
 128         `define PMPCFG3                 'hA3 //'h3A3 // Physical Memory Protection Configuration Registers
 129 `endif
 130 `define PMPADDRSTART 'hB0 //PMP Address array start
 131 `define PMPADDREND   'hB7 //PMP Address array end
 132 `define MCYCLE                          'h00 //'hB00 // Machine cycle counter
 133 `define MTIME                           'h01 //'hB01    // mtime register (Non-standard r/w)
 134 `define MINSTRET                        'h02 //'hB02 // Machine instructions retired.
 135 `define MHPMCOUNTSTART  'h03 //'hB03 // start address for performance counters
 136 `define MHPMCOUNTEND    'h05 //'hB05 // end address for performance counters
 137 `define MTIMECMP                        'h20 //'hB20 //  time compare register (Non-standard r/w)
 138 `define MCYCLEH                 'h80 //'hB80 // Upper 32 bits of mcycle
 139 `define MTIMEH                          'h81 //'hB81    // mtime hi-register (Non-standard r/w)
 140 `define MINSTRETH                       'h82 //'hB82 // Upper 32 bits of minstret.
 141 `define MHPMCOUNTHSTART 'h83 //'hB83 // start address for performance counters higher bits
 142 `define MHPMCOUNTHEND   'h85 //'hB86 // end address for performance counters higher bits
 143 `define MTIMECMPH                       'hA0 //'hBA0 //  time compare hi-register (Non-standard r/w)
 144 `define MHPMTHRESSTART  'hA3 //'hBA3 // start of counter-thresholds
 145 `define MHPMTHRESEND            'hA5 //'hBA6 // end of counter-thresholds
 146 `define MVENDORID                       'h11 //'hF11 // Vendor ID
 147 `define MARCHID                 'h12 //'hF12 // Architecture ID
 148 `define MIMPID                          'h13 //'hF13 // Implementation ID
 149 `define MHARTID                 'h14 //'hF14 // Hardware Thread ID
 150 `define MBOOTSEQ                        'h15 //'hF15 // Hardware Thread ID
 151
 152 `define MHPMTHRESHSTART 'hE0 //'h7E0 // start of counter-thresholds
 153 `define MHPMTHRESHEND   'hE2 //'h7FC // end of counter-thresholds
 154 /////////////////////////// Register Mapping for Supervisor Mode Regs /////////////////
 155 `define SSTATUS     'h00 //'h100 // Supervisor Status register
 156 `define SEDELEG     'h02 //'h102 // Supervisor exception delegation
 157 `define SIDELEG     'h03 //'h103 // Supervisor interrupt delegation
 158 `define SIE         'h04 //'h104 // Supervisor interrupt enable
 159 `define STVEC       'h05 //'h105 // Supervisor trap-handler base address
 160 `define SCOUNTEREN  'h06 //'h106 // Supervisor counter setup register
 161 `define SSCRATCH    'h40 //'h140 // Scratch register for supervisor trap hanglers
 162 `define SEPC        'h41 //'h141 // Supervisor exception program counter
 163 `define SCAUSE      'h42 //'h142 // Supervisor trap cause
 164 `define STVAL             'h43 //'h143 // Supervisor bad address or illegal instruction
 165 `define SIP         'h44 //'h144 // Supervisor interrupt pending
 166 `define SATP        'h80 //'h180 // Supervisor interrupt pending
 167
 168 /////////////////////////// Register Mapping for User Mode Regs /////////////////
 169 `define USTATUS         'h00 //'h000 // User status register
 170 `define FFLAGS                  'h01 //'h001 // FP Accrued exceptions
 171 `define FRM                             'h02 //'h002 // FP Dynamic rounding mode
 172 `define FCSR                    'h03 //'h003 // FP Control and status register
 173 `define UIE                             'h04 //'h004 // User interrupt enable register
 174 `define UTVEC                   'h05 //'h005 // User trap handler base address
 175 `define USCRATCH                'h40 //'h040 // Scratch register for user trap handlers
 176 `define UEPC                    'h41 //'h041 // User exception program counter
 177 `define UCAUSE                  'h42 //'h042 // User trap cause
 178 `define UTVAL                   'h43 //'h043 // User bad address or illegal instruction
 179 `define UIP                             'h44 //'h044 // User interrupt pending
 180 `define UMEMSE                  'h45 //'h045 // Machine Memory Structures enable
 181 `define UCYCLE                  'h00 //'hC00 // cycle counter for RDCYCLE instruction.
 182 `define UTIME                   'h01 //'hC01 // Tiemr for RDTIME instruction
 183 `define UINSTRET                'h02 //'hC02 // Instruction retired counter for RDINSTRET
 184 `define UCYCLEH         'h80 //'hC80 // Upper 32bits of UCYCLE
 185 `define UTIMEH                  'h81 //'hC81 // Upper 32bits of UTIME
 186 `define UINSTRETH               'h82 //'hC82 // Upper 32bits of UINSTRET
 187 `define HPMCOUNTSTART   'h03    //'hC03 // start address for performance counters
 188 `define HPMCOUNTEND             'h05  //'hC06 // start address for performance counters
 189 `define HPMCOUNTHSTART  'h83    //'hC83 // start address for performance counters higher bits
 190 `define HPMCOUNTHEND            'h85  //'hC86 // end address for performance counters higher bits
 191
 192 ////////////////////////////////////////////////////////////////////////////////////
 193 /////////// Debug registers //////////////////////////
 194 `define DCSR            'hb0 //'h7b0
 195 `define DPC                     'hb1 //'h7b1
 196 `define DSCRATCH0       'hb2 //'h7b2
 197 `define DSCRATCH1       'hb3 //'h7b3
 198 `define DENTRY          'hb4 //'h7b4 // holds the address of the debug entry for self loop
 199 `define TSELECT 'ha0 // 'h7a0 // holds the tselect information
 200 `define TDATA1          'ha1 // 'h7a1 // holds the first trigger data
 201 `define TDATA2          'ha2 // 'h7a2 // holds the first trigger data
 202 ////////////////////////////////////////////////////////////////////////////////////
 203 //////////////////////////////////// funct3 defintions for ISA ////////////////////
 204 `define JALR_f3 'b000
 205 `define BEQ_f3  'b000
 206 `define BNE_f3  'b001
 207 `define BLT_f3  'b100
 208 `define BGE_f3  'b101
 209 `define BLTU_f3 'b110
 210 `define BGEU_f3 'b111
 211 `define LB_f3           'b000
 212 `define Lh_f3           'b001
 213 `define LW_f3           'b010
 214 `define LBU_f3  'b100
 215 `define LHU_f3  'b101
 216 `define LWU_f3  'b110
 217 `define SB_f3           'b000
 218 `define SH_f3           'b001
 219 `define SW_f3           'b010
 220 `define ADD_SUB_f3      'b000
 221 `define SLT_SLTI_f3     'b010
 222 `define SLTU_SLTIU_f3   'b011
 223 `define XOR_XORI_f3     'b100
 224 `define OR_ORI_f3       'b110
 225 `define AND_ANDI_f3     'b111
 226 `define SLL_SLLI_f3     'b001
 227 `define SR_SRI_f3       'b101
 228 `define ECALL_f3        'b000
 229 `define EBREAK_f3       'b000
 230 `define CSRRW_f3        'b001
 231 `define CSRRS_f3        'b010
 232 `define CSRRC_f3        'b011
 233 `define CSRRWI_f3       'b101
 234 `define CSRRSI_f3       'b110
 235 `define CSRRCI_f3       'b111
 236 `define MUL_f3          'b000
 237 `define MULH_f3         'b001
 238 `define MULHSU_f3       'b010
 239 `define MULHU_f3        'b011
 240 `define DIV_f3          'b100
 241 `define DIVU_f3         'b101
 242 `define REM_f3          'b110
 243 `define REMU_f3         'b111
 244 `define ATOMIC_f3       'b010
 245 `define FENCE_f3        'b000
 246 `define FENCEI_f3       'b001
 247 /////////////////////////////////////////////////////////////////////////
 248 ////////////////////// opcode definitions of ISA ////////////////////////
 249 `define LUI_op                          'b01101
 250 `define AUIPC_op                        'b00101
 251 `define JAL_op                          'b11011
 252 `define JALR_op                         'b11001
 253 `define BRANCH_op                       'b11000
 254 `define LOAD_op                         'b00000
 255 `define FLOAD_op                        'b00001
 256 `define STORE_op                        'b01000
 257 `define FSTORE_op                       'b01001
 258 `define IMM_ARITH_op    'b00100
 259 `define ARITH_op                        'b01100
 260 `ifdef RV64
 261         `define IMM_ARITHW_op   'b00110
 262         `define ARITHW_op                       'b01110
 263         `define MULDIVW_op              'b01110
 264 `endif
 265 `define CSR_op                          'b11100
 266 `define MULDIV_op                       'b01100
 267 `define ATOMIC_op                       'b01011
 268 `define FMADD_op                'b10000
 269 `define FMSUB_op                        'b10001
 270 `define FNMSUB_op                       'b10010
 271 `define FNMADD_op                       'b10011
 272 `define FLOAT_op                'b10100
 273 `define FENCE_op                        'b00011
 274 //////////////////////////////////////////////////////////////////////////
 275 /////////////// funct7 deifnition of ISA /////////////////////////////////
 276 `define SLLI_f7         'b0000000
 277 `define LOGIC_SHIFT_f7          'b0000000
 278 `define ARITH_SHIFT_f7          'b0100000
 279 `define ARITH_f7                'b0000000
 280 `define SUB_f7                  'b0100000
 281 `define MULDIV_f7               'b0000001
 282 `define SFENCE_VMA      'b0001001
 283 `define LR_f5                           'b00010
 284 `define SC_f5                           'b00011
 285 `define AMOSWAP_f5      'b00001
 286 `define AMOADD_f5               'b00000
 287 `define AMOXOR_f5               'b00100
 288 `define AMOAND_f5               'b01100
 289 `define AMOOR_f5                'b01000
 290 `define AMOMIN_f5               'b10000
 291 `define AMOMAX_f5               'b10100
 292 `define AMOMINU_f5      'b11000
 293 `define AMOMAXU_f5      'b11100
 294 `define AMOMIN_f5       'b10000
 295 `define AMOMAX_f5       'b10100
 296
 297
 298 `define FADD_f5         'b00000
 299 `define FSUB_f5         'b00001
 300 `define FMUL_f5         'b00010
 301 `define FDIV_f5         'b00011
 302 `define FSQRT_f5        'b01011
 303 `define FP_OPCODE       'b0100
 304 `define FCMP_f5         'b10100
 305 `define FMMAX_f5        'b00101
 306 `define FCVT_F_I_f5     'b11010
 307 `define FCVT_I_F_f5     'b11000
 308 `define FSGNJN_f5       'b00100
 309 `define FCLASS_f5       'b11100
 310 `define FCVT_S_D_f5     'b01000
 311 `define FMV_X_S_f7      'b1110000
 312 `define FMV_S_X_f7      'b1111000
 313 `define FMV_X_D_f7      'b1110001
 314 `define FMV_D_X_f7      'b1111001
 315
 316
 317
 318
 319 ///////////////////////////////////////////////////////////////////////////
 320 ///////////////// Event Values of Performance Counters ////////////////////
 321 `define PERFMONITORS                                                    64
 322 `define CYCLECOUNTERS                                           13
 323 `define ICACHE_MISS                                                     0
 324 `define ICACHE_CACHEABLE                                        `ICACHE_MISS+1
 325 `define ICACHE_LINEREPLACE                              `ICACHE_CACHEABLE+1
 326 `define ICACHE_TLBMISS                                          `ICACHE_LINEREPLACE+1
 327 `define ICACHE_MISALIGNED                                       `ICACHE_TLBMISS+1
 328 `define ICACHE_PREFETCHMISS                             `ICACHE_MISALIGNED+1
 329 `define COND_BRANCH                                                     `ICACHE_PREFETCHMISS+1
 330 `define COND_BRANCH_TAKEN                                       `COND_BRANCH+1
 331 `define COND_BRANCH_MISPREDICTED                        `COND_BRANCH_TAKEN+1
 332 `define TAKEN_BRANCH_MISPREDICTED               `COND_BRANCH_MISPREDICTED+1
 333 `define UNCOND_JUMPS                                                    `TAKEN_BRANCH_MISPREDICTED+1
 334 `define SPFPU_INST                                                      `UNCOND_JUMPS+1
 335 `define DPFPU_INST                                                      `SPFPU_INST+1
 336 `define DCACHE_TLBMISS                                          `DPFPU_INST+1
 337 `define TOTAL_LOADS                                                     `DCACHE_TLBMISS+1
 338 `define TOTAL_STORES                                                    `TOTAL_LOADS+1
 339 `define TOTAL_ATOMIC                                                    `TOTAL_STORES+1
 340 `define DCACHE_LOAD_MISS                                        `TOTAL_ATOMIC+1
 341 `define DCACHE_STORE_MISS                                       `DCACHE_LOAD_MISS+1
 342 `define DCACHE_ATOMIC_MISS                                      `DCACHE_STORE_MISS+1
 343 `define DCACHE_CACHEABLE_LOAD                           `DCACHE_ATOMIC_MISS+1
 344 `define DCACHE_CACHEABLE_STORE                  `DCACHE_CACHEABLE_LOAD+1
 345 `define DCACHE_CACHEABLE_ATOMIC                 `DCACHE_CACHEABLE_STORE+1
 346 `define DCACHE_WRITEBACKS                                       `DCACHE_CACHEABLE_ATOMIC+1
 347 `define DCACHE_LINEREPLACE                                      `DCACHE_WRITEBACKS+1
 348 `define DCACHE_MISALIGNED                                       `DCACHE_LINEREPLACE+1
 349 `define EXCEPTIONS_TAKEN                                        `DCACHE_MISALIGNED+1
 350 `define INTERRUPTS_TAKEN                                        `EXCEPTIONS_TAKEN+1
 351 `define MULDIV_INSTRUCTIONS                             `INTERRUPTS_TAKEN+1
 352 `define MEMORY_INSTRUCTIONS                             `MULDIV_INSTRUCTIONS+1
 353 `define EXEC_FLUSHES                                                    `MEMORY_INSTRUCTIONS+1
 354 `define WB_FLUSHES                                                      `EXEC_FLUSHES+1
 355
 356 `define USERMODE_CYCLES                                         30
 357 `define SUPERVISORMODE_CYCLES                           31
 358 `define MACHINEMODE_CYLES                                       32
 359 `define MISPREDICTION_STALLS                            33
 360 `define INTERRUPT_STALLS                                        34
 361 `define DFENCE_CYCLES                                           35
 362 `define IFENCE_CYCLES                                           36
 363 `define DCACHE_MISS_CYCLES                                      37
 364 `define ICACHE_MISS_CYCLES                                      38
 365 `define FPBUSY_CYCLES                                           39
 366 `define DIVISIONBUSY_CYCLES                             40
 367 `define TOTAL_STALL_CYCLES                                      41
 368 `define PAGEWALK_CYCLES                                         42
 369 `define COREBUS_CYCLES                                          43
 370
 371 ///////////////////////////////////////////////////////////////////////////////////
 372 /*====== Define the slave number of each peripheral=== */
 373 //`ifdef simulate
 374 //      `define Sdram_slave_num                                 0
 375 //      `define Sdram_cfg_slave_num             `Sdram_slave_num
 376 //      `define BootRom_slave_num                       `Sdram_cfg_slave_num+1
 377 //      `define Uart0_slave_num                         `BootRom_slave_num+1
 378 //      `define Uart1_slave_num                         `Uart0_slave_num+1
 379 //      `define Debug_slave_num                         `Uart1_slave_num+1
 380 //      `define Plic_slave_num                          `Debug_slave_num+1
 381 //      `define Qspi0_slave_num          `Plic_slave_num
 382 //      `define Qspi1_slave_num          `Qspi0_slave_num
 383 //      `define Num_Slaves                                      `Qspi1_slave_num
 384 //`else
 385 //      `define Uart0_slave_num           0
 386 //      `define Uart1_slave_num           1
 387 //      `define Qspi0_slave_num           2
 388 //      `define Qspi1_slave_num           3
 389 //      `define I2c0_slave_num                           4
 390 //      `define I2c1_slave_num            5
 391 //      `define Sdram_slave_num           6
 392 //      `define Sdram_cfg_slave_num              7
 393 //      `define Dma_slave_num                            8
 394 //      `define Hyperflash_mem_slave_num  9
 395 //      `define Hyperflash_reg_slave_num  10
 396 //      `define Debug_slave_num                         11
 397 //      `define AxiExp1_slave_num                       12
 398 //      `define GPIO_slave_num                          13
 399 //      `define BootRom_slave_num                       14
 400 //      `define PLIC_slave_num                          15
 401 //      `define TCM_slave_num                           16
 402 //`endif
 403 /*=================================================== */
 404
 405 /*===== Define the base address of each peripheral === */
 406         `define DebugBase               'h00000000
 407         `define DebugEnd                'h000000FF
 408         `define BootRomBase  'h00001000
 409         `define BootRomEnd   'h00010FFF
 410         `define GPIOBase                'h00011100
 411         `define GPIOEnd         'h000111FF // 2 32-bit registers
 412         `define UART0Base               'h00011200
 413         `define UART0End                'h000112FF // 8 32-bit registers
 414         `define UART1Base               'h00011300
 415         `define UART1End                'h000113FF // 2 32-bit registers
 416         `define I2C0Base                'h00011400
 417         `define I2C0End         'h000114FF // 8 32-bit registers
 418         `define I2C1Base                'h00011500
 419         `define I2C1End         'h000115FF // 8 32-bit registers
 420         `define DMABase         'h00011600
 421         `define DMAEnd                  'h000116FF // TODO
 422         `define SDRAMCfgBase    'h00011700
 423         `define SDRAMCfgEnd  'h000117FF // 12 32-bit registers
 424         `define QSPI0CfgBase    'h00011800
 425         `define QSPI0CfgEnd  'h000118FF // 13 32-bit registers
 426         `define QSPI1CfgBase    'h00011900
 427         `define QSPI1CfgEnd  'h000119FF // 13 32-bit registers
 428   `define PWMBase      'h00011A00
 429   `define PWMEnd       'h00011A0C // 4 32-bit registers
 430         `define TCMBase         'h00020000 //
 431         `define TCMEnd                  'h00040000 // 128KB
 432   `define VMEBase       'h40000000
 433         `define  VMEEnd  'h4FFFFFFF // 1GB
 434     `ifdef FlexBus_verify
 435         `define FlexBusBase 'h80000000
 436         `define FlexBusEnd 'h8FFFFFFF
 437     `else
 438         `define FlexBusBase 'h50000000
 439         `define FlexBusEnd 'h5FFFFFFF
 440     `endif
 441         `define ClintBase               'h02000000
 442         `define ClintEnd                'h020BFFFF
 443     `ifdef FlexBus_verify
 444             `define SDRAMMemBase        'h50000000
 445             `define SDRAMMemEnd  'h5FFFFFFF // 1GB
 446     `else
 447             `define SDRAMMemBase        'h80000000
 448             `define SDRAMMemEnd  'h8FFFFFFF // 1GB
 449     `endif
 450         `define QSPI0MemBase    'h90000000
 451         `define QSPI0MemEnd  'h9FFFFFFF // 256 MB
 452         `define QSPI1MemBase    'hA0000000
 453         `define QSPI1MemEnd  'hAFFFFFFF // 256 MB
 454         `define PLICBase                'h0c000000
 455         `define PLICEnd         'h10000000
 456         `define AxiExp1Base     'hC0000000
 457         `define AxiExp1End      'hFFFFFFFF
 458 /*=================================================== */
 459 /*== Define the range of bytes per peripheral====
 460 `ifdef simulate
 461         `define MemCRange               'h7FFFFFFF
 462         `define ConfigMRange    'h3000
 463         `define DebugRange              'h44
 464 `else
 465     `define BootRomRange       'hFFF         //4KB for Now
 466          `define GPIORange                       'h8                            //2 registers for GPIO
 467     `define UART0Range         'h38          //8 Registers
 468     `define UART1Range         'h38          //2 registers
 469     `define I2C0Range          'h38          //6 Registers. Adding +2 to just have a backup, if at all it might be required
 470     `define I2C1Range          'h38          //8 registers
 471     `define DMARange           'hFF
 472     `define SDRAMCfgRange      'h58          //12 registers
 473     `define QSPI0CfgRange      'h60          //13 registers
 474     `define QSPI1CfgRange      'h60          //13 registers
 475     `define HyperCfgRange      'h70          //15 registers
 476     `define SDRAMMemRange      'hFFFFFFF     //512 MB
 477     `define HyperMemRange      'hFFFFFFF     //512 MB
 478          `define QSPI0MemRange      'h7FFFFFFF    //2 GB
 479     `define QSPI1MemRange           'h7FFFFFFF    //2 GB
 480     `define AxiExpRange                  'hFFFFFFFF    //512 MB for now!
 481     `define DebugRange         'h44          //16 Registers -- 32 bit
 482 `endif
 483         /*=================================================== */
 484 `define IONum 32
 485