2 Copyright (c) 2013, IIT Madras
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
7 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
15 /*==== Project Imports === */
16 import defined_types::*;
17 `include "core_parameters.bsv"
18 /*======================== */
19 /*===== Package Imports ==== */
22 /*===========================*/
24 interface Ifc_registerfile;
25 method ActionValue#(Output_for_operand_fetch) _inputs_from_decode_stage(Bit#(5) rs1_addr, Operand_type rs1_type, Bit#(5) rs2_addr, Operand_type rs2_type, Bit#(`VADDR) pc, Bit#(`Reg_width) imm `ifdef spfpu , Bool rs3_valid,Bit#(5) rs3_addr `endif );
27 method Bit#(`Reg_width) read_debug_igpr (Bit#(5) r); // Read a General-Purpose Register
28 method Action write_debug_igpr (Bit#(5) r, Bit#(`Reg_width) d); // Write a General-Purpose Register
29 method Bit#(`Reg_width) read_debug_fgpr (Bit#(5) r); // Read a General-Purpose Register
30 method Action write_debug_fgpr (Bit#(5) r, Bit#(`Reg_width) d); // Write a General-Purpose Register
32 method Action write_rd(Bit#(5) r, Bit#(`Reg_width) d, Operand_type rdtype);
33 method Action inferred_xlen(Bit#(2) mxl);
37 module mkregisterfile(Ifc_registerfile);
38 RegFile#(Bit#(5),Bit#(`Reg_width)) integer_rf <-mkRegFileWCF(0,31);
40 RegFile#(Bit#(5),Bit#(`Reg_width)) floating_rf <-mkRegFileWCF(0,31);
42 Reg#(Bool) initialize<-mkReg(True);
43 Reg#(Bit#(5)) rg_index<-mkReg(0);
44 Wire#(Bit#(2)) wr_mxl <- mkWire();
45 rule initialize_regfile(initialize);
47 floating_rf.upd(rg_index,0);
49 integer_rf.upd(rg_index,0);
55 method ActionValue#(Output_for_operand_fetch) _inputs_from_decode_stage(Bit#(5) rs1_addr, Operand_type rs1_type, Bit#(5) rs2_addr, Operand_type rs2_type, Bit#(`VADDR) pc, Bit#(`Reg_width) imm `ifdef spfpu , Bool rs3_valid,Bit#(5) rs3_addr `endif ) if(!initialize); // recives the input from the decode stage.
57 Bit#(`Reg_width) rs1=0;
58 Bit#(`Reg_width) rs2=0;
59 Bit#(`Reg_width) rs3=0;
63 else if(rs1_addr==0 && rs1_type==IntegerRF)
65 else if(rs1_type==IntegerRF)
66 rs1=integer_rf.sub(rs1_addr);
69 rs1=floating_rf.sub(rs1_addr);
72 if(rs2_type==Immediate)
74 else if(rs2_addr==0 && rs2_type==IntegerRF)
76 else if(rs2_type==IntegerRF)
77 rs2=integer_rf.sub(rs2_addr);
80 rs2=floating_rf.sub(rs2_addr);
85 rs3= floating_rf.sub(rs3_addr);
91 if(wr_mxl==1)begin // 32-bit
92 rs1=signExtend(rs1[31:0]);
93 rs2=signExtend(rs2[31:0]);
94 `ifdef spfpu rs3=signExtend(rs3[31:0]); `endif
97 `ifdef verbose $display($time,"\nReg1 :%d : ",rs1_addr,fshow(rs1),"\nReg2 : %d : ",rs2_addr,fshow(rs2) `ifdef spfpu ,"\nReg3: %d ; ",rs3_addr,fshow(rs3) `endif ); `endif
98 return Output_for_operand_fetch{rs1:rs1,rs2:rs2`ifdef spfpu ,rs3: rs3 `endif };
100 method Action write_rd(Bit#(5) r, Bit#(`Reg_width) d, Operand_type rdtype) if(!initialize); // TODO if not in critical path shift the CReg ports.
101 `ifdef verbose $display($time,"\tRF: Writing into reg: :%d data: %h ",r,d,fshow(rdtype)); `endif
102 if(wr_mxl==1)begin // 32-bit
103 d=signExtend(d[31:0]);
105 if(rdtype==IntegerRF)begin
111 else if(rdtype==FloatingRF)begin
112 floating_rf.upd(r,d);
117 method Bit#(`Reg_width) read_debug_igpr (Bit#(5) r); // Read a General-Purpose Register
118 return integer_rf.sub(r);
120 method Action write_debug_igpr (Bit#(5) r, Bit#(`Reg_width) d)if(!initialize); // Write a General-Purpose Register
124 method Bit#(`Reg_width) read_debug_fgpr (Bit#(5) r); // Read a General-Purpose Register
125 return floating_rf.sub(r);
127 method Action write_debug_fgpr (Bit#(5) r, Bit#(`Reg_width) d)if(!initialize); // Write a General-Purpose Register
128 floating_rf.upd(r,d);
132 method Action inferred_xlen(Bit#(2) mxl);