1 # Copyright (c) 2005-2008 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Nathan Binkert
31 from m5
.defines
import buildEnv
32 from m5
.params
import *
33 from m5
.proxy
import *
36 from InstTracer
import InstTracer
37 from ExeTracer
import ExeTracer
38 from MemObject
import MemObject
40 default_tracer
= ExeTracer()
42 if buildEnv
['TARGET_ISA'] == 'alpha':
43 from AlphaTLB
import AlphaDTB
, AlphaITB
44 if buildEnv
['FULL_SYSTEM']:
45 from AlphaInterrupts
import AlphaInterrupts
46 elif buildEnv
['TARGET_ISA'] == 'sparc':
47 from SparcTLB
import SparcTLB
48 if buildEnv
['FULL_SYSTEM']:
49 from SparcInterrupts
import SparcInterrupts
50 elif buildEnv
['TARGET_ISA'] == 'x86':
51 from X86TLB
import X86TLB
52 if buildEnv
['FULL_SYSTEM']:
53 from X86LocalApic
import X86LocalApic
54 elif buildEnv
['TARGET_ISA'] == 'mips':
55 from MipsTLB
import MipsTLB
56 if buildEnv
['FULL_SYSTEM']:
57 from MipsInterrupts
import MipsInterrupts
58 elif buildEnv
['TARGET_ISA'] == 'arm':
59 from ArmTLB
import ArmTLB
60 if buildEnv
['FULL_SYSTEM']:
61 from ArmInterrupts
import ArmInterrupts
62 elif buildEnv
['TARGET_ISA'] == 'power':
63 from PowerTLB
import PowerTLB
64 if buildEnv
['FULL_SYSTEM']:
65 from PowerInterrupts
import PowerInterrupts
67 class BaseCPU(MemObject
):
71 system
= Param
.System(Parent
.any
, "system object")
72 cpu_id
= Param
.Int(-1, "CPU identifier")
73 numThreads
= Param
.Unsigned(1, "number of HW thread contexts")
75 function_trace
= Param
.Bool(False, "Enable function trace")
76 function_trace_start
= Param
.Tick(0, "Cycle to start function trace")
78 checker
= Param
.BaseCPU(NULL
, "checker CPU")
80 do_checkpoint_insts
= Param
.Bool(True,
81 "enable checkpoint pseudo instructions")
82 do_statistics_insts
= Param
.Bool(True,
83 "enable statistics pseudo instructions")
85 if buildEnv
['FULL_SYSTEM']:
86 profile
= Param
.Latency('0ns', "trace the kernel stack")
87 do_quiesce
= Param
.Bool(True, "enable quiesce instructions")
89 workload
= VectorParam
.Process("processes to run")
91 if buildEnv
['TARGET_ISA'] == 'sparc':
92 dtb
= Param
.SparcTLB(SparcTLB(), "Data TLB")
93 itb
= Param
.SparcTLB(SparcTLB(), "Instruction TLB")
94 if buildEnv
['FULL_SYSTEM']:
95 interrupts
= Param
.SparcInterrupts(
96 SparcInterrupts(), "Interrupt Controller")
97 elif buildEnv
['TARGET_ISA'] == 'alpha':
98 dtb
= Param
.AlphaTLB(AlphaDTB(), "Data TLB")
99 itb
= Param
.AlphaTLB(AlphaITB(), "Instruction TLB")
100 if buildEnv
['FULL_SYSTEM']:
101 interrupts
= Param
.AlphaInterrupts(
102 AlphaInterrupts(), "Interrupt Controller")
103 elif buildEnv
['TARGET_ISA'] == 'x86':
104 dtb
= Param
.X86TLB(X86TLB(), "Data TLB")
105 itb
= Param
.X86TLB(X86TLB(), "Instruction TLB")
106 if buildEnv
['FULL_SYSTEM']:
107 _localApic
= X86LocalApic(pio_addr
=0x2000000000000000)
109 Param
.X86LocalApic(_localApic
, "Interrupt Controller")
110 elif buildEnv
['TARGET_ISA'] == 'mips':
111 dtb
= Param
.MipsTLB(MipsTLB(), "Data TLB")
112 itb
= Param
.MipsTLB(MipsTLB(), "Instruction TLB")
113 if buildEnv
['FULL_SYSTEM']:
114 interrupts
= Param
.MipsInterrupts(
115 MipsInterrupts(), "Interrupt Controller")
116 elif buildEnv
['TARGET_ISA'] == 'arm':
117 dtb
= Param
.ArmTLB(ArmTLB(), "Data TLB")
118 itb
= Param
.ArmTLB(ArmTLB(), "Instruction TLB")
119 if buildEnv
['FULL_SYSTEM']:
120 interrupts
= Param
.ArmInterrupts(
121 ArmInterrupts(), "Interrupt Controller")
122 elif buildEnv
['TARGET_ISA'] == 'power':
123 UnifiedTLB
= Param
.Bool(True, "Is this a Unified TLB?")
124 dtb
= Param
.PowerTLB(PowerTLB(), "Data TLB")
125 itb
= Param
.PowerTLB(PowerTLB(), "Instruction TLB")
126 if buildEnv
['FULL_SYSTEM']:
127 interrupts
= Param
.PowerInterrupts(
128 PowerInterrupts(), "Interrupt Controller")
130 print "Don't know what TLB to use for ISA %s" % \
131 buildEnv
['TARGET_ISA']
134 max_insts_all_threads
= Param
.Counter(0,
135 "terminate when all threads have reached this inst count")
136 max_insts_any_thread
= Param
.Counter(0,
137 "terminate when any thread reaches this inst count")
138 max_loads_all_threads
= Param
.Counter(0,
139 "terminate when all threads have reached this load count")
140 max_loads_any_thread
= Param
.Counter(0,
141 "terminate when any thread reaches this load count")
142 progress_interval
= Param
.Tick(0,
143 "interval to print out the progress message")
145 defer_registration
= Param
.Bool(False,
146 "defer registration with system (for sampling)")
148 clock
= Param
.Clock('1t', "clock speed")
149 phase
= Param
.Latency('0ns', "clock phase")
151 tracer
= Param
.InstTracer(default_tracer
, "Instruction tracer")
154 if buildEnv
['TARGET_ISA'] == 'x86' and buildEnv
['FULL_SYSTEM']:
155 _mem_ports
= ["itb.walker.port",
158 "interrupts.int_port"]
160 if buildEnv
['TARGET_ISA'] == 'arm' and buildEnv
['FULL_SYSTEM']:
161 _mem_ports
= ["itb.walker.port",
164 def connectMemPorts(self
, bus
):
165 for p
in self
._mem
_ports
:
166 if p
!= 'physmem_port':
167 exec('self.%s = bus.port' % p
)
169 def addPrivateSplitL1Caches(self
, ic
, dc
):
170 assert(len(self
._mem
_ports
) < 6)
173 self
.icache_port
= ic
.cpu_side
174 self
.dcache_port
= dc
.cpu_side
175 self
._mem
_ports
= ['icache.mem_side', 'dcache.mem_side']
176 if buildEnv
['FULL_SYSTEM']:
177 if buildEnv
['TARGET_ISA'] in ['x86', 'arm']:
178 self
._mem
_ports
+= ["itb.walker.port", "dtb.walker.port"]
180 def addTwoLevelCacheHierarchy(self
, ic
, dc
, l2c
):
181 self
.addPrivateSplitL1Caches(ic
, dc
)
183 self
.connectMemPorts(self
.toL2Bus
)
185 self
.l2cache
.cpu_side
= self
.toL2Bus
.port
186 self
._mem
_ports
= ['l2cache.mem_side']
188 if buildEnv
['TARGET_ISA'] == 'mips':
189 CP0_IntCtl_IPTI
= Param
.Unsigned(0,"No Description")
190 CP0_IntCtl_IPPCI
= Param
.Unsigned(0,"No Description")
191 CP0_SrsCtl_HSS
= Param
.Unsigned(0,"No Description")
192 CP0_EBase_CPUNum
= Param
.Unsigned(0,"No Description")
193 CP0_PRId_CompanyOptions
= Param
.Unsigned(0,"Company Options in Processor ID Register")
194 CP0_PRId_CompanyID
= Param
.Unsigned(0,"Company Identifier in Processor ID Register")
195 CP0_PRId_ProcessorID
= Param
.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
196 CP0_PRId_Revision
= Param
.Unsigned(0,"Processor Revision Number in Processor ID Register")
197 CP0_Config_BE
= Param
.Unsigned(0,"Big Endian?")
198 CP0_Config_AT
= Param
.Unsigned(0,"No Description")
199 CP0_Config_AR
= Param
.Unsigned(0,"No Description")
200 CP0_Config_MT
= Param
.Unsigned(0,"No Description")
201 CP0_Config_VI
= Param
.Unsigned(0,"No Description")
202 CP0_Config1_M
= Param
.Unsigned(0,"Config2 Implemented?")
203 CP0_Config1_MMU
= Param
.Unsigned(0,"MMU Type")
204 CP0_Config1_IS
= Param
.Unsigned(0,"No Description")
205 CP0_Config1_IL
= Param
.Unsigned(0,"No Description")
206 CP0_Config1_IA
= Param
.Unsigned(0,"No Description")
207 CP0_Config1_DS
= Param
.Unsigned(0,"No Description")
208 CP0_Config1_DL
= Param
.Unsigned(0,"No Description")
209 CP0_Config1_DA
= Param
.Unsigned(0,"No Description")
210 CP0_Config1_C2
= Param
.Bool(False,"No Description")
211 CP0_Config1_MD
= Param
.Bool(False,"No Description")
212 CP0_Config1_PC
= Param
.Bool(False,"No Description")
213 CP0_Config1_WR
= Param
.Bool(False,"No Description")
214 CP0_Config1_CA
= Param
.Bool(False,"No Description")
215 CP0_Config1_EP
= Param
.Bool(False,"No Description")
216 CP0_Config1_FP
= Param
.Bool(False,"FPU Implemented?")
217 CP0_Config2_M
= Param
.Bool(False,"Config3 Implemented?")
218 CP0_Config2_TU
= Param
.Unsigned(0,"No Description")
219 CP0_Config2_TS
= Param
.Unsigned(0,"No Description")
220 CP0_Config2_TL
= Param
.Unsigned(0,"No Description")
221 CP0_Config2_TA
= Param
.Unsigned(0,"No Description")
222 CP0_Config2_SU
= Param
.Unsigned(0,"No Description")
223 CP0_Config2_SS
= Param
.Unsigned(0,"No Description")
224 CP0_Config2_SL
= Param
.Unsigned(0,"No Description")
225 CP0_Config2_SA
= Param
.Unsigned(0,"No Description")
226 CP0_Config3_M
= Param
.Bool(False,"Config4 Implemented?")
227 CP0_Config3_DSPP
= Param
.Bool(False,"DSP Extensions Present?")
228 CP0_Config3_LPA
= Param
.Bool(False,"No Description")
229 CP0_Config3_VEIC
= Param
.Bool(False,"No Description")
230 CP0_Config3_VInt
= Param
.Bool(False,"No Description")
231 CP0_Config3_SP
= Param
.Bool(False,"No Description")
232 CP0_Config3_MT
= Param
.Bool(False,"Multithreading Extensions Present?")
233 CP0_Config3_SM
= Param
.Bool(False,"No Description")
234 CP0_Config3_TL
= Param
.Bool(False,"No Description")
235 CP0_WatchHi_M
= Param
.Bool(False,"No Description")
236 CP0_PerfCtr_M
= Param
.Bool(False,"No Description")
237 CP0_PerfCtr_W
= Param
.Bool(False,"No Description")
238 CP0_PRId
= Param
.Unsigned(0,"CP0 Status Register")
239 CP0_Config
= Param
.Unsigned(0,"CP0 Config Register")
240 CP0_Config1
= Param
.Unsigned(0,"CP0 Config1 Register")
241 CP0_Config2
= Param
.Unsigned(0,"CP0 Config2 Register")
242 CP0_Config3
= Param
.Unsigned(0,"CP0 Config3 Register")