src/cpu/BaseCPU.py

   1 # Copyright (c) 2012 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2005-2008 The Regents of The University of Michigan
  14 # Copyright (c) 2011 Regents of the University of California
  15 # All rights reserved.
  16 #
  17 # Redistribution and use in source and binary forms, with or without
  18 # modification, are permitted provided that the following conditions are
  19 # met: redistributions of source code must retain the above copyright
  20 # notice, this list of conditions and the following disclaimer;
  21 # redistributions in binary form must reproduce the above copyright
  22 # notice, this list of conditions and the following disclaimer in the
  23 # documentation and/or other materials provided with the distribution;
  24 # neither the name of the copyright holders nor the names of its
  25 # contributors may be used to endorse or promote products derived from
  26 # this software without specific prior written permission.
  27 #
  28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39 #
  40 # Authors: Nathan Binkert
  41 #          Rick Strong
  42 #          Andreas Hansson
  43
  44 import sys
  45
  46 from m5.defines import buildEnv
  47 from m5.params import *
  48 from m5.proxy import *
  49
  50 from Bus import CoherentBus
  51 from InstTracer import InstTracer
  52 from ExeTracer import ExeTracer
  53 from MemObject import MemObject
  54
  55 default_tracer = ExeTracer()
  56
  57 if buildEnv['TARGET_ISA'] == 'alpha':
  58     from AlphaTLB import AlphaDTB, AlphaITB
  59     from AlphaInterrupts import AlphaInterrupts
  60     from AlphaISA import AlphaISA
  61     isa_class = AlphaISA
  62 elif buildEnv['TARGET_ISA'] == 'sparc':
  63     from SparcTLB import SparcTLB
  64     from SparcInterrupts import SparcInterrupts
  65     from SparcISA import SparcISA
  66     isa_class = SparcISA
  67 elif buildEnv['TARGET_ISA'] == 'x86':
  68     from X86TLB import X86TLB
  69     from X86LocalApic import X86LocalApic
  70     from X86ISA import X86ISA
  71     isa_class = X86ISA
  72 elif buildEnv['TARGET_ISA'] == 'mips':
  73     from MipsTLB import MipsTLB
  74     from MipsInterrupts import MipsInterrupts
  75     from MipsISA import MipsISA
  76     isa_class = MipsISA
  77 elif buildEnv['TARGET_ISA'] == 'arm':
  78     from ArmTLB import ArmTLB
  79     from ArmInterrupts import ArmInterrupts
  80     from ArmISA import ArmISA
  81     isa_class = ArmISA
  82 elif buildEnv['TARGET_ISA'] == 'power':
  83     from PowerTLB import PowerTLB
  84     from PowerInterrupts import PowerInterrupts
  85     from PowerISA import PowerISA
  86     isa_class = PowerISA
  87
  88 class BaseCPU(MemObject):
  89     type = 'BaseCPU'
  90     abstract = True
  91     cxx_header = "cpu/base.hh"
  92
  93     @classmethod
  94     def export_methods(cls, code):
  95         code('''
  96     void switchOut();
  97     void takeOverFrom(BaseCPU *cpu);
  98     bool switchedOut();
  99     void flushTLBs();
 100 ''')
 101
 102     def takeOverFrom(self, old_cpu):
 103         self._ccObject.takeOverFrom(old_cpu._ccObject)
 104
 105
 106     system = Param.System(Parent.any, "system object")
 107     cpu_id = Param.Int(-1, "CPU identifier")
 108     numThreads = Param.Unsigned(1, "number of HW thread contexts")
 109
 110     function_trace = Param.Bool(False, "Enable function trace")
 111     function_trace_start = Param.Tick(0, "Tick to start function trace")
 112
 113     checker = Param.BaseCPU(NULL, "checker CPU")
 114
 115     do_checkpoint_insts = Param.Bool(True,
 116         "enable checkpoint pseudo instructions")
 117     do_statistics_insts = Param.Bool(True,
 118         "enable statistics pseudo instructions")
 119
 120     profile = Param.Latency('0ns', "trace the kernel stack")
 121     do_quiesce = Param.Bool(True, "enable quiesce instructions")
 122
 123     workload = VectorParam.Process([], "processes to run")
 124
 125     if buildEnv['TARGET_ISA'] == 'sparc':
 126         dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
 127         itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
 128         interrupts = Param.SparcInterrupts(
 129                 NULL, "Interrupt Controller")
 130         isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
 131     elif buildEnv['TARGET_ISA'] == 'alpha':
 132         dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
 133         itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
 134         interrupts = Param.AlphaInterrupts(
 135                 NULL, "Interrupt Controller")
 136         isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
 137     elif buildEnv['TARGET_ISA'] == 'x86':
 138         dtb = Param.X86TLB(X86TLB(), "Data TLB")
 139         itb = Param.X86TLB(X86TLB(), "Instruction TLB")
 140         interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
 141         isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
 142     elif buildEnv['TARGET_ISA'] == 'mips':
 143         dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
 144         itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
 145         interrupts = Param.MipsInterrupts(
 146                 NULL, "Interrupt Controller")
 147         isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
 148     elif buildEnv['TARGET_ISA'] == 'arm':
 149         dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
 150         itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
 151         interrupts = Param.ArmInterrupts(
 152                 NULL, "Interrupt Controller")
 153         isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
 154     elif buildEnv['TARGET_ISA'] == 'power':
 155         UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
 156         dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
 157         itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
 158         interrupts = Param.PowerInterrupts(
 159                 NULL, "Interrupt Controller")
 160         isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
 161     else:
 162         print "Don't know what TLB to use for ISA %s" % \
 163             buildEnv['TARGET_ISA']
 164         sys.exit(1)
 165
 166     max_insts_all_threads = Param.Counter(0,
 167         "terminate when all threads have reached this inst count")
 168     max_insts_any_thread = Param.Counter(0,
 169         "terminate when any thread reaches this inst count")
 170     max_loads_all_threads = Param.Counter(0,
 171         "terminate when all threads have reached this load count")
 172     max_loads_any_thread = Param.Counter(0,
 173         "terminate when any thread reaches this load count")
 174     progress_interval = Param.Frequency('0Hz',
 175         "frequency to print out the progress message")
 176
 177     switched_out = Param.Bool(False,
 178         "Leave the CPU switched out after startup (used when switching " \
 179         "between CPU models)")
 180
 181     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 182
 183     icache_port = MasterPort("Instruction Port")
 184     dcache_port = MasterPort("Data Port")
 185     _cached_ports = ['icache_port', 'dcache_port']
 186
 187     if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
 188         _cached_ports += ["itb.walker.port", "dtb.walker.port"]
 189
 190     _uncached_slave_ports = []
 191     _uncached_master_ports = []
 192     if buildEnv['TARGET_ISA'] == 'x86':
 193         _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
 194         _uncached_master_ports += ["interrupts.int_master"]
 195
 196     def createInterruptController(self):
 197         if buildEnv['TARGET_ISA'] == 'sparc':
 198             self.interrupts = SparcInterrupts()
 199         elif buildEnv['TARGET_ISA'] == 'alpha':
 200             self.interrupts = AlphaInterrupts()
 201         elif buildEnv['TARGET_ISA'] == 'x86':
 202             _localApic = X86LocalApic(pio_addr=0x2000000000000000)
 203             self.interrupts = _localApic
 204         elif buildEnv['TARGET_ISA'] == 'mips':
 205             self.interrupts = MipsInterrupts()
 206         elif buildEnv['TARGET_ISA'] == 'arm':
 207             self.interrupts = ArmInterrupts()
 208         elif buildEnv['TARGET_ISA'] == 'power':
 209             self.interrupts = PowerInterrupts()
 210         else:
 211             print "Don't know what Interrupt Controller to use for ISA %s" % \
 212                 buildEnv['TARGET_ISA']
 213             sys.exit(1)
 214
 215     def connectCachedPorts(self, bus):
 216         for p in self._cached_ports:
 217             exec('self.%s = bus.slave' % p)
 218
 219     def connectUncachedPorts(self, bus):
 220         for p in self._uncached_slave_ports:
 221             exec('self.%s = bus.master' % p)
 222         for p in self._uncached_master_ports:
 223             exec('self.%s = bus.slave' % p)
 224
 225     def connectAllPorts(self, cached_bus, uncached_bus = None):
 226         self.connectCachedPorts(cached_bus)
 227         if not uncached_bus:
 228             uncached_bus = cached_bus
 229         self.connectUncachedPorts(uncached_bus)
 230
 231     def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
 232         self.icache = ic
 233         self.dcache = dc
 234         self.icache_port = ic.cpu_side
 235         self.dcache_port = dc.cpu_side
 236         self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
 237         if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
 238             if iwc and dwc:
 239                 self.itb_walker_cache = iwc
 240                 self.dtb_walker_cache = dwc
 241                 self.itb.walker.port = iwc.cpu_side
 242                 self.dtb.walker.port = dwc.cpu_side
 243                 self._cached_ports += ["itb_walker_cache.mem_side", \
 244                                        "dtb_walker_cache.mem_side"]
 245             else:
 246                 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
 247
 248             # Checker doesn't need its own tlb caches because it does
 249             # functional accesses only
 250             if self.checker != NULL:
 251                 self._cached_ports += ["checker.itb.walker.port", \
 252                                        "checker.dtb.walker.port"]
 253
 254     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
 255         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
 256         # Override the default bus clock of 1 GHz and uses the CPU
 257         # clock for the L1-to-L2 bus, and also set a width of 32 bytes
 258         # (256-bits), which is four times that of the default bus.
 259         self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
 260         self.connectCachedPorts(self.toL2Bus)
 261         self.l2cache = l2c
 262         self.toL2Bus.master = self.l2cache.cpu_side
 263         self._cached_ports = ['l2cache.mem_side']
 264
 265     def createThreads(self):
 266         self.isa = [ isa_class() for i in xrange(self.numThreads) ]
 267         if self.checker != NULL:
 268             self.checker.createThreads()
 269
 270     def addCheckerCpu(self):
 271         pass