1 # Copyright (c) 2005-2008 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 # Authors: Nathan Binkert
29 from MemObject
import MemObject
30 from m5
.params
import *
31 from m5
.proxy
import *
32 from m5
import build_env
34 from InstTracer
import InstTracer
35 from ExeTracer
import ExeTracer
38 default_tracer
= ExeTracer()
40 if build_env
['TARGET_ISA'] == 'alpha':
41 from AlphaTLB
import AlphaDTB
, AlphaITB
42 if build_env
['FULL_SYSTEM']:
43 from AlphaInterrupts
import AlphaInterrupts
44 elif build_env
['TARGET_ISA'] == 'sparc':
45 from SparcTLB
import SparcDTB
, SparcITB
46 if build_env
['FULL_SYSTEM']:
47 from SparcInterrupts
import SparcInterrupts
48 elif build_env
['TARGET_ISA'] == 'x86':
49 from X86TLB
import X86DTB
, X86ITB
50 if build_env
['FULL_SYSTEM']:
51 from X86LocalApic
import X86LocalApic
52 elif build_env
['TARGET_ISA'] == 'mips':
53 from MipsTLB
import MipsTLB
,MipsDTB
, MipsITB
, MipsUTB
54 if build_env
['FULL_SYSTEM']:
55 from MipsInterrupts
import MipsInterrupts
56 elif build_env
['TARGET_ISA'] == 'arm':
57 from ArmTLB
import ArmTLB
, ArmDTB
, ArmITB
, ArmUTB
58 if build_env
['FULL_SYSTEM']:
59 from ArmInterrupts
import ArmInterrupts
61 class BaseCPU(MemObject
):
65 system
= Param
.System(Parent
.any
, "system object")
66 cpu_id
= Param
.Int("CPU identifier")
67 numThreads
= Param
.Unsigned(1, "number of HW thread contexts")
69 function_trace
= Param
.Bool(False, "Enable function trace")
70 function_trace_start
= Param
.Tick(0, "Cycle to start function trace")
72 checker
= Param
.BaseCPU("checker CPU")
74 if build_env
['FULL_SYSTEM']:
75 profile
= Param
.Latency('0ns', "trace the kernel stack")
76 do_quiesce
= Param
.Bool(True, "enable quiesce instructions")
77 do_checkpoint_insts
= Param
.Bool(True,
78 "enable checkpoint pseudo instructions")
79 do_statistics_insts
= Param
.Bool(True,
80 "enable statistics pseudo instructions")
82 workload
= VectorParam
.Process("processes to run")
84 if build_env
['TARGET_ISA'] == 'sparc':
85 dtb
= Param
.SparcDTB(SparcDTB(), "Data TLB")
86 itb
= Param
.SparcITB(SparcITB(), "Instruction TLB")
87 if build_env
['FULL_SYSTEM']:
88 interrupts
= Param
.SparcInterrupts(
89 SparcInterrupts(), "Interrupt Controller")
90 elif build_env
['TARGET_ISA'] == 'alpha':
91 dtb
= Param
.AlphaDTB(AlphaDTB(), "Data TLB")
92 itb
= Param
.AlphaITB(AlphaITB(), "Instruction TLB")
93 if build_env
['FULL_SYSTEM']:
94 interrupts
= Param
.AlphaInterrupts(
95 AlphaInterrupts(), "Interrupt Controller")
96 elif build_env
['TARGET_ISA'] == 'x86':
97 dtb
= Param
.X86DTB(X86DTB(), "Data TLB")
98 itb
= Param
.X86ITB(X86ITB(), "Instruction TLB")
99 if build_env
['FULL_SYSTEM']:
100 interrupts
= Param
.X86LocalApic(
101 X86LocalApic(), "Interrupt Controller")
102 elif build_env
['TARGET_ISA'] == 'mips':
103 UnifiedTLB
= Param
.Bool(True, "Is this a Unified TLB?")
104 dtb
= Param
.MipsDTB(MipsDTB(), "Data TLB")
105 itb
= Param
.MipsITB(MipsITB(), "Instruction TLB")
106 tlb
= Param
.MipsUTB(MipsUTB(), "Unified TLB")
107 if build_env
['FULL_SYSTEM']:
108 interrupts
= Param
.MipsInterrupts(
109 MipsInterrupts(), "Interrupt Controller")
110 elif build_env
['TARGET_ISA'] == 'arm':
111 UnifiedTLB
= Param
.Bool(True, "Is this a Unified TLB?")
112 dtb
= Param
.ArmDTB(ArmDTB(), "Data TLB")
113 itb
= Param
.ArmITB(ArmITB(), "Instruction TLB")
114 tlb
= Param
.ArmUTB(ArmUTB(), "Unified TLB")
115 if build_env
['FULL_SYSTEM']:
116 interrupts
= Param
.ArmInterrupts(
117 ArmInterrupts(), "Interrupt Controller")
119 print "Don't know what TLB to use for ISA %s" % \
120 build_env
['TARGET_ISA']
123 max_insts_all_threads
= Param
.Counter(0,
124 "terminate when all threads have reached this inst count")
125 max_insts_any_thread
= Param
.Counter(0,
126 "terminate when any thread reaches this inst count")
127 max_loads_all_threads
= Param
.Counter(0,
128 "terminate when all threads have reached this load count")
129 max_loads_any_thread
= Param
.Counter(0,
130 "terminate when any thread reaches this load count")
131 progress_interval
= Param
.Tick(0,
132 "interval to print out the progress message")
134 defer_registration
= Param
.Bool(False,
135 "defer registration with system (for sampling)")
137 clock
= Param
.Clock('1t', "clock speed")
138 phase
= Param
.Latency('0ns', "clock phase")
140 tracer
= Param
.InstTracer(default_tracer
, "Instruction tracer")
143 if build_env
['TARGET_ISA'] == 'x86' and build_env
['FULL_SYSTEM']:
144 _mem_ports
= ["itb.walker.port", "dtb.walker.port"]
146 def connectMemPorts(self
, bus
):
147 for p
in self
._mem
_ports
:
148 if p
!= 'physmem_port':
149 exec('self.%s = bus.port' % p
)
151 def addPrivateSplitL1Caches(self
, ic
, dc
):
152 assert(len(self
._mem
_ports
) < 6)
155 self
.icache_port
= ic
.cpu_side
156 self
.dcache_port
= dc
.cpu_side
157 self
._mem
_ports
= ['icache.mem_side', 'dcache.mem_side']
158 if build_env
['TARGET_ISA'] == 'x86' and build_env
['FULL_SYSTEM']:
159 self
._mem
_ports
+= ["itb.walker_port", "dtb.walker_port"]
161 def addTwoLevelCacheHierarchy(self
, ic
, dc
, l2c
):
162 self
.addPrivateSplitL1Caches(ic
, dc
)
164 self
.connectMemPorts(self
.toL2Bus
)
166 self
.l2cache
.cpu_side
= self
.toL2Bus
.port
167 self
._mem
_ports
= ['l2cache.mem_side']
169 if build_env
['TARGET_ISA'] == 'mips':
170 CP0_IntCtl_IPTI
= Param
.Unsigned(0,"No Description")
171 CP0_IntCtl_IPPCI
= Param
.Unsigned(0,"No Description")
172 CP0_SrsCtl_HSS
= Param
.Unsigned(0,"No Description")
173 CP0_EBase_CPUNum
= Param
.Unsigned(0,"No Description")
174 CP0_PRId_CompanyOptions
= Param
.Unsigned(0,"Company Options in Processor ID Register")
175 CP0_PRId_CompanyID
= Param
.Unsigned(0,"Company Identifier in Processor ID Register")
176 CP0_PRId_ProcessorID
= Param
.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
177 CP0_PRId_Revision
= Param
.Unsigned(0,"Processor Revision Number in Processor ID Register")
178 CP0_Config_BE
= Param
.Unsigned(0,"Big Endian?")
179 CP0_Config_AT
= Param
.Unsigned(0,"No Description")
180 CP0_Config_AR
= Param
.Unsigned(0,"No Description")
181 CP0_Config_MT
= Param
.Unsigned(0,"No Description")
182 CP0_Config_VI
= Param
.Unsigned(0,"No Description")
183 CP0_Config1_M
= Param
.Unsigned(0,"Config2 Implemented?")
184 CP0_Config1_MMU
= Param
.Unsigned(0,"MMU Type")
185 CP0_Config1_IS
= Param
.Unsigned(0,"No Description")
186 CP0_Config1_IL
= Param
.Unsigned(0,"No Description")
187 CP0_Config1_IA
= Param
.Unsigned(0,"No Description")
188 CP0_Config1_DS
= Param
.Unsigned(0,"No Description")
189 CP0_Config1_DL
= Param
.Unsigned(0,"No Description")
190 CP0_Config1_DA
= Param
.Unsigned(0,"No Description")
191 CP0_Config1_C2
= Param
.Bool(False,"No Description")
192 CP0_Config1_MD
= Param
.Bool(False,"No Description")
193 CP0_Config1_PC
= Param
.Bool(False,"No Description")
194 CP0_Config1_WR
= Param
.Bool(False,"No Description")
195 CP0_Config1_CA
= Param
.Bool(False,"No Description")
196 CP0_Config1_EP
= Param
.Bool(False,"No Description")
197 CP0_Config1_FP
= Param
.Bool(False,"FPU Implemented?")
198 CP0_Config2_M
= Param
.Bool(False,"Config3 Implemented?")
199 CP0_Config2_TU
= Param
.Unsigned(0,"No Description")
200 CP0_Config2_TS
= Param
.Unsigned(0,"No Description")
201 CP0_Config2_TL
= Param
.Unsigned(0,"No Description")
202 CP0_Config2_TA
= Param
.Unsigned(0,"No Description")
203 CP0_Config2_SU
= Param
.Unsigned(0,"No Description")
204 CP0_Config2_SS
= Param
.Unsigned(0,"No Description")
205 CP0_Config2_SL
= Param
.Unsigned(0,"No Description")
206 CP0_Config2_SA
= Param
.Unsigned(0,"No Description")
207 CP0_Config3_M
= Param
.Bool(False,"Config4 Implemented?")
208 CP0_Config3_DSPP
= Param
.Bool(False,"DSP Extensions Present?")
209 CP0_Config3_LPA
= Param
.Bool(False,"No Description")
210 CP0_Config3_VEIC
= Param
.Bool(False,"No Description")
211 CP0_Config3_VInt
= Param
.Bool(False,"No Description")
212 CP0_Config3_SP
= Param
.Bool(False,"No Description")
213 CP0_Config3_MT
= Param
.Bool(False,"Multithreading Extensions Present?")
214 CP0_Config3_SM
= Param
.Bool(False,"No Description")
215 CP0_Config3_TL
= Param
.Bool(False,"No Description")
216 CP0_WatchHi_M
= Param
.Bool(False,"No Description")
217 CP0_PerfCtr_M
= Param
.Bool(False,"No Description")
218 CP0_PerfCtr_W
= Param
.Bool(False,"No Description")
219 CP0_PRId
= Param
.Unsigned(0,"CP0 Status Register")
220 CP0_Config
= Param
.Unsigned(0,"CP0 Config Register")
221 CP0_Config1
= Param
.Unsigned(0,"CP0 Config1 Register")
222 CP0_Config2
= Param
.Unsigned(0,"CP0 Config2 Register")
223 CP0_Config3
= Param
.Unsigned(0,"CP0 Config3 Register")