1 # Copyright (c) 2012 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2005-2008 The Regents of The University of Michigan
14 # Copyright (c) 2011 Regents of the University of California
15 # All rights reserved.
17 # Redistribution and use in source and binary forms, with or without
18 # modification, are permitted provided that the following conditions are
19 # met: redistributions of source code must retain the above copyright
20 # notice, this list of conditions and the following disclaimer;
21 # redistributions in binary form must reproduce the above copyright
22 # notice, this list of conditions and the following disclaimer in the
23 # documentation and/or other materials provided with the distribution;
24 # neither the name of the copyright holders nor the names of its
25 # contributors may be used to endorse or promote products derived from
26 # this software without specific prior written permission.
28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 # Authors: Nathan Binkert
46 from m5
.defines
import buildEnv
47 from m5
.params
import *
48 from m5
.proxy
import *
50 from Bus
import CoherentBus
51 from InstTracer
import InstTracer
52 from ExeTracer
import ExeTracer
53 from MemObject
import MemObject
55 default_tracer
= ExeTracer()
57 if buildEnv
['TARGET_ISA'] == 'alpha':
58 from AlphaTLB
import AlphaDTB
, AlphaITB
59 from AlphaInterrupts
import AlphaInterrupts
60 elif buildEnv
['TARGET_ISA'] == 'sparc':
61 from SparcTLB
import SparcTLB
62 from SparcInterrupts
import SparcInterrupts
63 elif buildEnv
['TARGET_ISA'] == 'x86':
64 from X86TLB
import X86TLB
65 from X86LocalApic
import X86LocalApic
66 elif buildEnv
['TARGET_ISA'] == 'mips':
67 from MipsTLB
import MipsTLB
68 from MipsInterrupts
import MipsInterrupts
69 elif buildEnv
['TARGET_ISA'] == 'arm':
70 from ArmTLB
import ArmTLB
71 from ArmInterrupts
import ArmInterrupts
72 elif buildEnv
['TARGET_ISA'] == 'power':
73 from PowerTLB
import PowerTLB
74 from PowerInterrupts
import PowerInterrupts
76 class BaseCPU(MemObject
):
79 cxx_header
= "cpu/base.hh"
82 def export_methods(cls
, code
):
85 void takeOverFrom(BaseCPU *cpu);
88 def takeOverFrom(self
, old_cpu
):
89 self
._ccObject
.takeOverFrom(old_cpu
._ccObject
)
92 system
= Param
.System(Parent
.any
, "system object")
93 cpu_id
= Param
.Int(-1, "CPU identifier")
94 numThreads
= Param
.Unsigned(1, "number of HW thread contexts")
96 function_trace
= Param
.Bool(False, "Enable function trace")
97 function_trace_start
= Param
.Tick(0, "Tick to start function trace")
99 checker
= Param
.BaseCPU(NULL
, "checker CPU")
101 do_checkpoint_insts
= Param
.Bool(True,
102 "enable checkpoint pseudo instructions")
103 do_statistics_insts
= Param
.Bool(True,
104 "enable statistics pseudo instructions")
106 profile
= Param
.Latency('0ns', "trace the kernel stack")
107 do_quiesce
= Param
.Bool(True, "enable quiesce instructions")
109 workload
= VectorParam
.Process([], "processes to run")
111 if buildEnv
['TARGET_ISA'] == 'sparc':
112 dtb
= Param
.SparcTLB(SparcTLB(), "Data TLB")
113 itb
= Param
.SparcTLB(SparcTLB(), "Instruction TLB")
114 interrupts
= Param
.SparcInterrupts(
115 NULL
, "Interrupt Controller")
116 elif buildEnv
['TARGET_ISA'] == 'alpha':
117 dtb
= Param
.AlphaTLB(AlphaDTB(), "Data TLB")
118 itb
= Param
.AlphaTLB(AlphaITB(), "Instruction TLB")
119 interrupts
= Param
.AlphaInterrupts(
120 NULL
, "Interrupt Controller")
121 elif buildEnv
['TARGET_ISA'] == 'x86':
122 dtb
= Param
.X86TLB(X86TLB(), "Data TLB")
123 itb
= Param
.X86TLB(X86TLB(), "Instruction TLB")
124 interrupts
= Param
.X86LocalApic(NULL
, "Interrupt Controller")
125 elif buildEnv
['TARGET_ISA'] == 'mips':
126 dtb
= Param
.MipsTLB(MipsTLB(), "Data TLB")
127 itb
= Param
.MipsTLB(MipsTLB(), "Instruction TLB")
128 interrupts
= Param
.MipsInterrupts(
129 NULL
, "Interrupt Controller")
130 elif buildEnv
['TARGET_ISA'] == 'arm':
131 dtb
= Param
.ArmTLB(ArmTLB(), "Data TLB")
132 itb
= Param
.ArmTLB(ArmTLB(), "Instruction TLB")
133 interrupts
= Param
.ArmInterrupts(
134 NULL
, "Interrupt Controller")
135 elif buildEnv
['TARGET_ISA'] == 'power':
136 UnifiedTLB
= Param
.Bool(True, "Is this a Unified TLB?")
137 dtb
= Param
.PowerTLB(PowerTLB(), "Data TLB")
138 itb
= Param
.PowerTLB(PowerTLB(), "Instruction TLB")
139 interrupts
= Param
.PowerInterrupts(
140 NULL
, "Interrupt Controller")
142 print "Don't know what TLB to use for ISA %s" % \
143 buildEnv
['TARGET_ISA']
146 max_insts_all_threads
= Param
.Counter(0,
147 "terminate when all threads have reached this inst count")
148 max_insts_any_thread
= Param
.Counter(0,
149 "terminate when any thread reaches this inst count")
150 max_loads_all_threads
= Param
.Counter(0,
151 "terminate when all threads have reached this load count")
152 max_loads_any_thread
= Param
.Counter(0,
153 "terminate when any thread reaches this load count")
154 progress_interval
= Param
.Frequency('0Hz',
155 "frequency to print out the progress message")
157 defer_registration
= Param
.Bool(False,
158 "defer registration with system (for sampling)")
160 tracer
= Param
.InstTracer(default_tracer
, "Instruction tracer")
162 icache_port
= MasterPort("Instruction Port")
163 dcache_port
= MasterPort("Data Port")
164 _cached_ports
= ['icache_port', 'dcache_port']
166 if buildEnv
['TARGET_ISA'] in ['x86', 'arm']:
167 _cached_ports
+= ["itb.walker.port", "dtb.walker.port"]
169 _uncached_slave_ports
= []
170 _uncached_master_ports
= []
171 if buildEnv
['TARGET_ISA'] == 'x86':
172 _uncached_slave_ports
+= ["interrupts.pio", "interrupts.int_slave"]
173 _uncached_master_ports
+= ["interrupts.int_master"]
175 def createInterruptController(self
):
176 if buildEnv
['TARGET_ISA'] == 'sparc':
177 self
.interrupts
= SparcInterrupts()
178 elif buildEnv
['TARGET_ISA'] == 'alpha':
179 self
.interrupts
= AlphaInterrupts()
180 elif buildEnv
['TARGET_ISA'] == 'x86':
181 _localApic
= X86LocalApic(pio_addr
=0x2000000000000000)
182 self
.interrupts
= _localApic
183 elif buildEnv
['TARGET_ISA'] == 'mips':
184 self
.interrupts
= MipsInterrupts()
185 elif buildEnv
['TARGET_ISA'] == 'arm':
186 self
.interrupts
= ArmInterrupts()
187 elif buildEnv
['TARGET_ISA'] == 'power':
188 self
.interrupts
= PowerInterrupts()
190 print "Don't know what Interrupt Controller to use for ISA %s" % \
191 buildEnv
['TARGET_ISA']
194 def connectCachedPorts(self
, bus
):
195 for p
in self
._cached
_ports
:
196 exec('self.%s = bus.slave' % p
)
198 def connectUncachedPorts(self
, bus
):
199 for p
in self
._uncached
_slave
_ports
:
200 exec('self.%s = bus.master' % p
)
201 for p
in self
._uncached
_master
_ports
:
202 exec('self.%s = bus.slave' % p
)
204 def connectAllPorts(self
, cached_bus
, uncached_bus
= None):
205 self
.connectCachedPorts(cached_bus
)
207 uncached_bus
= cached_bus
208 self
.connectUncachedPorts(uncached_bus
)
210 def addPrivateSplitL1Caches(self
, ic
, dc
, iwc
= None, dwc
= None):
213 self
.icache_port
= ic
.cpu_side
214 self
.dcache_port
= dc
.cpu_side
215 self
._cached
_ports
= ['icache.mem_side', 'dcache.mem_side']
216 if buildEnv
['TARGET_ISA'] in ['x86', 'arm']:
218 self
.itb_walker_cache
= iwc
219 self
.dtb_walker_cache
= dwc
220 self
.itb
.walker
.port
= iwc
.cpu_side
221 self
.dtb
.walker
.port
= dwc
.cpu_side
222 self
._cached
_ports
+= ["itb_walker_cache.mem_side", \
223 "dtb_walker_cache.mem_side"]
225 self
._cached
_ports
+= ["itb.walker.port", "dtb.walker.port"]
227 # Checker doesn't need its own tlb caches because it does
228 # functional accesses only
229 if self
.checker
!= NULL
:
230 self
._cached
_ports
+= ["checker.itb.walker.port", \
231 "checker.dtb.walker.port"]
233 def addTwoLevelCacheHierarchy(self
, ic
, dc
, l2c
, iwc
= None, dwc
= None):
234 self
.addPrivateSplitL1Caches(ic
, dc
, iwc
, dwc
)
235 # Override the default bus clock of 1 GHz and uses the CPU
236 # clock for the L1-to-L2 bus, and also set a width of 32 bytes
237 # (256-bits), which is four times that of the default bus.
238 self
.toL2Bus
= CoherentBus(clock
= Parent
.clock
, width
= 32)
239 self
.connectCachedPorts(self
.toL2Bus
)
241 self
.toL2Bus
.master
= self
.l2cache
.cpu_side
242 self
._cached
_ports
= ['l2cache.mem_side']
244 def addCheckerCpu(self
):