src/cpu/BaseCPU.py

   1 # Copyright (c) 2012-2013, 2015-2017 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
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  13 # Copyright (c) 2005-2008 The Regents of The University of Michigan
  14 # Copyright (c) 2011 Regents of the University of California
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  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39
  40 from __future__ import print_function
  41
  42 import sys
  43
  44 from m5.SimObject import *
  45 from m5.defines import buildEnv
  46 from m5.params import *
  47 from m5.proxy import *
  48 from m5.util.fdthelper import *
  49
  50 from m5.objects.ClockedObject import ClockedObject
  51 from m5.objects.XBar import L2XBar
  52 from m5.objects.InstTracer import InstTracer
  53 from m5.objects.CPUTracers import ExeTracer
  54 from m5.objects.SubSystem import SubSystem
  55 from m5.objects.ClockDomain import *
  56 from m5.objects.Platform import Platform
  57
  58 default_tracer = ExeTracer()
  59
  60 if buildEnv['TARGET_ISA'] == 'sparc':
  61     from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
  62     from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts
  63     from m5.objects.SparcISA import SparcISA as ArchISA
  64 elif buildEnv['TARGET_ISA'] == 'x86':
  65     from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
  66     from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts
  67     from m5.objects.X86ISA import X86ISA as ArchISA
  68 elif buildEnv['TARGET_ISA'] == 'mips':
  69     from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
  70     from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts
  71     from m5.objects.MipsISA import MipsISA as ArchISA
  72 elif buildEnv['TARGET_ISA'] == 'arm':
  73     from m5.objects.ArmTLB import ArmDTB as ArchDTB, ArmITB as ArchITB
  74     from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts
  75     from m5.objects.ArmISA import ArmISA as ArchISA
  76 elif buildEnv['TARGET_ISA'] == 'power':
  77     from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
  78     from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts
  79     from m5.objects.PowerISA import PowerISA as ArchISA
  80 elif buildEnv['TARGET_ISA'] == 'riscv':
  81     from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
  82     from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts
  83     from m5.objects.RiscvISA import RiscvISA as ArchISA
  84 else:
  85     print("Don't know what object types to use for ISA %s" %
  86             buildEnv['TARGET_ISA'])
  87     sys.exit(1)
  88
  89 class BaseCPU(ClockedObject):
  90     type = 'BaseCPU'
  91     abstract = True
  92     cxx_header = "cpu/base.hh"
  93
  94     cxx_exports = [
  95         PyBindMethod("switchOut"),
  96         PyBindMethod("takeOverFrom"),
  97         PyBindMethod("switchedOut"),
  98         PyBindMethod("flushTLBs"),
  99         PyBindMethod("totalInsts"),
 100         PyBindMethod("scheduleInstStop"),
 101         PyBindMethod("getCurrentInstCount"),
 102     ]
 103
 104     @classmethod
 105     def memory_mode(cls):
 106         """Which memory mode does this CPU require?"""
 107         return 'invalid'
 108
 109     @classmethod
 110     def require_caches(cls):
 111         """Does the CPU model require caches?
 112
 113         Some CPU models might make assumptions that require them to
 114         have caches.
 115         """
 116         return False
 117
 118     @classmethod
 119     def support_take_over(cls):
 120         """Does the CPU model support CPU takeOverFrom?"""
 121         return False
 122
 123     def takeOverFrom(self, old_cpu):
 124         self._ccObject.takeOverFrom(old_cpu._ccObject)
 125
 126
 127     system = Param.System(Parent.any, "system object")
 128     cpu_id = Param.Int(-1, "CPU identifier")
 129     socket_id = Param.Unsigned(0, "Physical Socket identifier")
 130     numThreads = Param.Unsigned(1, "number of HW thread contexts")
 131     pwr_gating_latency = Param.Cycles(300,
 132         "Latency to enter power gating state when all contexts are suspended")
 133
 134     power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\
 135         "to the OFF power state after all thread are disabled for "\
 136         "pwr_gating_latency cycles")
 137
 138     function_trace = Param.Bool(False, "Enable function trace")
 139     function_trace_start = Param.Tick(0, "Tick to start function trace")
 140
 141     checker = Param.BaseCPU(NULL, "checker CPU")
 142
 143     syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry")
 144
 145     do_checkpoint_insts = Param.Bool(True,
 146         "enable checkpoint pseudo instructions")
 147     do_statistics_insts = Param.Bool(True,
 148         "enable statistics pseudo instructions")
 149
 150     profile = Param.Latency('0ns', "trace the kernel stack")
 151     do_quiesce = Param.Bool(True, "enable quiesce instructions")
 152
 153     wait_for_remote_gdb = Param.Bool(False,
 154         "Wait for a remote GDB connection");
 155
 156     workload = VectorParam.Process([], "processes to run")
 157
 158     dtb = Param.BaseTLB(ArchDTB(), "Data TLB")
 159     itb = Param.BaseTLB(ArchITB(), "Instruction TLB")
 160     if buildEnv['TARGET_ISA'] == 'power':
 161         UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
 162     interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller")
 163     isa = VectorParam.BaseISA([], "ISA instance")
 164
 165     max_insts_all_threads = Param.Counter(0,
 166         "terminate when all threads have reached this inst count")
 167     max_insts_any_thread = Param.Counter(0,
 168         "terminate when any thread reaches this inst count")
 169     simpoint_start_insts = VectorParam.Counter([],
 170         "starting instruction counts of simpoints")
 171     progress_interval = Param.Frequency('0Hz',
 172         "frequency to print out the progress message")
 173
 174     switched_out = Param.Bool(False,
 175         "Leave the CPU switched out after startup (used when switching " \
 176         "between CPU models)")
 177
 178     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 179
 180     icache_port = MasterPort("Instruction Port")
 181     dcache_port = MasterPort("Data Port")
 182     _cached_ports = ['icache_port', 'dcache_port']
 183
 184     if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
 185         _cached_ports += ["itb.walker.port", "dtb.walker.port"]
 186
 187     _uncached_slave_ports = []
 188     _uncached_master_ports = []
 189     if buildEnv['TARGET_ISA'] == 'x86':
 190         _uncached_slave_ports += ["interrupts[0].pio",
 191                                   "interrupts[0].int_slave"]
 192         _uncached_master_ports += ["interrupts[0].int_master"]
 193
 194     def createInterruptController(self):
 195         self.interrupts = [ArchInterrupts() for i in range(self.numThreads)]
 196
 197     def connectCachedPorts(self, bus):
 198         for p in self._cached_ports:
 199             exec('self.%s = bus.slave' % p)
 200
 201     def connectUncachedPorts(self, bus):
 202         for p in self._uncached_slave_ports:
 203             exec('self.%s = bus.master' % p)
 204         for p in self._uncached_master_ports:
 205             exec('self.%s = bus.slave' % p)
 206
 207     def connectAllPorts(self, cached_bus, uncached_bus = None):
 208         self.connectCachedPorts(cached_bus)
 209         if not uncached_bus:
 210             uncached_bus = cached_bus
 211         self.connectUncachedPorts(uncached_bus)
 212
 213     def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
 214         self.icache = ic
 215         self.dcache = dc
 216         self.icache_port = ic.cpu_side
 217         self.dcache_port = dc.cpu_side
 218         self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
 219         if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
 220             if iwc and dwc:
 221                 self.itb_walker_cache = iwc
 222                 self.dtb_walker_cache = dwc
 223                 self.itb.walker.port = iwc.cpu_side
 224                 self.dtb.walker.port = dwc.cpu_side
 225                 self._cached_ports += ["itb_walker_cache.mem_side", \
 226                                        "dtb_walker_cache.mem_side"]
 227             else:
 228                 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
 229
 230             # Checker doesn't need its own tlb caches because it does
 231             # functional accesses only
 232             if self.checker != NULL:
 233                 self._cached_ports += ["checker.itb.walker.port", \
 234                                        "checker.dtb.walker.port"]
 235
 236     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None,
 237                                   xbar=None):
 238         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
 239         self.toL2Bus = xbar if xbar else L2XBar()
 240         self.connectCachedPorts(self.toL2Bus)
 241         self.l2cache = l2c
 242         self.toL2Bus.master = self.l2cache.cpu_side
 243         self._cached_ports = ['l2cache.mem_side']
 244
 245     def createThreads(self):
 246         # If no ISAs have been created, assume that the user wants the
 247         # default ISA.
 248         if len(self.isa) == 0:
 249             self.isa = [ ArchISA() for i in range(self.numThreads) ]
 250         else:
 251             if len(self.isa) != int(self.numThreads):
 252                 raise RuntimeError("Number of ISA instances doesn't "
 253                                    "match thread count")
 254         if self.checker != NULL:
 255             self.checker.createThreads()
 256
 257     def addCheckerCpu(self):
 258         pass
 259
 260     def createPhandleKey(self, thread):
 261         # This method creates a unique key for this cpu as a function of a
 262         # certain thread
 263         return 'CPU-%d-%d-%d' % (self.socket_id, self.cpu_id, thread)
 264
 265     #Generate simple CPU Device Tree structure
 266     def generateDeviceTree(self, state):
 267         """Generate cpu nodes for each thread and the corresponding part of the
 268         cpu-map node. Note that this implementation does not support clusters
 269         of clusters. Note that GEM5 is not compatible with the official way of
 270         numbering cores as defined in the Device Tree documentation. Where the
 271         cpu_id needs to reset to 0 for each cluster by specification, GEM5
 272         expects the cpu_id to be globally unique and incremental. This
 273         generated node adheres the GEM5 way of doing things."""
 274         if bool(self.switched_out):
 275             return
 276
 277         cpus_node = FdtNode('cpus')
 278         cpus_node.append(state.CPUCellsProperty())
 279         #Special size override of 0
 280         cpus_node.append(FdtPropertyWords('#size-cells', [0]))
 281
 282         # Generate cpu nodes
 283         for i in range(int(self.numThreads)):
 284             reg = (int(self.socket_id)<<8) + int(self.cpu_id) + i
 285             node = FdtNode("cpu@%x" % reg)
 286             node.append(FdtPropertyStrings("device_type", "cpu"))
 287             node.appendCompatible(["gem5,arm-cpu"])
 288             node.append(FdtPropertyWords("reg", state.CPUAddrCells(reg)))
 289             platform, found = self.system.unproxy(self).find_any(Platform)
 290             if found:
 291                 platform.annotateCpuDeviceNode(node, state)
 292             else:
 293                 warn("Platform not found for device tree generation; " \
 294                      "system or multiple CPUs may not start")
 295
 296             freq = int(self.clk_domain.unproxy(self).clock[0].frequency)
 297             node.append(FdtPropertyWords("clock-frequency", freq))
 298
 299             # Unique key for this CPU
 300             phandle_key = self.createPhandleKey(i)
 301             node.appendPhandle(phandle_key)
 302             cpus_node.append(node)
 303
 304         yield cpus_node