1 # Copyright (c) 2005-2008 The Regents of The University of Michigan
2 # Copyright (c) 2011 Regents of the University of California
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 # Authors: Nathan Binkert
33 from m5
.defines
import buildEnv
34 from m5
.params
import *
35 from m5
.proxy
import *
38 from InstTracer
import InstTracer
39 from ExeTracer
import ExeTracer
40 from MemObject
import MemObject
42 default_tracer
= ExeTracer()
44 if buildEnv
['TARGET_ISA'] == 'alpha':
45 from AlphaTLB
import AlphaDTB
, AlphaITB
46 from AlphaInterrupts
import AlphaInterrupts
47 elif buildEnv
['TARGET_ISA'] == 'sparc':
48 from SparcTLB
import SparcTLB
49 from SparcInterrupts
import SparcInterrupts
50 elif buildEnv
['TARGET_ISA'] == 'x86':
51 from X86TLB
import X86TLB
52 from X86LocalApic
import X86LocalApic
53 elif buildEnv
['TARGET_ISA'] == 'mips':
54 from MipsTLB
import MipsTLB
55 from MipsInterrupts
import MipsInterrupts
56 elif buildEnv
['TARGET_ISA'] == 'arm':
57 from ArmTLB
import ArmTLB
58 from ArmInterrupts
import ArmInterrupts
59 elif buildEnv
['TARGET_ISA'] == 'power':
60 from PowerTLB
import PowerTLB
61 from PowerInterrupts
import PowerInterrupts
63 class BaseCPU(MemObject
):
67 system
= Param
.System(Parent
.any
, "system object")
68 cpu_id
= Param
.Int(-1, "CPU identifier")
69 numThreads
= Param
.Unsigned(1, "number of HW thread contexts")
71 function_trace
= Param
.Bool(False, "Enable function trace")
72 function_trace_start
= Param
.Tick(0, "Cycle to start function trace")
74 checker
= Param
.BaseCPU(NULL
, "checker CPU")
76 do_checkpoint_insts
= Param
.Bool(True,
77 "enable checkpoint pseudo instructions")
78 do_statistics_insts
= Param
.Bool(True,
79 "enable statistics pseudo instructions")
81 profile
= Param
.Latency('0ns', "trace the kernel stack")
82 do_quiesce
= Param
.Bool(True, "enable quiesce instructions")
84 workload
= VectorParam
.Process([], "processes to run")
86 if buildEnv
['TARGET_ISA'] == 'sparc':
87 dtb
= Param
.SparcTLB(SparcTLB(), "Data TLB")
88 itb
= Param
.SparcTLB(SparcTLB(), "Instruction TLB")
89 interrupts
= Param
.SparcInterrupts(
90 SparcInterrupts(), "Interrupt Controller")
91 elif buildEnv
['TARGET_ISA'] == 'alpha':
92 dtb
= Param
.AlphaTLB(AlphaDTB(), "Data TLB")
93 itb
= Param
.AlphaTLB(AlphaITB(), "Instruction TLB")
94 interrupts
= Param
.AlphaInterrupts(
95 AlphaInterrupts(), "Interrupt Controller")
96 elif buildEnv
['TARGET_ISA'] == 'x86':
97 dtb
= Param
.X86TLB(X86TLB(), "Data TLB")
98 itb
= Param
.X86TLB(X86TLB(), "Instruction TLB")
99 _localApic
= X86LocalApic(pio_addr
=0x2000000000000000)
100 interrupts
= Param
.X86LocalApic(_localApic
, "Interrupt Controller")
101 elif buildEnv
['TARGET_ISA'] == 'mips':
102 dtb
= Param
.MipsTLB(MipsTLB(), "Data TLB")
103 itb
= Param
.MipsTLB(MipsTLB(), "Instruction TLB")
104 interrupts
= Param
.MipsInterrupts(
105 MipsInterrupts(), "Interrupt Controller")
106 elif buildEnv
['TARGET_ISA'] == 'arm':
107 dtb
= Param
.ArmTLB(ArmTLB(), "Data TLB")
108 itb
= Param
.ArmTLB(ArmTLB(), "Instruction TLB")
109 interrupts
= Param
.ArmInterrupts(
110 ArmInterrupts(), "Interrupt Controller")
111 elif buildEnv
['TARGET_ISA'] == 'power':
112 UnifiedTLB
= Param
.Bool(True, "Is this a Unified TLB?")
113 dtb
= Param
.PowerTLB(PowerTLB(), "Data TLB")
114 itb
= Param
.PowerTLB(PowerTLB(), "Instruction TLB")
115 interrupts
= Param
.PowerInterrupts(
116 PowerInterrupts(), "Interrupt Controller")
118 print "Don't know what TLB to use for ISA %s" % \
119 buildEnv
['TARGET_ISA']
122 max_insts_all_threads
= Param
.Counter(0,
123 "terminate when all threads have reached this inst count")
124 max_insts_any_thread
= Param
.Counter(0,
125 "terminate when any thread reaches this inst count")
126 max_loads_all_threads
= Param
.Counter(0,
127 "terminate when all threads have reached this load count")
128 max_loads_any_thread
= Param
.Counter(0,
129 "terminate when any thread reaches this load count")
130 progress_interval
= Param
.Tick(0,
131 "interval to print out the progress message")
133 defer_registration
= Param
.Bool(False,
134 "defer registration with system (for sampling)")
136 clock
= Param
.Clock('1t', "clock speed")
137 phase
= Param
.Latency('0ns', "clock phase")
139 tracer
= Param
.InstTracer(default_tracer
, "Instruction tracer")
142 if buildEnv
['TARGET_ISA'] in ['x86', 'arm']:
143 _cached_ports
= ["itb.walker.port", "dtb.walker.port"]
146 if buildEnv
['TARGET_ISA'] == 'x86':
147 _uncached_ports
= ["interrupts.pio", "interrupts.int_port"]
149 def connectCachedPorts(self
, bus
):
150 for p
in self
._cached
_ports
:
151 exec('self.%s = bus.port' % p
)
153 def connectUncachedPorts(self
, bus
):
154 for p
in self
._uncached
_ports
:
155 exec('self.%s = bus.port' % p
)
157 def connectAllPorts(self
, cached_bus
, uncached_bus
= None):
158 self
.connectCachedPorts(cached_bus
)
160 uncached_bus
= cached_bus
161 self
.connectUncachedPorts(uncached_bus
)
163 def addPrivateSplitL1Caches(self
, ic
, dc
, iwc
= None, dwc
= None):
164 assert(len(self
._cached
_ports
) < 7)
167 self
.icache_port
= ic
.cpu_side
168 self
.dcache_port
= dc
.cpu_side
169 self
._cached
_ports
= ['icache.mem_side', 'dcache.mem_side']
170 if buildEnv
['TARGET_ISA'] in ['x86', 'arm']:
172 self
.itb_walker_cache
= iwc
173 self
.dtb_walker_cache
= dwc
174 self
.itb
.walker
.port
= iwc
.cpu_side
175 self
.dtb
.walker
.port
= dwc
.cpu_side
176 self
._cached
_ports
+= ["itb_walker_cache.mem_side", \
177 "dtb_walker_cache.mem_side"]
179 self
._cached
_ports
+= ["itb.walker.port", "dtb.walker.port"]
181 def addTwoLevelCacheHierarchy(self
, ic
, dc
, l2c
, iwc
= None, dwc
= None):
182 self
.addPrivateSplitL1Caches(ic
, dc
, iwc
, dwc
)
184 self
.connectCachedPorts(self
.toL2Bus
)
186 self
.l2cache
.cpu_side
= self
.toL2Bus
.port
187 self
._cached
_ports
= ['l2cache.mem_side']