src/cpu/BaseCPU.py

   1 # Copyright (c) 2005-2008 The Regents of The University of Michigan
   2 # Copyright (c) 2011 Regents of the University of California
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Nathan Binkert
  29 #          Rick Strong
  30
  31 import sys
  32
  33 from m5.defines import buildEnv
  34 from m5.params import *
  35 from m5.proxy import *
  36
  37 from Bus import Bus
  38 from InstTracer import InstTracer
  39 from ExeTracer import ExeTracer
  40 from MemObject import MemObject
  41
  42 default_tracer = ExeTracer()
  43
  44 if buildEnv['TARGET_ISA'] == 'alpha':
  45     from AlphaTLB import AlphaDTB, AlphaITB
  46     if buildEnv['FULL_SYSTEM']:
  47         from AlphaInterrupts import AlphaInterrupts
  48 elif buildEnv['TARGET_ISA'] == 'sparc':
  49     from SparcTLB import SparcTLB
  50     if buildEnv['FULL_SYSTEM']:
  51         from SparcInterrupts import SparcInterrupts
  52 elif buildEnv['TARGET_ISA'] == 'x86':
  53     from X86TLB import X86TLB
  54     if buildEnv['FULL_SYSTEM']:
  55         from X86LocalApic import X86LocalApic
  56 elif buildEnv['TARGET_ISA'] == 'mips':
  57     from MipsTLB import MipsTLB
  58     if buildEnv['FULL_SYSTEM']:
  59         from MipsInterrupts import MipsInterrupts
  60 elif buildEnv['TARGET_ISA'] == 'arm':
  61     from ArmTLB import ArmTLB
  62     if buildEnv['FULL_SYSTEM']:
  63         from ArmInterrupts import ArmInterrupts
  64 elif buildEnv['TARGET_ISA'] == 'power':
  65     from PowerTLB import PowerTLB
  66     if buildEnv['FULL_SYSTEM']:
  67         from PowerInterrupts import PowerInterrupts
  68
  69 class BaseCPU(MemObject):
  70     type = 'BaseCPU'
  71     abstract = True
  72
  73     system = Param.System(Parent.any, "system object")
  74     cpu_id = Param.Int(-1, "CPU identifier")
  75     numThreads = Param.Unsigned(1, "number of HW thread contexts")
  76
  77     function_trace = Param.Bool(False, "Enable function trace")
  78     function_trace_start = Param.Tick(0, "Cycle to start function trace")
  79
  80     checker = Param.BaseCPU(NULL, "checker CPU")
  81
  82     do_checkpoint_insts = Param.Bool(True,
  83         "enable checkpoint pseudo instructions")
  84     do_statistics_insts = Param.Bool(True,
  85         "enable statistics pseudo instructions")
  86
  87     if buildEnv['FULL_SYSTEM']:
  88         profile = Param.Latency('0ns', "trace the kernel stack")
  89         do_quiesce = Param.Bool(True, "enable quiesce instructions")
  90     else:
  91         workload = VectorParam.Process("processes to run")
  92
  93     if buildEnv['TARGET_ISA'] == 'sparc':
  94         dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
  95         itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
  96         if buildEnv['FULL_SYSTEM']:
  97             interrupts = Param.SparcInterrupts(
  98                 SparcInterrupts(), "Interrupt Controller")
  99     elif buildEnv['TARGET_ISA'] == 'alpha':
 100         dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
 101         itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
 102         if buildEnv['FULL_SYSTEM']:
 103             interrupts = Param.AlphaInterrupts(
 104                 AlphaInterrupts(), "Interrupt Controller")
 105     elif buildEnv['TARGET_ISA'] == 'x86':
 106         dtb = Param.X86TLB(X86TLB(), "Data TLB")
 107         itb = Param.X86TLB(X86TLB(), "Instruction TLB")
 108         if buildEnv['FULL_SYSTEM']:
 109             _localApic = X86LocalApic(pio_addr=0x2000000000000000)
 110             interrupts = \
 111                 Param.X86LocalApic(_localApic, "Interrupt Controller")
 112     elif buildEnv['TARGET_ISA'] == 'mips':
 113         dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
 114         itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
 115         if buildEnv['FULL_SYSTEM']:
 116             interrupts = Param.MipsInterrupts(
 117                     MipsInterrupts(), "Interrupt Controller")
 118     elif buildEnv['TARGET_ISA'] == 'arm':
 119         dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
 120         itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
 121         if buildEnv['FULL_SYSTEM']:
 122             interrupts = Param.ArmInterrupts(
 123                     ArmInterrupts(), "Interrupt Controller")
 124     elif buildEnv['TARGET_ISA'] == 'power':
 125         UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
 126         dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
 127         itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
 128         if buildEnv['FULL_SYSTEM']:
 129             interrupts = Param.PowerInterrupts(
 130                     PowerInterrupts(), "Interrupt Controller")
 131     else:
 132         print "Don't know what TLB to use for ISA %s" % \
 133             buildEnv['TARGET_ISA']
 134         sys.exit(1)
 135
 136     max_insts_all_threads = Param.Counter(0,
 137         "terminate when all threads have reached this inst count")
 138     max_insts_any_thread = Param.Counter(0,
 139         "terminate when any thread reaches this inst count")
 140     max_loads_all_threads = Param.Counter(0,
 141         "terminate when all threads have reached this load count")
 142     max_loads_any_thread = Param.Counter(0,
 143         "terminate when any thread reaches this load count")
 144     progress_interval = Param.Tick(0,
 145         "interval to print out the progress message")
 146
 147     defer_registration = Param.Bool(False,
 148         "defer registration with system (for sampling)")
 149
 150     clock = Param.Clock('1t', "clock speed")
 151     phase = Param.Latency('0ns', "clock phase")
 152
 153     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 154
 155     _cached_ports = []
 156     if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
 157         _cached_ports = ["itb.walker.port", "dtb.walker.port"]
 158
 159     _uncached_ports = []
 160     if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
 161         _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
 162
 163     def connectCachedPorts(self, bus):
 164         for p in self._cached_ports:
 165             exec('self.%s = bus.port' % p)
 166
 167     def connectUncachedPorts(self, bus):
 168         for p in self._uncached_ports:
 169             exec('self.%s = bus.port' % p)
 170
 171     def connectAllPorts(self, cached_bus, uncached_bus = None):
 172         self.connectCachedPorts(cached_bus)
 173         if not uncached_bus:
 174             uncached_bus = cached_bus
 175         self.connectUncachedPorts(uncached_bus)
 176
 177     def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
 178         assert(len(self._cached_ports) < 7)
 179         self.icache = ic
 180         self.dcache = dc
 181         self.icache_port = ic.cpu_side
 182         self.dcache_port = dc.cpu_side
 183         self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
 184         if buildEnv['FULL_SYSTEM']:
 185             if buildEnv['TARGET_ISA'] == 'x86':
 186                 self.itb_walker_cache = iwc
 187                 self.dtb_walker_cache = dwc
 188                 self.itb.walker.port = iwc.cpu_side
 189                 self.dtb.walker.port = dwc.cpu_side
 190                 self._cached_ports += ["itb_walker_cache.mem_side", \
 191                                        "dtb_walker_cache.mem_side"]
 192             elif buildEnv['TARGET_ISA'] == 'arm':
 193                 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
 194
 195     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
 196         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
 197         self.toL2Bus = Bus()
 198         self.connectCachedPorts(self.toL2Bus)
 199         self.l2cache = l2c
 200         self.l2cache.cpu_side = self.toL2Bus.port
 201         self._cached_ports = ['l2cache.mem_side']