src/cpu/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2020 ARM Limited
   4 # All rights reserved.
   5 #
   6 # The license below extends only to copyright in the software and shall
   7 # not be construed as granting a license to any other intellectual
   8 # property including but not limited to intellectual property relating
   9 # to a hardware implementation of the functionality of the software
  10 # licensed hereunder.  You may use the software subject to the license
  11 # terms below provided that you ensure that this notice is replicated
  12 # unmodified and in its entirety in all distributions of the software,
  13 # modified or unmodified, in source code or in binary form.
  14 #
  15 # Copyright (c) 2006 The Regents of The University of Michigan
  16 # All rights reserved.
  17 #
  18 # Redistribution and use in source and binary forms, with or without
  19 # modification, are permitted provided that the following conditions are
  20 # met: redistributions of source code must retain the above copyright
  21 # notice, this list of conditions and the following disclaimer;
  22 # redistributions in binary form must reproduce the above copyright
  23 # notice, this list of conditions and the following disclaimer in the
  24 # documentation and/or other materials provided with the distribution;
  25 # neither the name of the copyright holders nor the names of its
  26 # contributors may be used to endorse or promote products derived from
  27 # this software without specific prior written permission.
  28 #
  29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40
  41 Import('*')
  42
  43 DebugFlag('Activity')
  44 DebugFlag('Commit')
  45 DebugFlag('Context')
  46 DebugFlag('Decode')
  47 DebugFlag('DynInst')
  48 DebugFlag('ExecEnable',
  49         'Filter: Enable exec tracing (no tracing without this)')
  50 DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
  51 DebugFlag('ExecEffAddr', 'Format: Include effective address')
  52 DebugFlag('ExecFaulting', 'Trace faulting instructions')
  53 DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
  54 DebugFlag('ExecOpClass', 'Format: Include operand class')
  55 DebugFlag('ExecRegDelta')
  56 DebugFlag('ExecResult', 'Format: Include results from execution')
  57 DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
  58 DebugFlag('ExecThread', 'Format: Include thread ID in trace')
  59 DebugFlag('ExecMicro', 'Filter: Include microops')
  60 DebugFlag('ExecMacro', 'Filter: Include macroops')
  61 DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
  62 DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
  63 DebugFlag('ExecAsid', 'Format: Include ASID in trace')
  64 DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
  65 DebugFlag('Fetch')
  66 DebugFlag('HtmCpu', 'Hardware Transactional Memory (CPU side)')
  67 DebugFlag('IntrControl')
  68 DebugFlag('O3PipeView')
  69 DebugFlag('PCEvent')
  70 DebugFlag('Quiesce')
  71 DebugFlag('Mwait')
  72
  73 CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
  74     'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
  75     'ExecResult', 'ExecSymbol', 'ExecThread',
  76     'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
  77     'ExecAsid', 'ExecFlags' ])
  78 CompoundFlag('Exec', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
  79     'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecMacro',
  80     'ExecFaulting', 'ExecUser', 'ExecKernel' ])
  81 CompoundFlag('ExecNoTicks', [ 'Exec', 'FmtTicksOff' ])
  82
  83 Source('pc_event.cc')
  84
  85 if env['TARGET_ISA'] == 'null':
  86     SimObject('IntrControl.py')
  87     Source('intr_control_noisa.cc')
  88     Return()
  89
  90 # Only build the protocol buffer instructions tracer if we have protobuf support
  91 if env['HAVE_PROTOBUF'] and env['TARGET_ISA'] != 'x86':
  92     SimObject('InstPBTrace.py')
  93     Source('inst_pb_trace.cc')
  94
  95 SimObject('CheckerCPU.py')
  96
  97 SimObject('BaseCPU.py')
  98 SimObject('CPUTracers.py')
  99 SimObject('FuncUnit.py')
 100 SimObject('IntrControl.py')
 101 SimObject('TimingExpr.py')
 102
 103 Source('activity.cc')
 104 Source('base.cc')
 105 Source('exetrace.cc')
 106 Source('exec_context.cc')
 107 Source('func_unit.cc')
 108 Source('inteltrace.cc')
 109 Source('intr_control.cc')
 110 Source('nativetrace.cc')
 111 Source('profile.cc')
 112 Source('reg_class.cc')
 113 Source('static_inst.cc')
 114 Source('simple_thread.cc')
 115 Source('thread_context.cc')
 116 Source('thread_state.cc')
 117 Source('timing_expr.cc')
 118
 119 SimObject('DummyChecker.py')
 120 SimObject('StaticInstFlags.py')
 121 Source('checker/cpu.cc')
 122 Source('dummy_checker.cc')
 123 DebugFlag('Checker')