3 # Copyright (c) 2006 The Regents of The University of Michigan
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 # Authors: Steve Reinhardt
33 #################################################################
35 # Generate StaticInst execute() method signatures.
37 # There must be one signature for each CPU model compiled in.
38 # Since the set of compiled-in models is flexible, we generate a
39 # header containing the appropriate set of signatures on the fly.
41 #################################################################
43 # CPU model-specific data is contained in cpu_models.py
44 # Convert to SCons File node to get path handling
45 models_db = File('cpu_models.py')
46 # slurp in contents of file
47 execfile(models_db.srcnode().abspath)
49 # Template for execute() signature.
50 exec_sig_template = '''
51 virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
52 virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
53 { panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
54 virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
55 Trace::InstRecord *traceData) const
56 { panic("completeAcc not defined!"); M5_DUMMY_RETURN };
57 virtual int memAccSize(%(type)s *xc)
58 { panic("memAccSize not defined!"); M5_DUMMY_RETURN };
61 mem_ini_sig_template = '''
62 virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
65 mem_comp_sig_template = '''
66 virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
69 # Generate a temporary CPU list, including the CheckerCPU if
70 # it's enabled. This isn't used for anything else other than StaticInst
72 temp_cpu_list = env['CPU_MODELS'][:]
74 if env['USE_CHECKER']:
75 temp_cpu_list.append('CheckerCPU')
76 SimObject('CheckerCPU.py')
79 def gen_cpu_exec_signatures(target, source, env):
80 f = open(str(target[0]), 'w')
82 #ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
83 #define __CPU_STATIC_INST_EXEC_SIGS_HH__
85 for cpu in temp_cpu_list:
86 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
87 print >> f, exec_sig_template % { 'type' : xc_type }
89 #endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
92 # Generate string that gets printed when header is rebuilt
93 def gen_sigs_string(target, source, env):
94 return "Generating static_inst_exec_sigs.hh: " \
95 + ', '.join(temp_cpu_list)
97 # Add command to generate header to environment.
98 env.Command('static_inst_exec_sigs.hh', models_db,
99 Action(gen_cpu_exec_signatures, gen_sigs_string,
100 varlist = temp_cpu_list))
102 env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
103 env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
105 # List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True
106 # and one of these are not being used.
107 CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
109 SimObject('BaseCPU.py')
110 SimObject('FuncUnit.py')
111 SimObject('ExeTracer.py')
112 SimObject('IntelTrace.py')
114 Source('activity.cc')
116 Source('cpuevent.cc')
117 Source('exetrace.cc')
118 Source('func_unit.cc')
119 Source('inteltrace.cc')
120 Source('pc_event.cc')
121 Source('quiesce_event.cc')
122 Source('static_inst.cc')
123 Source('simple_thread.cc')
124 Source('thread_context.cc')
125 Source('thread_state.cc')
127 if env['FULL_SYSTEM']:
128 SimObject('IntrControl.py')
130 Source('intr_control.cc')
133 if env['TARGET_ISA'] == 'sparc':
134 SimObject('LegionTrace.py')
135 Source('legiontrace.cc')
137 if env['TARGET_ISA'] == 'x86':
138 SimObject('NativeTrace.py')
139 Source('nativetrace.cc')
141 if env['USE_CHECKER']:
142 Source('checker/cpu.cc')
144 checker_supports = False
145 for i in CheckerSupportedCPUList:
146 if i in env['CPU_MODELS']:
147 checker_supports = True
148 if not checker_supports:
149 print "Checker only supports CPU models",
150 for i in CheckerSupportedCPUList:
152 print ", please set USE_CHECKER=False or use one of those CPU models"
155 TraceFlag('Activity')
160 TraceFlag('ExecEnable')
161 TraceFlag('ExecCPSeq')
162 TraceFlag('ExecEffAddr')
163 TraceFlag('ExecFetchSeq')
164 TraceFlag('ExecOpClass')
165 TraceFlag('ExecRegDelta')
166 TraceFlag('ExecResult')
167 TraceFlag('ExecSpeculative')
168 TraceFlag('ExecSymbol')
169 TraceFlag('ExecThread')
170 TraceFlag('ExecTicks')
171 TraceFlag('ExecMicro')
172 TraceFlag('ExecMacro')
174 TraceFlag('IntrControl')
178 CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
179 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro' ])
180 CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
181 'ExecEffAddr', 'ExecResult', 'ExecMicro' ])