34bad132c3edeb0bd9eeddfc5c4e3146e43cc2b4
[gem5.git] / src / cpu / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2006 The Regents of The University of Michigan
4 # All rights reserved.
5 #
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
16 #
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #
29 # Authors: Steve Reinhardt
30
31 import os
32 import os.path
33
34 # Import build environment variable from SConstruct.
35 Import('env')
36
37 #################################################################
38 #
39 # Generate StaticInst execute() method signatures.
40 #
41 # There must be one signature for each CPU model compiled in.
42 # Since the set of compiled-in models is flexible, we generate a
43 # header containing the appropriate set of signatures on the fly.
44 #
45 #################################################################
46
47 # CPU model-specific data is contained in cpu_models.py
48 # Convert to SCons File node to get path handling
49 models_db = File('cpu_models.py')
50 # slurp in contents of file
51 execfile(models_db.srcnode().abspath)
52
53 # Template for execute() signature.
54 exec_sig_template = '''
55 virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
56 virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const
57 { panic("initiateAcc not defined!"); };
58 virtual Fault completeAcc(Packet *pkt, %s *xc,
59 Trace::InstRecord *traceData) const
60 { panic("completeAcc not defined!"); };
61 '''
62
63 mem_ini_sig_template = '''
64 virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); };
65 '''
66
67 mem_comp_sig_template = '''
68 virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; };
69 '''
70
71 # Generate header.
72 def gen_cpu_exec_signatures(target, source, env):
73 f = open(str(target[0]), 'w')
74 print >> f, '''
75 #ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
76 #define __CPU_STATIC_INST_EXEC_SIGS_HH__
77 '''
78 for cpu in env['CPU_MODELS']:
79 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
80 print >> f, exec_sig_template % (xc_type, xc_type, xc_type)
81 print >> f, '''
82 #endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
83 '''
84
85 # Generate string that gets printed when header is rebuilt
86 def gen_sigs_string(target, source, env):
87 return "Generating static_inst_exec_sigs.hh: " \
88 + ', '.join(env['CPU_MODELS'])
89
90 # Add command to generate header to environment.
91 env.Command('static_inst_exec_sigs.hh', models_db,
92 Action(gen_cpu_exec_signatures, gen_sigs_string,
93 varlist = ['CPU_MODELS']))
94
95 #################################################################
96 #
97 # Include CPU-model-specific files based on set of models
98 # specified in CPU_MODELS build option.
99 #
100 #################################################################
101
102 sources = []
103
104 need_simple_base = False
105 if 'AtomicSimpleCPU' in env['CPU_MODELS']:
106 need_simple_base = True
107 sources += Split('simple/atomic.cc')
108
109 if 'TimingSimpleCPU' in env['CPU_MODELS']:
110 need_simple_base = True
111 sources += Split('simple/timing.cc')
112
113 if need_simple_base:
114 sources += Split('simple/base.cc')
115
116 if 'FastCPU' in env['CPU_MODELS']:
117 sources += Split('fast/cpu.cc')
118
119 if 'AlphaFullCPU' in env['CPU_MODELS']:
120 sources += Split('''
121 base_dyn_inst.cc
122 o3/2bit_local_pred.cc
123 o3/alpha_dyn_inst.cc
124 o3/alpha_cpu.cc
125 o3/alpha_cpu_builder.cc
126 o3/bpred_unit.cc
127 o3/btb.cc
128 o3/commit.cc
129 o3/decode.cc
130 o3/fetch.cc
131 o3/free_list.cc
132 o3/fu_pool.cc
133 o3/cpu.cc
134 o3/iew.cc
135 o3/inst_queue.cc
136 o3/lsq_unit.cc
137 o3/lsq.cc
138 o3/mem_dep_unit.cc
139 o3/ras.cc
140 o3/rename.cc
141 o3/rename_map.cc
142 o3/rob.cc
143 o3/scoreboard.cc
144 o3/store_set.cc
145 o3/tournament_pred.cc
146 ''')
147
148 if 'OzoneSimpleCPU' in env['CPU_MODELS']:
149 sources += Split('''
150 ozone/cpu.cc
151 ozone/cpu_builder.cc
152 ozone/dyn_inst.cc
153 ozone/front_end.cc
154 ozone/inorder_back_end.cc
155 ozone/inst_queue.cc
156 ozone/rename_table.cc
157 ''')
158
159 if 'OzoneCPU' in env['CPU_MODELS']:
160 sources += Split('''
161 ozone/lsq_unit.cc
162 ozone/lw_back_end.cc
163 ozone/lw_lsq.cc
164 ''')
165
166 if 'CheckerCPU' in env['CPU_MODELS']:
167 sources += Split('''
168 checker/cpu.cc
169 checker/o3_cpu_builder.cc
170 ''')
171
172 # FullCPU sources are included from m5/SConscript since they're not
173 # below this point in the file hierarchy.
174
175 # Convert file names to SCons File objects. This takes care of the
176 # path relative to the top of the directory tree.
177 sources = [File(s) for s in sources]
178
179 Return('sources')
180