src/cpu/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2006 The Regents of The University of Michigan
   4 # All rights reserved.
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are
   8 # met: redistributions of source code must retain the above copyright
   9 # notice, this list of conditions and the following disclaimer;
  10 # redistributions in binary form must reproduce the above copyright
  11 # notice, this list of conditions and the following disclaimer in the
  12 # documentation and/or other materials provided with the distribution;
  13 # neither the name of the copyright holders nor the names of its
  14 # contributors may be used to endorse or promote products derived from
  15 # this software without specific prior written permission.
  16 #
  17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 #
  29 # Authors: Steve Reinhardt
  30
  31 Import('*')
  32
  33 if env['TARGET_ISA'] == 'null':
  34     SimObject('IntrControl.py')
  35     Source('intr_control_noisa.cc')
  36     Return()
  37
  38 # Only build the protocol buffer instructions tracer if we have protobuf support
  39 if env['HAVE_PROTOBUF'] and env['TARGET_ISA'] != 'x86':
  40     SimObject('InstPBTrace.py')
  41     Source('inst_pb_trace.cc')
  42
  43 SimObject('CheckerCPU.py')
  44
  45 SimObject('BaseCPU.py')
  46 SimObject('CPUTracers.py')
  47 SimObject('FuncUnit.py')
  48 SimObject('IntrControl.py')
  49 SimObject('TimingExpr.py')
  50
  51 Source('activity.cc')
  52 Source('base.cc')
  53 Source('cpuevent.cc')
  54 Source('exetrace.cc')
  55 Source('exec_context.cc')
  56 Source('func_unit.cc')
  57 Source('inteltrace.cc')
  58 Source('intr_control.cc')
  59 Source('nativetrace.cc')
  60 Source('pc_event.cc')
  61 Source('profile.cc')
  62 Source('quiesce_event.cc')
  63 Source('reg_class.cc')
  64 Source('static_inst.cc')
  65 Source('simple_thread.cc')
  66 Source('thread_context.cc')
  67 Source('thread_state.cc')
  68 Source('timing_expr.cc')
  69
  70 SimObject('DummyChecker.py')
  71 SimObject('StaticInstFlags.py')
  72 Source('checker/cpu.cc')
  73 Source('dummy_checker.cc')
  74 DebugFlag('Checker')
  75
  76 DebugFlag('Activity')
  77 DebugFlag('Commit')
  78 DebugFlag('Context')
  79 DebugFlag('Decode')
  80 DebugFlag('DynInst')
  81 DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
  82 DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
  83 DebugFlag('ExecEffAddr', 'Format: Include effective address')
  84 DebugFlag('ExecFaulting', 'Trace faulting instructions')
  85 DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
  86 DebugFlag('ExecOpClass', 'Format: Include operand class')
  87 DebugFlag('ExecRegDelta')
  88 DebugFlag('ExecResult', 'Format: Include results from execution')
  89 DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
  90 DebugFlag('ExecThread', 'Format: Include thread ID in trace')
  91 DebugFlag('ExecTicks', 'Format: Include tick count')
  92 DebugFlag('ExecMicro', 'Filter: Include microops')
  93 DebugFlag('ExecMacro', 'Filter: Include macroops')
  94 DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
  95 DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
  96 DebugFlag('ExecAsid', 'Format: Include ASID in trace')
  97 DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
  98 DebugFlag('Fetch')
  99 DebugFlag('IntrControl')
 100 DebugFlag('O3PipeView')
 101 DebugFlag('PCEvent')
 102 DebugFlag('Quiesce')
 103 DebugFlag('Mwait')
 104
 105 CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
 106     'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
 107     'ExecResult', 'ExecSymbol', 'ExecThread',
 108     'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
 109     'ExecAsid', 'ExecFlags' ])
 110 CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
 111     'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecMacro',
 112     'ExecFaulting', 'ExecUser', 'ExecKernel' ])
 113 CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
 114     'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecMacro', 'ExecFaulting',
 115     'ExecUser', 'ExecKernel' ])