src/cpu/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2006 The Regents of The University of Michigan
   4 # All rights reserved.
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are
   8 # met: redistributions of source code must retain the above copyright
   9 # notice, this list of conditions and the following disclaimer;
  10 # redistributions in binary form must reproduce the above copyright
  11 # notice, this list of conditions and the following disclaimer in the
  12 # documentation and/or other materials provided with the distribution;
  13 # neither the name of the copyright holders nor the names of its
  14 # contributors may be used to endorse or promote products derived from
  15 # this software without specific prior written permission.
  16 #
  17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 #
  29 # Authors: Steve Reinhardt
  30
  31 Import('*')
  32
  33 #################################################################
  34 #
  35 # Generate StaticInst execute() method signatures.
  36 #
  37 # There must be one signature for each CPU model compiled in.
  38 # Since the set of compiled-in models is flexible, we generate a
  39 # header containing the appropriate set of signatures on the fly.
  40 #
  41 #################################################################
  42
  43 # CPU model-specific data is contained in cpu_models.py
  44 # Convert to SCons File node to get path handling
  45 models_db = File('cpu_models.py')
  46 # slurp in contents of file
  47 execfile(models_db.srcnode().abspath)
  48
  49 # Template for execute() signature.
  50 exec_sig_template = '''
  51 virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
  52 virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const
  53 { panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
  54 virtual Fault completeAcc(Packet *pkt, %s *xc,
  55                           Trace::InstRecord *traceData) const
  56 { panic("completeAcc not defined!"); M5_DUMMY_RETURN };
  57 '''
  58
  59 mem_ini_sig_template = '''
  60 virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
  61 '''
  62
  63 mem_comp_sig_template = '''
  64 virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
  65 '''
  66
  67 # Generate a temporary CPU list, including the CheckerCPU if
  68 # it's enabled.  This isn't used for anything else other than StaticInst
  69 # headers.
  70 temp_cpu_list = env['CPU_MODELS'][:]
  71
  72 if env['USE_CHECKER']:
  73     temp_cpu_list.append('CheckerCPU')
  74     SimObject('CheckerCPU.py')
  75
  76 # Generate header.
  77 def gen_cpu_exec_signatures(target, source, env):
  78     f = open(str(target[0]), 'w')
  79     print >> f, '''
  80 #ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
  81 #define __CPU_STATIC_INST_EXEC_SIGS_HH__
  82 '''
  83     for cpu in temp_cpu_list:
  84         xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
  85         print >> f, exec_sig_template % (xc_type, xc_type, xc_type)
  86     print >> f, '''
  87 #endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
  88 '''
  89
  90 # Generate string that gets printed when header is rebuilt
  91 def gen_sigs_string(target, source, env):
  92     return "Generating static_inst_exec_sigs.hh: " \
  93            + ', '.join(temp_cpu_list)
  94
  95 # Add command to generate header to environment.
  96 env.Command('static_inst_exec_sigs.hh', models_db,
  97             Action(gen_cpu_exec_signatures, gen_sigs_string,
  98                    varlist = temp_cpu_list))
  99
 100 env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
 101 env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
 102
 103 # List of suppported CPUs by the Checker.  Errors out if USE_CHECKER=True
 104 # and one of these are not being used.
 105 CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
 106
 107 SimObject('BaseCPU.py')
 108 SimObject('FuncUnit.py')
 109 SimObject('ExeTracer.py')
 110 SimObject('IntelTrace.py')
 111
 112 Source('activity.cc')
 113 Source('base.cc')
 114 Source('cpuevent.cc')
 115 Source('exetrace.cc')
 116 Source('func_unit.cc')
 117 Source('inteltrace.cc')
 118 Source('pc_event.cc')
 119 Source('quiesce_event.cc')
 120 Source('static_inst.cc')
 121 Source('simple_thread.cc')
 122 Source('thread_context.cc')
 123 Source('thread_state.cc')
 124
 125 if env['FULL_SYSTEM']:
 126     SimObject('IntrControl.py')
 127
 128     Source('intr_control.cc')
 129     Source('profile.cc')
 130
 131     if env['TARGET_ISA'] == 'sparc':
 132         SimObject('LegionTrace.py')
 133         Source('legiontrace.cc')
 134
 135 if env['TARGET_ISA'] == 'x86':
 136     SimObject('NativeTrace.py')
 137     Source('nativetrace.cc')
 138
 139 if env['USE_CHECKER']:
 140     Source('checker/cpu.cc')
 141     TraceFlag('Checker')
 142     checker_supports = False
 143     for i in CheckerSupportedCPUList:
 144         if i in env['CPU_MODELS']:
 145             checker_supports = True
 146     if not checker_supports:
 147         print "Checker only supports CPU models",
 148         for i in CheckerSupportedCPUList:
 149             print i,
 150         print ", please set USE_CHECKER=False or use one of those CPU models"
 151         Exit(1)
 152
 153 TraceFlag('Activity')
 154 TraceFlag('Commit')
 155 TraceFlag('Context')
 156 TraceFlag('Decode')
 157 TraceFlag('DynInst')
 158 TraceFlag('ExecEnable')
 159 TraceFlag('ExecCPSeq')
 160 TraceFlag('ExecEffAddr')
 161 TraceFlag('ExecFetchSeq')
 162 TraceFlag('ExecOpClass')
 163 TraceFlag('ExecRegDelta')
 164 TraceFlag('ExecResult')
 165 TraceFlag('ExecSpeculative')
 166 TraceFlag('ExecSymbol')
 167 TraceFlag('ExecThread')
 168 TraceFlag('ExecTicks')
 169 TraceFlag('ExecMicro')
 170 TraceFlag('ExecMacro')
 171 TraceFlag('Fetch')
 172 TraceFlag('IntrControl')
 173 TraceFlag('PCEvent')
 174 TraceFlag('Quiesce')
 175
 176 CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
 177     'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro' ])