src/cpu/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2006 The Regents of The University of Michigan
   4 # All rights reserved.
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are
   8 # met: redistributions of source code must retain the above copyright
   9 # notice, this list of conditions and the following disclaimer;
  10 # redistributions in binary form must reproduce the above copyright
  11 # notice, this list of conditions and the following disclaimer in the
  12 # documentation and/or other materials provided with the distribution;
  13 # neither the name of the copyright holders nor the names of its
  14 # contributors may be used to endorse or promote products derived from
  15 # this software without specific prior written permission.
  16 #
  17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 #
  29 # Authors: Steve Reinhardt
  30
  31 Import('*')
  32
  33 if env['TARGET_ISA'] == 'null':
  34     SimObject('IntrControl.py')
  35     Source('intr_control_noisa.cc')
  36     Return()
  37
  38 #################################################################
  39 #
  40 # Generate StaticInst execute() method signatures.
  41 #
  42 # There must be one signature for each CPU model compiled in.
  43 # Since the set of compiled-in models is flexible, we generate a
  44 # header containing the appropriate set of signatures on the fly.
  45 #
  46 #################################################################
  47
  48 # Template for execute() signature.
  49 exec_sig_template = '''
  50 virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
  51 virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
  52 { panic("eaComp not defined!"); M5_DUMMY_RETURN };
  53 virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
  54 { panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
  55 virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
  56                           Trace::InstRecord *traceData) const
  57 { panic("completeAcc not defined!"); M5_DUMMY_RETURN };
  58 '''
  59
  60 mem_ini_sig_template = '''
  61 virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
  62 { panic("eaComp not defined!"); M5_DUMMY_RETURN };
  63 virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
  64 '''
  65
  66 mem_comp_sig_template = '''
  67 virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
  68 '''
  69
  70 # Generate a temporary CPU list, including the CheckerCPU if
  71 # it's enabled.  This isn't used for anything else other than StaticInst
  72 # headers.
  73 temp_cpu_list = env['CPU_MODELS'][:]
  74 temp_cpu_list.append('CheckerCPU')
  75 SimObject('CheckerCPU.py')
  76
  77 # Generate header.
  78 def gen_cpu_exec_signatures(target, source, env):
  79     f = open(str(target[0]), 'w')
  80     print >> f, '''
  81 #ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
  82 #define __CPU_STATIC_INST_EXEC_SIGS_HH__
  83 '''
  84     for cpu in temp_cpu_list:
  85         xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
  86         print >> f, exec_sig_template % { 'type' : xc_type }
  87     print >> f, '''
  88 #endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
  89 '''
  90
  91 # Generate string that gets printed when header is rebuilt
  92 def gen_sigs_string(target, source, env):
  93     return " [GENERATE] static_inst_exec_sigs.hh: " \
  94            + ', '.join(temp_cpu_list)
  95
  96 # Add command to generate header to environment.
  97 env.Command('static_inst_exec_sigs.hh', (),
  98             Action(gen_cpu_exec_signatures, gen_sigs_string,
  99                    varlist = temp_cpu_list))
 100
 101 env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
 102
 103 SimObject('BaseCPU.py')
 104 SimObject('FuncUnit.py')
 105 SimObject('ExeTracer.py')
 106 SimObject('IntelTrace.py')
 107 SimObject('IntrControl.py')
 108 SimObject('NativeTrace.py')
 109
 110 Source('activity.cc')
 111 Source('base.cc')
 112 Source('cpuevent.cc')
 113 Source('exetrace.cc')
 114 Source('func_unit.cc')
 115 Source('inteltrace.cc')
 116 Source('intr_control.cc')
 117 Source('nativetrace.cc')
 118 Source('pc_event.cc')
 119 Source('profile.cc')
 120 Source('quiesce_event.cc')
 121 Source('reg_class.cc')
 122 Source('static_inst.cc')
 123 Source('simple_thread.cc')
 124 Source('thread_context.cc')
 125 Source('thread_state.cc')
 126
 127 if env['TARGET_ISA'] == 'sparc':
 128     SimObject('LegionTrace.py')
 129     Source('legiontrace.cc')
 130
 131 SimObject('DummyChecker.py')
 132 Source('checker/cpu.cc')
 133 Source('dummy_checker.cc')
 134 DebugFlag('Checker')
 135
 136 DebugFlag('Activity')
 137 DebugFlag('Commit')
 138 DebugFlag('Context')
 139 DebugFlag('Decode')
 140 DebugFlag('DynInst')
 141 DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
 142 DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
 143 DebugFlag('ExecEffAddr', 'Format: Include effective address')
 144 DebugFlag('ExecFaulting', 'Trace faulting instructions')
 145 DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
 146 DebugFlag('ExecOpClass', 'Format: Include operand class')
 147 DebugFlag('ExecRegDelta')
 148 DebugFlag('ExecResult', 'Format: Include results from execution')
 149 DebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)')
 150 DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
 151 DebugFlag('ExecThread', 'Format: Include thread ID in trace')
 152 DebugFlag('ExecTicks', 'Format: Include tick count')
 153 DebugFlag('ExecMicro', 'Filter: Include microops')
 154 DebugFlag('ExecMacro', 'Filter: Include macroops')
 155 DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
 156 DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
 157 DebugFlag('ExecAsid', 'Format: Include ASID in trace')
 158 DebugFlag('Fetch')
 159 DebugFlag('IntrControl')
 160 DebugFlag('O3PipeView')
 161 DebugFlag('PCEvent')
 162 DebugFlag('Quiesce')
 163
 164 CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
 165     'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
 166     'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
 167     'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
 168     'ExecAsid' ])
 169 CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
 170     'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
 171     'ExecUser', 'ExecKernel' ])
 172 CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
 173     'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
 174     'ExecUser', 'ExecKernel' ])