src/cpu/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2006 The Regents of The University of Michigan
   4 # All rights reserved.
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are
   8 # met: redistributions of source code must retain the above copyright
   9 # notice, this list of conditions and the following disclaimer;
  10 # redistributions in binary form must reproduce the above copyright
  11 # notice, this list of conditions and the following disclaimer in the
  12 # documentation and/or other materials provided with the distribution;
  13 # neither the name of the copyright holders nor the names of its
  14 # contributors may be used to endorse or promote products derived from
  15 # this software without specific prior written permission.
  16 #
  17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 #
  29 # Authors: Steve Reinhardt
  30
  31 Import('*')
  32
  33 if env['TARGET_ISA'] == 'no':
  34     Return()
  35
  36 #################################################################
  37 #
  38 # Generate StaticInst execute() method signatures.
  39 #
  40 # There must be one signature for each CPU model compiled in.
  41 # Since the set of compiled-in models is flexible, we generate a
  42 # header containing the appropriate set of signatures on the fly.
  43 #
  44 #################################################################
  45
  46 # Template for execute() signature.
  47 exec_sig_template = '''
  48 virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
  49 virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
  50 { panic("eaComp not defined!"); M5_DUMMY_RETURN };
  51 virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
  52 { panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
  53 virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
  54                           Trace::InstRecord *traceData) const
  55 { panic("completeAcc not defined!"); M5_DUMMY_RETURN };
  56 '''
  57
  58 mem_ini_sig_template = '''
  59 virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
  60 { panic("eaComp not defined!"); M5_DUMMY_RETURN };
  61 virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
  62 '''
  63
  64 mem_comp_sig_template = '''
  65 virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
  66 '''
  67
  68 # Generate a temporary CPU list, including the CheckerCPU if
  69 # it's enabled.  This isn't used for anything else other than StaticInst
  70 # headers.
  71 temp_cpu_list = env['CPU_MODELS'][:]
  72 temp_cpu_list.append('CheckerCPU')
  73 SimObject('CheckerCPU.py')
  74
  75 # Generate header.
  76 def gen_cpu_exec_signatures(target, source, env):
  77     f = open(str(target[0]), 'w')
  78     print >> f, '''
  79 #ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
  80 #define __CPU_STATIC_INST_EXEC_SIGS_HH__
  81 '''
  82     for cpu in temp_cpu_list:
  83         xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
  84         print >> f, exec_sig_template % { 'type' : xc_type }
  85     print >> f, '''
  86 #endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
  87 '''
  88
  89 # Generate string that gets printed when header is rebuilt
  90 def gen_sigs_string(target, source, env):
  91     return " [GENERATE] static_inst_exec_sigs.hh: " \
  92            + ', '.join(temp_cpu_list)
  93
  94 # Add command to generate header to environment.
  95 env.Command('static_inst_exec_sigs.hh', (),
  96             Action(gen_cpu_exec_signatures, gen_sigs_string,
  97                    varlist = temp_cpu_list))
  98
  99 env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
 100
 101 SimObject('BaseCPU.py')
 102 SimObject('FuncUnit.py')
 103 SimObject('ExeTracer.py')
 104 SimObject('IntelTrace.py')
 105 SimObject('IntrControl.py')
 106 SimObject('NativeTrace.py')
 107
 108 Source('activity.cc')
 109 Source('base.cc')
 110 Source('cpuevent.cc')
 111 Source('decode.cc')
 112 Source('exetrace.cc')
 113 Source('func_unit.cc')
 114 Source('inteltrace.cc')
 115 Source('intr_control.cc')
 116 Source('nativetrace.cc')
 117 Source('pc_event.cc')
 118 Source('profile.cc')
 119 Source('quiesce_event.cc')
 120 Source('static_inst.cc')
 121 Source('simple_thread.cc')
 122 Source('thread_context.cc')
 123 Source('thread_state.cc')
 124
 125 if env['TARGET_ISA'] == 'sparc':
 126     SimObject('LegionTrace.py')
 127     Source('legiontrace.cc')
 128
 129 SimObject('DummyChecker.py')
 130 Source('checker/cpu.cc')
 131 Source('dummy_checker_builder.cc')
 132 DebugFlag('Checker')
 133
 134 DebugFlag('Activity')
 135 DebugFlag('Commit')
 136 DebugFlag('Context')
 137 DebugFlag('Decode')
 138 DebugFlag('DynInst')
 139 DebugFlag('ExecEnable')
 140 DebugFlag('ExecCPSeq')
 141 DebugFlag('ExecEffAddr')
 142 DebugFlag('ExecFaulting', 'Trace faulting instructions')
 143 DebugFlag('ExecFetchSeq')
 144 DebugFlag('ExecOpClass')
 145 DebugFlag('ExecRegDelta')
 146 DebugFlag('ExecResult')
 147 DebugFlag('ExecSpeculative')
 148 DebugFlag('ExecSymbol')
 149 DebugFlag('ExecThread')
 150 DebugFlag('ExecTicks')
 151 DebugFlag('ExecMicro')
 152 DebugFlag('ExecMacro')
 153 DebugFlag('ExecUser')
 154 DebugFlag('ExecKernel')
 155 DebugFlag('ExecAsid')
 156 DebugFlag('Fetch')
 157 DebugFlag('IntrControl')
 158 DebugFlag('O3PipeView')
 159 DebugFlag('PCEvent')
 160 DebugFlag('Quiesce')
 161
 162 CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
 163     'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
 164     'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
 165     'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
 166     'ExecAsid' ])
 167 CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
 168     'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
 169     'ExecUser', 'ExecKernel' ])
 170 CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
 171     'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
 172     'ExecUser', 'ExecKernel' ])