src/cpu/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2006 The Regents of The University of Michigan
   4 # All rights reserved.
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are
   8 # met: redistributions of source code must retain the above copyright
   9 # notice, this list of conditions and the following disclaimer;
  10 # redistributions in binary form must reproduce the above copyright
  11 # notice, this list of conditions and the following disclaimer in the
  12 # documentation and/or other materials provided with the distribution;
  13 # neither the name of the copyright holders nor the names of its
  14 # contributors may be used to endorse or promote products derived from
  15 # this software without specific prior written permission.
  16 #
  17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 #
  29 # Authors: Steve Reinhardt
  30
  31 Import('*')
  32
  33 DebugFlag('Activity')
  34 DebugFlag('Commit')
  35 DebugFlag('Context')
  36 DebugFlag('Decode')
  37 DebugFlag('DynInst')
  38 DebugFlag('ExecEnable',
  39         'Filter: Enable exec tracing (no tracing without this)')
  40 DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
  41 DebugFlag('ExecEffAddr', 'Format: Include effective address')
  42 DebugFlag('ExecFaulting', 'Trace faulting instructions')
  43 DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
  44 DebugFlag('ExecOpClass', 'Format: Include operand class')
  45 DebugFlag('ExecRegDelta')
  46 DebugFlag('ExecResult', 'Format: Include results from execution')
  47 DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
  48 DebugFlag('ExecThread', 'Format: Include thread ID in trace')
  49 DebugFlag('ExecTicks', 'Format: Include tick count')
  50 DebugFlag('ExecMicro', 'Filter: Include microops')
  51 DebugFlag('ExecMacro', 'Filter: Include macroops')
  52 DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
  53 DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
  54 DebugFlag('ExecAsid', 'Format: Include ASID in trace')
  55 DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
  56 DebugFlag('Fetch')
  57 DebugFlag('IntrControl')
  58 DebugFlag('O3PipeView')
  59 DebugFlag('PCEvent')
  60 DebugFlag('Quiesce')
  61 DebugFlag('Mwait')
  62
  63 CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
  64     'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
  65     'ExecResult', 'ExecSymbol', 'ExecThread',
  66     'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
  67     'ExecAsid', 'ExecFlags' ])
  68 CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
  69     'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecMacro',
  70     'ExecFaulting', 'ExecUser', 'ExecKernel' ])
  71 CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
  72     'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecMacro', 'ExecFaulting',
  73     'ExecUser', 'ExecKernel' ])
  74
  75 if env['TARGET_ISA'] == 'null':
  76     SimObject('IntrControl.py')
  77     Source('intr_control_noisa.cc')
  78     Return()
  79
  80 # Only build the protocol buffer instructions tracer if we have protobuf support
  81 if env['HAVE_PROTOBUF'] and env['TARGET_ISA'] != 'x86':
  82     SimObject('InstPBTrace.py')
  83     Source('inst_pb_trace.cc')
  84
  85 SimObject('CheckerCPU.py')
  86
  87 SimObject('BaseCPU.py')
  88 SimObject('CPUTracers.py')
  89 SimObject('FuncUnit.py')
  90 SimObject('IntrControl.py')
  91 SimObject('TimingExpr.py')
  92
  93 Source('activity.cc')
  94 Source('base.cc')
  95 Source('cpuevent.cc')
  96 Source('exetrace.cc')
  97 Source('exec_context.cc')
  98 Source('func_unit.cc')
  99 Source('inteltrace.cc')
 100 Source('intr_control.cc')
 101 Source('nativetrace.cc')
 102 Source('pc_event.cc')
 103 Source('profile.cc')
 104 Source('quiesce_event.cc')
 105 Source('reg_class.cc')
 106 Source('static_inst.cc')
 107 Source('simple_thread.cc')
 108 Source('thread_context.cc')
 109 Source('thread_state.cc')
 110 Source('timing_expr.cc')
 111
 112 SimObject('DummyChecker.py')
 113 SimObject('StaticInstFlags.py')
 114 Source('checker/cpu.cc')
 115 Source('dummy_checker.cc')
 116 DebugFlag('Checker')