src/cpu/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2006 The Regents of The University of Michigan
   4 # All rights reserved.
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are
   8 # met: redistributions of source code must retain the above copyright
   9 # notice, this list of conditions and the following disclaimer;
  10 # redistributions in binary form must reproduce the above copyright
  11 # notice, this list of conditions and the following disclaimer in the
  12 # documentation and/or other materials provided with the distribution;
  13 # neither the name of the copyright holders nor the names of its
  14 # contributors may be used to endorse or promote products derived from
  15 # this software without specific prior written permission.
  16 #
  17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 #
  29 # Authors: Steve Reinhardt
  30
  31 Import('*')
  32
  33 #################################################################
  34 #
  35 # Generate StaticInst execute() method signatures.
  36 #
  37 # There must be one signature for each CPU model compiled in.
  38 # Since the set of compiled-in models is flexible, we generate a
  39 # header containing the appropriate set of signatures on the fly.
  40 #
  41 #################################################################
  42
  43 # CPU model-specific data is contained in cpu_models.py
  44 # Convert to SCons File node to get path handling
  45 models_db = File('cpu_models.py')
  46 # slurp in contents of file
  47 execfile(models_db.srcnode().abspath)
  48
  49 # Template for execute() signature.
  50 exec_sig_template = '''
  51 virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
  52 virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
  53 { panic("eaComp not defined!"); M5_DUMMY_RETURN };
  54 virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
  55 { panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
  56 virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
  57                           Trace::InstRecord *traceData) const
  58 { panic("completeAcc not defined!"); M5_DUMMY_RETURN };
  59 '''
  60
  61 mem_ini_sig_template = '''
  62 virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
  63 { panic("eaComp not defined!"); M5_DUMMY_RETURN };
  64 virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
  65 '''
  66
  67 mem_comp_sig_template = '''
  68 virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
  69 '''
  70
  71 # Generate a temporary CPU list, including the CheckerCPU if
  72 # it's enabled.  This isn't used for anything else other than StaticInst
  73 # headers.
  74 temp_cpu_list = env['CPU_MODELS'][:]
  75
  76 if env['USE_CHECKER']:
  77     temp_cpu_list.append('CheckerCPU')
  78     SimObject('CheckerCPU.py')
  79
  80 # Generate header.
  81 def gen_cpu_exec_signatures(target, source, env):
  82     f = open(str(target[0]), 'w')
  83     print >> f, '''
  84 #ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
  85 #define __CPU_STATIC_INST_EXEC_SIGS_HH__
  86 '''
  87     for cpu in temp_cpu_list:
  88         xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
  89         print >> f, exec_sig_template % { 'type' : xc_type }
  90     print >> f, '''
  91 #endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
  92 '''
  93
  94 # Generate string that gets printed when header is rebuilt
  95 def gen_sigs_string(target, source, env):
  96     return "Generating static_inst_exec_sigs.hh: " \
  97            + ', '.join(temp_cpu_list)
  98
  99 # Add command to generate header to environment.
 100 env.Command('static_inst_exec_sigs.hh', models_db,
 101             Action(gen_cpu_exec_signatures, gen_sigs_string,
 102                    varlist = temp_cpu_list))
 103
 104 env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
 105 env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
 106
 107 # List of suppported CPUs by the Checker.  Errors out if USE_CHECKER=True
 108 # and one of these are not being used.
 109 CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
 110
 111 SimObject('BaseCPU.py')
 112 SimObject('FuncUnit.py')
 113 SimObject('ExeTracer.py')
 114 SimObject('IntelTrace.py')
 115
 116 Source('activity.cc')
 117 Source('base.cc')
 118 Source('cpuevent.cc')
 119 Source('exetrace.cc')
 120 Source('func_unit.cc')
 121 Source('inteltrace.cc')
 122 Source('pc_event.cc')
 123 Source('quiesce_event.cc')
 124 Source('static_inst.cc')
 125 Source('simple_thread.cc')
 126 Source('thread_context.cc')
 127 Source('thread_state.cc')
 128
 129 if 'InOrderCPU' in env['CPU_MODELS'] or 'O3CPU' in env['CPU_MODELS']:
 130     Source('btb.cc')
 131     Source('tournament_pred.cc')
 132     Source('2bit_local_pred.cc')
 133     Source('ras.cc')
 134     TraceFlag('FreeList')
 135
 136 if env['FULL_SYSTEM']:
 137     SimObject('IntrControl.py')
 138
 139     Source('intr_control.cc')
 140     Source('profile.cc')
 141
 142     if env['TARGET_ISA'] == 'sparc':
 143         SimObject('LegionTrace.py')
 144         Source('legiontrace.cc')
 145
 146 if env['TARGET_ISA'] == 'x86':
 147     SimObject('NativeTrace.py')
 148     Source('nativetrace.cc')
 149
 150 if env['USE_CHECKER']:
 151     Source('checker/cpu.cc')
 152     TraceFlag('Checker')
 153     checker_supports = False
 154     for i in CheckerSupportedCPUList:
 155         if i in env['CPU_MODELS']:
 156             checker_supports = True
 157     if not checker_supports:
 158         print "Checker only supports CPU models",
 159         for i in CheckerSupportedCPUList:
 160             print i,
 161         print ", please set USE_CHECKER=False or use one of those CPU models"
 162         Exit(1)
 163
 164 TraceFlag('Activity')
 165 TraceFlag('Commit')
 166 TraceFlag('Context')
 167 TraceFlag('Decode')
 168 TraceFlag('DynInst')
 169 TraceFlag('ExecEnable')
 170 TraceFlag('ExecCPSeq')
 171 TraceFlag('ExecEffAddr')
 172 TraceFlag('ExecFetchSeq')
 173 TraceFlag('ExecOpClass')
 174 TraceFlag('ExecRegDelta')
 175 TraceFlag('ExecResult')
 176 TraceFlag('ExecSpeculative')
 177 TraceFlag('ExecSymbol')
 178 TraceFlag('ExecThread')
 179 TraceFlag('ExecTicks')
 180 TraceFlag('ExecMicro')
 181 TraceFlag('ExecMacro')
 182 TraceFlag('Fetch')
 183 TraceFlag('IntrControl')
 184 TraceFlag('PCEvent')
 185 TraceFlag('Quiesce')
 186
 187 CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
 188     'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro' ])
 189 CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
 190     'ExecEffAddr', 'ExecResult', 'ExecMicro' ])