src/cpu/StaticInstFlags.py

   1 # Copyright (c) 2020 ARM Limited
   2 # Copyright (c) 2003-2005 The Regents of The University of Michigan
   3 # Copyright (c) 2013 Advanced Micro Devices, Inc.
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  28
  29 from m5.params import *
  30
  31 # Set of boolean static instruction properties.
  32 #
  33 # Notes:
  34 # - The IsInteger and IsFloating flags are based on the class of registers
  35 # accessed by the instruction.  Although most instructions will have exactly
  36 # one of these two flags set, it is possible for an instruction to have
  37 # neither (e.g., direct unconditional branches, memory barriers) or both
  38 # (e.g., an FP/int conversion).
  39 # - If IsMemRef is set, then exactly one of IsLoad or IsStore will be set.
  40 # - If IsControl is set, then exactly one of IsDirectControl or IsIndirect
  41 # Control will be set, and exactly one of IsCondControl or IsUncondControl
  42 # will be set.
  43 # - IsSerializing, IsMemBarrier, and IsWriteBarrier are implemented as flags
  44 # since in the current model there's no other way for instructions to inject
  45 # behavior into the pipeline outside of fetch.  Once we go to an exec-in-exec
  46 # CPU model we should be able to get rid of these flags and implement this
  47 # behavior via the execute() methods.
  48
  49 class StaticInstFlags(Enum):
  50     wrapper_name = 'StaticInstFlags'
  51     wrapper_is_struct = True
  52     enum_name = 'Flags'
  53
  54     vals = [
  55         'IsNop',            # Is a no-op (no effect at all).
  56
  57         'IsInteger',        # References integer regs.
  58         'IsFloating',       # References FP regs.
  59         'IsCC',             # References CC regs.
  60         'IsVector',         # References Vector regs.
  61         'IsVectorElem',     # References Vector reg elems.
  62
  63         'IsMemRef',         # References memory (load, store, or prefetch)
  64         'IsLoad',           # Reads from memory (load or prefetch).
  65         'IsStore',          # Writes to memory.
  66         'IsAtomic',         # Does atomic RMW to memory.
  67         'IsStoreConditional',   # Store conditional instruction.
  68         'IsIndexed',        # Accesses memory with an indexed address
  69                             # computation
  70         'IsInstPrefetch',   # Instruction-cache prefetch.
  71         'IsDataPrefetch',   # Data-cache prefetch.
  72
  73         'IsControl',        # Control transfer instruction.
  74         'IsDirectControl',  # PC relative control transfer.
  75         'IsIndirectControl',# Register indirect control transfer.
  76         'IsCondControl',    # Conditional control transfer.
  77         'IsUncondControl',  # Unconditional control transfer.
  78         'IsCall',           # Subroutine call.
  79         'IsReturn',         # Subroutine return.
  80
  81         'IsSerializing',    # Serializes pipeline: won't execute until all
  82                             # older instructions have committed.
  83         'IsSerializeBefore',
  84         'IsSerializeAfter',
  85         'IsMemBarrier',     # Is a memory barrier
  86         'IsWriteBarrier',   # Is a write barrier
  87         'IsReadBarrier',    # Is a read barrier
  88
  89         'IsNonSpeculative', # Should not be executed speculatively
  90         'IsQuiesce',        # Is a quiesce instruction
  91
  92         'IsIprAccess',      # Accesses IPRs
  93         'IsUnverifiable',   # Can't be verified by a checker
  94
  95         'IsSyscall',        # Causes a system call to be emulated in syscall
  96                             # emulation mode.
  97
  98         # Flags for microcode
  99         'IsMacroop',        # Is a macroop containing microops
 100         'IsMicroop',        # Is a microop
 101         'IsDelayedCommit',  # This microop doesn't commit right away
 102         'IsLastMicroop',    # This microop ends a microop sequence
 103         'IsFirstMicroop',   # This microop begins a microop sequence
 104         # This flag doesn't do anything yet
 105         'IsMicroBranch',    # This microop branches within the microcode for
 106                             # a macroop
 107         'IsDspOp',
 108         'IsSquashAfter',     # Squash all uncommitted state after executed
 109         # hardware transactional memory
 110         'IsHtmStart',       # Starts a HTM transaction
 111         'IsHtmStop',        # Stops (commits) a HTM transaction
 112         'IsHtmCancel'       # Explicitely aborts a HTM transaction
 113         ]