src/cpu/TimingExpr.py

   1 # Copyright (c) 2013-2014 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Redistribution and use in source and binary forms, with or without
  14 # modification, are permitted provided that the following conditions are
  15 # met: redistributions of source code must retain the above copyright
  16 # notice, this list of conditions and the following disclaimer;
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  18 # notice, this list of conditions and the following disclaimer in the
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  20 # neither the name of the copyright holders nor the names of its
  21 # contributors may be used to endorse or promote products derived from
  22 # this software without specific prior written permission.
  23 #
  24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 #
  36 # Authors: Andrew Bardsley
  37
  38 from m5.params import *
  39 from m5.SimObject import SimObject
  40
  41 # These classes define an expression language over uint64_t with only
  42 # a few operators.  This can be used to form expressions for the extra
  43 # delay required in variable execution time instructions.
  44 #
  45 # Expressions, in evaluation, will have access to the ThreadContext and
  46 # a StaticInst
  47
  48 class TimingExpr(SimObject):
  49     type = 'TimingExpr'
  50     cxx_header = 'cpu/timing_expr.hh'
  51     abstract = True;
  52
  53 class TimingExprLiteral(TimingExpr):
  54     """Literal 64 bit unsigned value"""
  55     type = 'TimingExprLiteral'
  56     cxx_header = 'cpu/timing_expr.hh'
  57
  58     value = Param.UInt64("literal value")
  59
  60     def set_params(self, value):
  61         self.value = value
  62         return self
  63
  64 class TimingExpr0(TimingExprLiteral):
  65     """Convenient 0"""
  66     value = 0
  67
  68 class TimingExprSrcReg(TimingExpr):
  69     """Find the source register number from the current inst"""
  70     type = 'TimingExprSrcReg'
  71     cxx_header = 'cpu/timing_expr.hh'
  72
  73     # index = Param.Unsigned("index into inst src regs")
  74     index = Param.Unsigned("index into inst src regs")
  75
  76     def set_params(self, index):
  77         self.index = index
  78         return self
  79
  80 class TimingExprReadIntReg(TimingExpr):
  81     """Read an architectural register"""
  82     type = 'TimingExprReadIntReg'
  83     cxx_header = 'cpu/timing_expr.hh'
  84
  85     reg = Param.TimingExpr("register raw index to read")
  86
  87     def set_params(self, reg):
  88         self.reg = reg
  89         return self
  90
  91 class TimingExprLet(TimingExpr):
  92     """Block of declarations"""
  93     type = 'TimingExprLet'
  94     cxx_header = 'cpu/timing_expr.hh'
  95
  96     defns = VectorParam.TimingExpr("expressions for bindings")
  97     expr = Param.TimingExpr("body expression")
  98
  99     def set_params(self, defns, expr):
 100         self.defns = defns
 101         self.expr = expr
 102         return self
 103
 104 class TimingExprRef(TimingExpr):
 105     """Value of a bound sub-expression"""
 106     type = 'TimingExprRef'
 107     cxx_header = 'cpu/timing_expr.hh'
 108
 109     index = Param.Unsigned("expression index")
 110
 111     def set_params(self, index):
 112         self.index = index
 113         return self
 114
 115 class TimingExprOp(Enum):
 116     vals = [
 117         'timingExprAdd', 'timingExprSub',
 118         'timingExprUMul', 'timingExprUDiv',
 119         'timingExprSMul', 'timingExprSDiv',
 120         'timingExprUCeilDiv', # Unsigned divide rounding up
 121         'timingExprEqual', 'timingExprNotEqual',
 122         'timingExprULessThan',
 123         'timingExprUGreaterThan',
 124         'timingExprSLessThan',
 125         'timingExprSGreaterThan',
 126         'timingExprInvert',
 127         'timingExprNot',
 128         'timingExprAnd',
 129         'timingExprOr',
 130         'timingExprSizeInBits',
 131         'timingExprSignExtend32To64',
 132         'timingExprAbs'
 133         ]
 134
 135 class TimingExprUn(TimingExpr):
 136     """Unary operator"""
 137     type = 'TimingExprUn'
 138     cxx_header = 'cpu/timing_expr.hh'
 139
 140     op = Param.TimingExprOp("operator")
 141     arg = Param.TimingExpr("expression")
 142
 143     def set_params(self, op, arg):
 144         self.op = op
 145         self.arg = arg
 146         return self
 147
 148 class TimingExprBin(TimingExpr):
 149     """Binary operator"""
 150     type = 'TimingExprBin'
 151     cxx_header = 'cpu/timing_expr.hh'
 152
 153     op = Param.TimingExprOp("operator")
 154     left = Param.TimingExpr("LHS expression")
 155     right = Param.TimingExpr("RHS expression")
 156
 157     def set_params(self, op, left, right):
 158         self.op = op
 159         self.left = left
 160         self.right = right
 161         return self
 162
 163 class TimingExprIf(TimingExpr):
 164     """If-then-else operator"""
 165     type = 'TimingExprIf'
 166     cxx_header = 'cpu/timing_expr.hh'
 167
 168     cond = Param.TimingExpr("condition expression")
 169     trueExpr = Param.TimingExpr("true expression")
 170     falseExpr = Param.TimingExpr("false expression")
 171
 172     def set_params(self, cond, trueExpr, falseExpr):
 173         self.cond = cond
 174         self.trueExpr = trueExpr
 175         self.falseExpr = falseExpr
 176         return self