10b8ce297d90d15d8bb4b2f3cf5445e15601a2be
2 * Copyright (c) 2011-2012,2016 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * Copyright (c) 2013 Advanced Micro Devices, Inc.
17 * Copyright (c) 2013 Mark D. Hill and David A. Wood
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are
22 * met: redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer;
24 * redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution;
27 * neither the name of the copyright holders nor the names of its
28 * contributors may be used to endorse or promote products derived from
29 * this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * Authors: Steve Reinhardt
48 #include "cpu/base.hh"
54 #include "arch/tlb.hh"
55 #include "base/cprintf.hh"
56 #include "base/loader/symtab.hh"
57 #include "base/misc.hh"
58 #include "base/output.hh"
59 #include "base/trace.hh"
60 #include "cpu/checker/cpu.hh"
61 #include "cpu/cpuevent.hh"
62 #include "cpu/profile.hh"
63 #include "cpu/thread_context.hh"
64 #include "debug/Mwait.hh"
65 #include "debug/SyscallVerbose.hh"
66 #include "mem/page_table.hh"
67 #include "params/BaseCPU.hh"
68 #include "sim/clocked_object.hh"
69 #include "sim/full_system.hh"
70 #include "sim/process.hh"
71 #include "sim/sim_events.hh"
72 #include "sim/sim_exit.hh"
73 #include "sim/system.hh"
76 #include "sim/stat_control.hh"
80 vector
<BaseCPU
*> BaseCPU::cpuList
;
82 // This variable reflects the max number of threads in any CPU. Be
83 // careful to only use it once all the CPUs that you care about have
85 int maxThreadsPerCPU
= 1;
87 CPUProgressEvent::CPUProgressEvent(BaseCPU
*_cpu
, Tick ival
)
88 : Event(Event::Progress_Event_Pri
), _interval(ival
), lastNumInst(0),
89 cpu(_cpu
), _repeatEvent(true)
92 cpu
->schedule(this, curTick() + _interval
);
96 CPUProgressEvent::process()
98 Counter temp
= cpu
->totalOps();
101 cpu
->schedule(this, curTick() + _interval
);
103 if (cpu
->switchedOut()) {
108 double ipc
= double(temp
- lastNumInst
) / (_interval
/ cpu
->clockPeriod());
110 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
111 "%lli, IPC: %0.8d\n", cpu
->name(), temp
, temp
- lastNumInst
,
115 cprintf("%lli: %s progress event, total committed:%i, progress insts "
116 "committed: %lli\n", curTick(), cpu
->name(), temp
,
123 CPUProgressEvent::description() const
125 return "CPU Progress";
128 BaseCPU::BaseCPU(Params
*p
, bool is_checker
)
129 : MemObject(p
), instCnt(0), _cpuId(p
->cpu_id
), _socketId(p
->socket_id
),
130 _instMasterId(p
->system
->getMasterId(name() + ".inst")),
131 _dataMasterId(p
->system
->getMasterId(name() + ".data")),
132 _taskId(ContextSwitchTaskId::Unknown
), _pid(invldPid
),
133 _switchedOut(p
->switched_out
), _cacheLineSize(p
->system
->cacheLineSize()),
134 interrupts(p
->interrupts
), profileEvent(NULL
),
135 numThreads(p
->numThreads
), system(p
->system
),
136 functionTraceStream(nullptr), currentFunctionStart(0),
137 currentFunctionEnd(0), functionEntryTick(0),
138 addressMonitor(p
->numThreads
)
140 // if Python did not provide a valid ID, do it here
142 _cpuId
= cpuList
.size();
145 // add self to global list of CPUs
146 cpuList
.push_back(this);
148 DPRINTF(SyscallVerbose
, "Constructing CPU with id %d, socket id %d\n",
151 if (numThreads
> maxThreadsPerCPU
)
152 maxThreadsPerCPU
= numThreads
;
154 // allocate per-thread instruction-based event queues
155 comInstEventQueue
= new EventQueue
*[numThreads
];
156 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
157 comInstEventQueue
[tid
] =
158 new EventQueue("instruction-based event queue");
161 // set up instruction-count-based termination events, if any
163 if (p
->max_insts_any_thread
!= 0) {
164 const char *cause
= "a thread reached the max instruction count";
165 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
166 scheduleInstStop(tid
, p
->max_insts_any_thread
, cause
);
169 // Set up instruction-count-based termination events for SimPoints
170 // Typically, there are more than one action points.
171 // Simulation.py is responsible to take the necessary actions upon
172 // exitting the simulation loop.
173 if (!p
->simpoint_start_insts
.empty()) {
174 const char *cause
= "simpoint starting point found";
175 for (size_t i
= 0; i
< p
->simpoint_start_insts
.size(); ++i
)
176 scheduleInstStop(0, p
->simpoint_start_insts
[i
], cause
);
179 if (p
->max_insts_all_threads
!= 0) {
180 const char *cause
= "all threads reached the max instruction count";
182 // allocate & initialize shared downcounter: each event will
183 // decrement this when triggered; simulation will terminate
184 // when counter reaches 0
185 int *counter
= new int;
186 *counter
= numThreads
;
187 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
188 Event
*event
= new CountedExitEvent(cause
, *counter
);
189 comInstEventQueue
[tid
]->schedule(event
, p
->max_insts_all_threads
);
193 // allocate per-thread load-based event queues
194 comLoadEventQueue
= new EventQueue
*[numThreads
];
195 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
196 comLoadEventQueue
[tid
] = new EventQueue("load-based event queue");
199 // set up instruction-count-based termination events, if any
201 if (p
->max_loads_any_thread
!= 0) {
202 const char *cause
= "a thread reached the max load count";
203 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
204 scheduleLoadStop(tid
, p
->max_loads_any_thread
, cause
);
207 if (p
->max_loads_all_threads
!= 0) {
208 const char *cause
= "all threads reached the max load count";
209 // allocate & initialize shared downcounter: each event will
210 // decrement this when triggered; simulation will terminate
211 // when counter reaches 0
212 int *counter
= new int;
213 *counter
= numThreads
;
214 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
215 Event
*event
= new CountedExitEvent(cause
, *counter
);
216 comLoadEventQueue
[tid
]->schedule(event
, p
->max_loads_all_threads
);
220 functionTracingEnabled
= false;
221 if (p
->function_trace
) {
222 const string fname
= csprintf("ftrace.%s", name());
223 functionTraceStream
= simout
.findOrCreate(fname
)->stream();
225 currentFunctionStart
= currentFunctionEnd
= 0;
226 functionEntryTick
= p
->function_trace_start
;
228 if (p
->function_trace_start
== 0) {
229 functionTracingEnabled
= true;
231 typedef EventWrapper
<BaseCPU
, &BaseCPU::enableFunctionTrace
> wrap
;
232 Event
*event
= new wrap(this, true);
233 schedule(event
, p
->function_trace_start
);
237 // The interrupts should always be present unless this CPU is
238 // switched in later or in case it is a checker CPU
239 if (!params()->switched_out
&& !is_checker
) {
240 fatal_if(interrupts
.size() != numThreads
,
241 "CPU %s has %i interrupt controllers, but is expecting one "
243 name(), interrupts
.size(), numThreads
);
244 for (ThreadID tid
= 0; tid
< numThreads
; tid
++)
245 interrupts
[tid
]->setCPU(this);
249 if (params()->profile
)
250 profileEvent
= new ProfileEvent(this, params()->profile
);
252 tracer
= params()->tracer
;
254 if (params()->isa
.size() != numThreads
) {
255 fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
256 "of threads (%i).\n", params()->isa
.size(), numThreads
);
261 BaseCPU::enableFunctionTrace()
263 functionTracingEnabled
= true;
269 delete[] comLoadEventQueue
;
270 delete[] comInstEventQueue
;
274 BaseCPU::armMonitor(ThreadID tid
, Addr address
)
276 assert(tid
< numThreads
);
277 AddressMonitor
&monitor
= addressMonitor
[tid
];
279 monitor
.armed
= true;
280 monitor
.vAddr
= address
;
282 DPRINTF(Mwait
,"[tid:%d] Armed monitor (vAddr=0x%lx)\n", tid
, address
);
286 BaseCPU::mwait(ThreadID tid
, PacketPtr pkt
)
288 assert(tid
< numThreads
);
289 AddressMonitor
&monitor
= addressMonitor
[tid
];
291 if (!monitor
.gotWakeup
) {
292 int block_size
= cacheLineSize();
293 uint64_t mask
= ~((uint64_t)(block_size
- 1));
295 assert(pkt
->req
->hasPaddr());
296 monitor
.pAddr
= pkt
->getAddr() & mask
;
297 monitor
.waiting
= true;
299 DPRINTF(Mwait
,"[tid:%d] mwait called (vAddr=0x%lx, "
300 "line's paddr=0x%lx)\n", tid
, monitor
.vAddr
, monitor
.pAddr
);
303 monitor
.gotWakeup
= false;
309 BaseCPU::mwaitAtomic(ThreadID tid
, ThreadContext
*tc
, TheISA::TLB
*dtb
)
311 assert(tid
< numThreads
);
312 AddressMonitor
&monitor
= addressMonitor
[tid
];
315 Addr addr
= monitor
.vAddr
;
316 int block_size
= cacheLineSize();
317 uint64_t mask
= ~((uint64_t)(block_size
- 1));
318 int size
= block_size
;
320 //The address of the next line if it crosses a cache line boundary.
321 Addr secondAddr
= roundDown(addr
+ size
- 1, block_size
);
323 if (secondAddr
> addr
)
324 size
= secondAddr
- addr
;
326 req
.setVirt(0, addr
, size
, 0x0, dataMasterId(), tc
->instAddr());
328 // translate to physical address
329 Fault fault
= dtb
->translateAtomic(&req
, tc
, BaseTLB::Read
);
330 assert(fault
== NoFault
);
332 monitor
.pAddr
= req
.getPaddr() & mask
;
333 monitor
.waiting
= true;
335 DPRINTF(Mwait
,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
336 tid
, monitor
.vAddr
, monitor
.pAddr
);
342 if (!params()->switched_out
) {
343 registerThreadContexts();
353 if (!params()->switched_out
&& profileEvent
)
354 schedule(profileEvent
, curTick());
357 if (params()->progress_interval
) {
358 new CPUProgressEvent(this, params()->progress_interval
);
361 // Assumption CPU start to operate instantaneously without any latency
362 if (ClockedObject::pwrState() == Enums::PwrState::UNDEFINED
)
363 ClockedObject::pwrState(Enums::PwrState::ON
);
368 BaseCPU::pmuProbePoint(const char *name
)
370 ProbePoints::PMUUPtr ptr
;
371 ptr
.reset(new ProbePoints::PMU(getProbeManager(), name
));
377 BaseCPU::regProbePoints()
379 ppCycles
= pmuProbePoint("Cycles");
381 ppRetiredInsts
= pmuProbePoint("RetiredInsts");
382 ppRetiredLoads
= pmuProbePoint("RetiredLoads");
383 ppRetiredStores
= pmuProbePoint("RetiredStores");
384 ppRetiredBranches
= pmuProbePoint("RetiredBranches");
388 BaseCPU::probeInstCommit(const StaticInstPtr
&inst
)
390 if (!inst
->isMicroop() || inst
->isLastMicroop())
391 ppRetiredInsts
->notify(1);
395 ppRetiredLoads
->notify(1);
398 ppRetiredStores
->notify(1);
400 if (inst
->isControl())
401 ppRetiredBranches
->notify(1);
407 MemObject::regStats();
409 using namespace Stats
;
412 .name(name() + ".numCycles")
413 .desc("number of cpu cycles simulated")
417 .name(name() + ".numWorkItemsStarted")
418 .desc("number of work items this cpu started")
421 numWorkItemsCompleted
422 .name(name() + ".numWorkItemsCompleted")
423 .desc("number of work items this cpu completed")
426 int size
= threadContexts
.size();
428 for (int i
= 0; i
< size
; ++i
) {
429 stringstream namestr
;
430 ccprintf(namestr
, "%s.ctx%d", name(), i
);
431 threadContexts
[i
]->regStats(namestr
.str());
433 } else if (size
== 1)
434 threadContexts
[0]->regStats(name());
438 BaseCPU::getMasterPort(const string
&if_name
, PortID idx
)
440 // Get the right port based on name. This applies to all the
441 // subclasses of the base CPU and relies on their implementation
442 // of getDataPort and getInstPort. In all cases there methods
443 // return a MasterPort pointer.
444 if (if_name
== "dcache_port")
445 return getDataPort();
446 else if (if_name
== "icache_port")
447 return getInstPort();
449 return MemObject::getMasterPort(if_name
, idx
);
453 BaseCPU::registerThreadContexts()
455 assert(system
->multiThread
|| numThreads
== 1);
457 ThreadID size
= threadContexts
.size();
458 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
459 ThreadContext
*tc
= threadContexts
[tid
];
461 if (system
->multiThread
) {
462 tc
->setContextId(system
->registerThreadContext(tc
));
464 tc
->setContextId(system
->registerThreadContext(tc
, _cpuId
));
468 tc
->getProcessPtr()->assignThreadContext(tc
->contextId());
474 BaseCPU::findContext(ThreadContext
*tc
)
476 ThreadID size
= threadContexts
.size();
477 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
478 if (tc
== threadContexts
[tid
])
485 BaseCPU::activateContext(ThreadID thread_num
)
487 // For any active thread running, update CPU power state to active (ON)
488 ClockedObject::pwrState(Enums::PwrState::ON
);
492 BaseCPU::suspendContext(ThreadID thread_num
)
494 // Check if all threads are suspended
495 for (auto t
: threadContexts
) {
496 if (t
->status() != ThreadContext::Suspended
) {
501 // All CPU threads suspended, enter lower power state for the CPU
502 ClockedObject::pwrState(Enums::PwrState::CLK_GATED
);
508 assert(!_switchedOut
);
510 if (profileEvent
&& profileEvent
->scheduled())
511 deschedule(profileEvent
);
513 // Flush all TLBs in the CPU to avoid having stale translations if
514 // it gets switched in later.
519 BaseCPU::takeOverFrom(BaseCPU
*oldCPU
)
521 assert(threadContexts
.size() == oldCPU
->threadContexts
.size());
522 assert(_cpuId
== oldCPU
->cpuId());
523 assert(_switchedOut
);
524 assert(oldCPU
!= this);
525 _pid
= oldCPU
->getPid();
526 _taskId
= oldCPU
->taskId();
527 _switchedOut
= false;
529 ThreadID size
= threadContexts
.size();
530 for (ThreadID i
= 0; i
< size
; ++i
) {
531 ThreadContext
*newTC
= threadContexts
[i
];
532 ThreadContext
*oldTC
= oldCPU
->threadContexts
[i
];
534 newTC
->takeOverFrom(oldTC
);
536 CpuEvent::replaceThreadContext(oldTC
, newTC
);
538 assert(newTC
->contextId() == oldTC
->contextId());
539 assert(newTC
->threadId() == oldTC
->threadId());
540 system
->replaceThreadContext(newTC
, newTC
->contextId());
542 /* This code no longer works since the zero register (e.g.,
543 * r31 on Alpha) doesn't necessarily contain zero at this
546 ThreadContext::compare(oldTC, newTC);
549 BaseMasterPort
*old_itb_port
= oldTC
->getITBPtr()->getMasterPort();
550 BaseMasterPort
*old_dtb_port
= oldTC
->getDTBPtr()->getMasterPort();
551 BaseMasterPort
*new_itb_port
= newTC
->getITBPtr()->getMasterPort();
552 BaseMasterPort
*new_dtb_port
= newTC
->getDTBPtr()->getMasterPort();
554 // Move over any table walker ports if they exist
556 assert(!new_itb_port
->isConnected());
557 assert(old_itb_port
);
558 assert(old_itb_port
->isConnected());
559 BaseSlavePort
&slavePort
= old_itb_port
->getSlavePort();
560 old_itb_port
->unbind();
561 new_itb_port
->bind(slavePort
);
564 assert(!new_dtb_port
->isConnected());
565 assert(old_dtb_port
);
566 assert(old_dtb_port
->isConnected());
567 BaseSlavePort
&slavePort
= old_dtb_port
->getSlavePort();
568 old_dtb_port
->unbind();
569 new_dtb_port
->bind(slavePort
);
571 newTC
->getITBPtr()->takeOverFrom(oldTC
->getITBPtr());
572 newTC
->getDTBPtr()->takeOverFrom(oldTC
->getDTBPtr());
574 // Checker whether or not we have to transfer CheckerCPU
575 // objects over in the switch
576 CheckerCPU
*oldChecker
= oldTC
->getCheckerCpuPtr();
577 CheckerCPU
*newChecker
= newTC
->getCheckerCpuPtr();
578 if (oldChecker
&& newChecker
) {
579 BaseMasterPort
*old_checker_itb_port
=
580 oldChecker
->getITBPtr()->getMasterPort();
581 BaseMasterPort
*old_checker_dtb_port
=
582 oldChecker
->getDTBPtr()->getMasterPort();
583 BaseMasterPort
*new_checker_itb_port
=
584 newChecker
->getITBPtr()->getMasterPort();
585 BaseMasterPort
*new_checker_dtb_port
=
586 newChecker
->getDTBPtr()->getMasterPort();
588 newChecker
->getITBPtr()->takeOverFrom(oldChecker
->getITBPtr());
589 newChecker
->getDTBPtr()->takeOverFrom(oldChecker
->getDTBPtr());
591 // Move over any table walker ports if they exist for checker
592 if (new_checker_itb_port
) {
593 assert(!new_checker_itb_port
->isConnected());
594 assert(old_checker_itb_port
);
595 assert(old_checker_itb_port
->isConnected());
596 BaseSlavePort
&slavePort
=
597 old_checker_itb_port
->getSlavePort();
598 old_checker_itb_port
->unbind();
599 new_checker_itb_port
->bind(slavePort
);
601 if (new_checker_dtb_port
) {
602 assert(!new_checker_dtb_port
->isConnected());
603 assert(old_checker_dtb_port
);
604 assert(old_checker_dtb_port
->isConnected());
605 BaseSlavePort
&slavePort
=
606 old_checker_dtb_port
->getSlavePort();
607 old_checker_dtb_port
->unbind();
608 new_checker_dtb_port
->bind(slavePort
);
613 interrupts
= oldCPU
->interrupts
;
614 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
615 interrupts
[tid
]->setCPU(this);
617 oldCPU
->interrupts
.clear();
620 for (ThreadID i
= 0; i
< size
; ++i
)
621 threadContexts
[i
]->profileClear();
624 schedule(profileEvent
, curTick());
627 // All CPUs have an instruction and a data port, and the new CPU's
628 // ports are dangling while the old CPU has its ports connected
629 // already. Unbind the old CPU and then bind the ports of the one
630 // we are switching to.
631 assert(!getInstPort().isConnected());
632 assert(oldCPU
->getInstPort().isConnected());
633 BaseSlavePort
&inst_peer_port
= oldCPU
->getInstPort().getSlavePort();
634 oldCPU
->getInstPort().unbind();
635 getInstPort().bind(inst_peer_port
);
637 assert(!getDataPort().isConnected());
638 assert(oldCPU
->getDataPort().isConnected());
639 BaseSlavePort
&data_peer_port
= oldCPU
->getDataPort().getSlavePort();
640 oldCPU
->getDataPort().unbind();
641 getDataPort().bind(data_peer_port
);
647 for (ThreadID i
= 0; i
< threadContexts
.size(); ++i
) {
648 ThreadContext
&tc(*threadContexts
[i
]);
649 CheckerCPU
*checker(tc
.getCheckerCpuPtr());
651 tc
.getITBPtr()->flushAll();
652 tc
.getDTBPtr()->flushAll();
654 checker
->getITBPtr()->flushAll();
655 checker
->getDTBPtr()->flushAll();
661 BaseCPU::ProfileEvent::ProfileEvent(BaseCPU
*_cpu
, Tick _interval
)
662 : cpu(_cpu
), interval(_interval
)
666 BaseCPU::ProfileEvent::process()
668 ThreadID size
= cpu
->threadContexts
.size();
669 for (ThreadID i
= 0; i
< size
; ++i
) {
670 ThreadContext
*tc
= cpu
->threadContexts
[i
];
674 cpu
->schedule(this, curTick() + interval
);
678 BaseCPU::serialize(CheckpointOut
&cp
) const
680 SERIALIZE_SCALAR(instCnt
);
683 /* Unlike _pid, _taskId is not serialized, as they are dynamically
684 * assigned unique ids that are only meaningful for the duration of
685 * a specific run. We will need to serialize the entire taskMap in
687 SERIALIZE_SCALAR(_pid
);
689 // Serialize the threads, this is done by the CPU implementation.
690 for (ThreadID i
= 0; i
< numThreads
; ++i
) {
691 ScopedCheckpointSection
sec(cp
, csprintf("xc.%i", i
));
692 interrupts
[i
]->serialize(cp
);
693 serializeThread(cp
, i
);
699 BaseCPU::unserialize(CheckpointIn
&cp
)
701 UNSERIALIZE_SCALAR(instCnt
);
704 UNSERIALIZE_SCALAR(_pid
);
706 // Unserialize the threads, this is done by the CPU implementation.
707 for (ThreadID i
= 0; i
< numThreads
; ++i
) {
708 ScopedCheckpointSection
sec(cp
, csprintf("xc.%i", i
));
709 interrupts
[i
]->unserialize(cp
);
710 unserializeThread(cp
, i
);
716 BaseCPU::scheduleInstStop(ThreadID tid
, Counter insts
, const char *cause
)
718 const Tick
now(comInstEventQueue
[tid
]->getCurTick());
719 Event
*event(new LocalSimLoopExitEvent(cause
, 0));
721 comInstEventQueue
[tid
]->schedule(event
, now
+ insts
);
725 BaseCPU::getCurrentInstCount(ThreadID tid
)
727 return Tick(comInstEventQueue
[tid
]->getCurTick());
730 AddressMonitor::AddressMonitor() {
736 bool AddressMonitor::doMonitor(PacketPtr pkt
) {
737 assert(pkt
->req
->hasPaddr());
738 if (armed
&& waiting
) {
739 if (pAddr
== pkt
->getAddr()) {
740 DPRINTF(Mwait
,"pAddr=0x%lx invalidated: waking up core\n",
750 BaseCPU::scheduleLoadStop(ThreadID tid
, Counter loads
, const char *cause
)
752 const Tick
now(comLoadEventQueue
[tid
]->getCurTick());
753 Event
*event(new LocalSimLoopExitEvent(cause
, 0));
755 comLoadEventQueue
[tid
]->schedule(event
, now
+ loads
);
760 BaseCPU::traceFunctionsInternal(Addr pc
)
762 if (!debugSymbolTable
)
765 // if pc enters different function, print new function symbol and
766 // update saved range. Otherwise do nothing.
767 if (pc
< currentFunctionStart
|| pc
>= currentFunctionEnd
) {
769 bool found
= debugSymbolTable
->findNearestSymbol(pc
, sym_str
,
770 currentFunctionStart
,
774 // no symbol found: use addr as label
775 sym_str
= csprintf("0x%x", pc
);
776 currentFunctionStart
= pc
;
777 currentFunctionEnd
= pc
+ 1;
780 ccprintf(*functionTraceStream
, " (%d)\n%d: %s",
781 curTick() - functionEntryTick
, curTick(), sym_str
);
782 functionEntryTick
= curTick();