1add92d1f65f271073d2ced76684c5be62668dc4
2 * Copyright (c) 2011-2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
50 #include "arch/tlb.hh"
51 #include "base/loader/symtab.hh"
52 #include "base/cprintf.hh"
53 #include "base/misc.hh"
54 #include "base/output.hh"
55 #include "base/trace.hh"
56 #include "cpu/base.hh"
57 #include "cpu/checker/cpu.hh"
58 #include "cpu/cpuevent.hh"
59 #include "cpu/profile.hh"
60 #include "cpu/thread_context.hh"
61 #include "debug/SyscallVerbose.hh"
62 #include "params/BaseCPU.hh"
63 #include "sim/full_system.hh"
64 #include "sim/process.hh"
65 #include "sim/sim_events.hh"
66 #include "sim/sim_exit.hh"
67 #include "sim/system.hh"
70 #include "sim/stat_control.hh"
74 vector
<BaseCPU
*> BaseCPU::cpuList
;
76 // This variable reflects the max number of threads in any CPU. Be
77 // careful to only use it once all the CPUs that you care about have
79 int maxThreadsPerCPU
= 1;
81 CPUProgressEvent::CPUProgressEvent(BaseCPU
*_cpu
, Tick ival
)
82 : Event(Event::Progress_Event_Pri
), _interval(ival
), lastNumInst(0),
83 cpu(_cpu
), _repeatEvent(true)
86 cpu
->schedule(this, curTick() + _interval
);
90 CPUProgressEvent::process()
92 Counter temp
= cpu
->totalOps();
94 double ipc
= double(temp
- lastNumInst
) / (_interval
/ cpu
->clockPeriod());
96 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
97 "%lli, IPC: %0.8d\n", cpu
->name(), temp
, temp
- lastNumInst
,
101 cprintf("%lli: %s progress event, total committed:%i, progress insts "
102 "committed: %lli\n", curTick(), cpu
->name(), temp
,
108 cpu
->schedule(this, curTick() + _interval
);
112 CPUProgressEvent::description() const
114 return "CPU Progress";
117 BaseCPU::BaseCPU(Params
*p
, bool is_checker
)
118 : MemObject(p
), instCnt(0), _cpuId(p
->cpu_id
),
119 _instMasterId(p
->system
->getMasterId(name() + ".inst")),
120 _dataMasterId(p
->system
->getMasterId(name() + ".data")),
121 interrupts(p
->interrupts
), profileEvent(NULL
),
122 numThreads(p
->numThreads
), system(p
->system
)
124 // if Python did not provide a valid ID, do it here
126 _cpuId
= cpuList
.size();
129 // add self to global list of CPUs
130 cpuList
.push_back(this);
132 DPRINTF(SyscallVerbose
, "Constructing CPU with id %d\n", _cpuId
);
134 if (numThreads
> maxThreadsPerCPU
)
135 maxThreadsPerCPU
= numThreads
;
137 // allocate per-thread instruction-based event queues
138 comInstEventQueue
= new EventQueue
*[numThreads
];
139 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
140 comInstEventQueue
[tid
] =
141 new EventQueue("instruction-based event queue");
144 // set up instruction-count-based termination events, if any
146 if (p
->max_insts_any_thread
!= 0) {
147 const char *cause
= "a thread reached the max instruction count";
148 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
149 Event
*event
= new SimLoopExitEvent(cause
, 0);
150 comInstEventQueue
[tid
]->schedule(event
, p
->max_insts_any_thread
);
154 if (p
->max_insts_all_threads
!= 0) {
155 const char *cause
= "all threads reached the max instruction count";
157 // allocate & initialize shared downcounter: each event will
158 // decrement this when triggered; simulation will terminate
159 // when counter reaches 0
160 int *counter
= new int;
161 *counter
= numThreads
;
162 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
163 Event
*event
= new CountedExitEvent(cause
, *counter
);
164 comInstEventQueue
[tid
]->schedule(event
, p
->max_insts_all_threads
);
168 // allocate per-thread load-based event queues
169 comLoadEventQueue
= new EventQueue
*[numThreads
];
170 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
171 comLoadEventQueue
[tid
] = new EventQueue("load-based event queue");
174 // set up instruction-count-based termination events, if any
176 if (p
->max_loads_any_thread
!= 0) {
177 const char *cause
= "a thread reached the max load count";
178 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
179 Event
*event
= new SimLoopExitEvent(cause
, 0);
180 comLoadEventQueue
[tid
]->schedule(event
, p
->max_loads_any_thread
);
184 if (p
->max_loads_all_threads
!= 0) {
185 const char *cause
= "all threads reached the max load count";
186 // allocate & initialize shared downcounter: each event will
187 // decrement this when triggered; simulation will terminate
188 // when counter reaches 0
189 int *counter
= new int;
190 *counter
= numThreads
;
191 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
192 Event
*event
= new CountedExitEvent(cause
, *counter
);
193 comLoadEventQueue
[tid
]->schedule(event
, p
->max_loads_all_threads
);
197 functionTracingEnabled
= false;
198 if (p
->function_trace
) {
199 const string fname
= csprintf("ftrace.%s", name());
200 functionTraceStream
= simout
.find(fname
);
201 if (!functionTraceStream
)
202 functionTraceStream
= simout
.create(fname
);
204 currentFunctionStart
= currentFunctionEnd
= 0;
205 functionEntryTick
= p
->function_trace_start
;
207 if (p
->function_trace_start
== 0) {
208 functionTracingEnabled
= true;
210 typedef EventWrapper
<BaseCPU
, &BaseCPU::enableFunctionTrace
> wrap
;
211 Event
*event
= new wrap(this, true);
212 schedule(event
, p
->function_trace_start
);
216 // The interrupts should always be present unless this CPU is
217 // switched in later or in case it is a checker CPU
218 if (!params()->defer_registration
&& !is_checker
) {
220 interrupts
->setCPU(this);
222 fatal("CPU %s has no interrupt controller.\n"
223 "Ensure createInterruptController() is called.\n", name());
228 if (params()->profile
)
229 profileEvent
= new ProfileEvent(this, params()->profile
);
231 tracer
= params()->tracer
;
235 BaseCPU::enableFunctionTrace()
237 functionTracingEnabled
= true;
243 delete[] comLoadEventQueue
;
244 delete[] comInstEventQueue
;
250 if (!params()->defer_registration
)
251 registerThreadContexts();
258 if (!params()->defer_registration
&& profileEvent
)
259 schedule(profileEvent
, curTick());
262 if (params()->progress_interval
) {
263 new CPUProgressEvent(this, params()->progress_interval
);
271 using namespace Stats
;
274 .name(name() + ".numCycles")
275 .desc("number of cpu cycles simulated")
279 .name(name() + ".numWorkItemsStarted")
280 .desc("number of work items this cpu started")
283 numWorkItemsCompleted
284 .name(name() + ".numWorkItemsCompleted")
285 .desc("number of work items this cpu completed")
288 int size
= threadContexts
.size();
290 for (int i
= 0; i
< size
; ++i
) {
291 stringstream namestr
;
292 ccprintf(namestr
, "%s.ctx%d", name(), i
);
293 threadContexts
[i
]->regStats(namestr
.str());
295 } else if (size
== 1)
296 threadContexts
[0]->regStats(name());
300 BaseCPU::getMasterPort(const string
&if_name
, int idx
)
302 // Get the right port based on name. This applies to all the
303 // subclasses of the base CPU and relies on their implementation
304 // of getDataPort and getInstPort. In all cases there methods
305 // return a CpuPort pointer.
306 if (if_name
== "dcache_port")
307 return getDataPort();
308 else if (if_name
== "icache_port")
309 return getInstPort();
311 return MemObject::getMasterPort(if_name
, idx
);
315 BaseCPU::registerThreadContexts()
317 ThreadID size
= threadContexts
.size();
318 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
319 ThreadContext
*tc
= threadContexts
[tid
];
321 /** This is so that contextId and cpuId match where there is a
322 * 1cpu:1context relationship. Otherwise, the order of registration
323 * could affect the assignment and cpu 1 could have context id 3, for
324 * example. We may even want to do something like this for SMT so that
325 * cpu 0 has the lowest thread contexts and cpu N has the highest, but
326 * I'll just do this for now
329 tc
->setContextId(system
->registerThreadContext(tc
, _cpuId
));
331 tc
->setContextId(system
->registerThreadContext(tc
));
334 tc
->getProcessPtr()->assignThreadContext(tc
->contextId());
340 BaseCPU::findContext(ThreadContext
*tc
)
342 ThreadID size
= threadContexts
.size();
343 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
344 if (tc
== threadContexts
[tid
])
353 if (profileEvent
&& profileEvent
->scheduled())
354 deschedule(profileEvent
);
358 BaseCPU::takeOverFrom(BaseCPU
*oldCPU
)
360 assert(threadContexts
.size() == oldCPU
->threadContexts
.size());
361 assert(_cpuId
== oldCPU
->cpuId());
363 ThreadID size
= threadContexts
.size();
364 for (ThreadID i
= 0; i
< size
; ++i
) {
365 ThreadContext
*newTC
= threadContexts
[i
];
366 ThreadContext
*oldTC
= oldCPU
->threadContexts
[i
];
368 newTC
->takeOverFrom(oldTC
);
370 CpuEvent::replaceThreadContext(oldTC
, newTC
);
372 assert(newTC
->contextId() == oldTC
->contextId());
373 assert(newTC
->threadId() == oldTC
->threadId());
374 system
->replaceThreadContext(newTC
, newTC
->contextId());
376 /* This code no longer works since the zero register (e.g.,
377 * r31 on Alpha) doesn't necessarily contain zero at this
380 ThreadContext::compare(oldTC, newTC);
383 MasterPort
*old_itb_port
= oldTC
->getITBPtr()->getMasterPort();
384 MasterPort
*old_dtb_port
= oldTC
->getDTBPtr()->getMasterPort();
385 MasterPort
*new_itb_port
= newTC
->getITBPtr()->getMasterPort();
386 MasterPort
*new_dtb_port
= newTC
->getDTBPtr()->getMasterPort();
388 // Move over any table walker ports if they exist
390 assert(!new_itb_port
->isConnected());
391 assert(old_itb_port
);
392 assert(old_itb_port
->isConnected());
393 SlavePort
&slavePort
= old_itb_port
->getSlavePort();
394 old_itb_port
->unbind();
395 new_itb_port
->bind(slavePort
);
398 assert(!new_dtb_port
->isConnected());
399 assert(old_dtb_port
);
400 assert(old_dtb_port
->isConnected());
401 SlavePort
&slavePort
= old_dtb_port
->getSlavePort();
402 old_dtb_port
->unbind();
403 new_dtb_port
->bind(slavePort
);
406 // Checker whether or not we have to transfer CheckerCPU
407 // objects over in the switch
408 CheckerCPU
*oldChecker
= oldTC
->getCheckerCpuPtr();
409 CheckerCPU
*newChecker
= newTC
->getCheckerCpuPtr();
410 if (oldChecker
&& newChecker
) {
411 MasterPort
*old_checker_itb_port
=
412 oldChecker
->getITBPtr()->getMasterPort();
413 MasterPort
*old_checker_dtb_port
=
414 oldChecker
->getDTBPtr()->getMasterPort();
415 MasterPort
*new_checker_itb_port
=
416 newChecker
->getITBPtr()->getMasterPort();
417 MasterPort
*new_checker_dtb_port
=
418 newChecker
->getDTBPtr()->getMasterPort();
420 // Move over any table walker ports if they exist for checker
421 if (new_checker_itb_port
) {
422 assert(!new_checker_itb_port
->isConnected());
423 assert(old_checker_itb_port
);
424 assert(old_checker_itb_port
->isConnected());
425 SlavePort
&slavePort
= old_checker_itb_port
->getSlavePort();
426 old_checker_itb_port
->unbind();
427 new_checker_itb_port
->bind(slavePort
);
429 if (new_checker_dtb_port
) {
430 assert(!new_checker_dtb_port
->isConnected());
431 assert(old_checker_dtb_port
);
432 assert(old_checker_dtb_port
->isConnected());
433 SlavePort
&slavePort
= old_checker_dtb_port
->getSlavePort();
434 old_checker_dtb_port
->unbind();
435 new_checker_dtb_port
->bind(slavePort
);
440 interrupts
= oldCPU
->interrupts
;
441 interrupts
->setCPU(this);
442 oldCPU
->interrupts
= NULL
;
445 for (ThreadID i
= 0; i
< size
; ++i
)
446 threadContexts
[i
]->profileClear();
449 schedule(profileEvent
, curTick());
452 // All CPUs have an instruction and a data port, and the new CPU's
453 // ports are dangling while the old CPU has its ports connected
454 // already. Unbind the old CPU and then bind the ports of the one
455 // we are switching to.
456 assert(!getInstPort().isConnected());
457 assert(oldCPU
->getInstPort().isConnected());
458 SlavePort
&inst_peer_port
= oldCPU
->getInstPort().getSlavePort();
459 oldCPU
->getInstPort().unbind();
460 getInstPort().bind(inst_peer_port
);
462 assert(!getDataPort().isConnected());
463 assert(oldCPU
->getDataPort().isConnected());
464 SlavePort
&data_peer_port
= oldCPU
->getDataPort().getSlavePort();
465 oldCPU
->getDataPort().unbind();
466 getDataPort().bind(data_peer_port
);
470 BaseCPU::ProfileEvent::ProfileEvent(BaseCPU
*_cpu
, Tick _interval
)
471 : cpu(_cpu
), interval(_interval
)
475 BaseCPU::ProfileEvent::process()
477 ThreadID size
= cpu
->threadContexts
.size();
478 for (ThreadID i
= 0; i
< size
; ++i
) {
479 ThreadContext
*tc
= cpu
->threadContexts
[i
];
483 cpu
->schedule(this, curTick() + interval
);
487 BaseCPU::serialize(std::ostream
&os
)
489 SERIALIZE_SCALAR(instCnt
);
490 interrupts
->serialize(os
);
494 BaseCPU::unserialize(Checkpoint
*cp
, const std::string
§ion
)
496 UNSERIALIZE_SCALAR(instCnt
);
497 interrupts
->unserialize(cp
, section
);
501 BaseCPU::traceFunctionsInternal(Addr pc
)
503 if (!debugSymbolTable
)
506 // if pc enters different function, print new function symbol and
507 // update saved range. Otherwise do nothing.
508 if (pc
< currentFunctionStart
|| pc
>= currentFunctionEnd
) {
510 bool found
= debugSymbolTable
->findNearestSymbol(pc
, sym_str
,
511 currentFunctionStart
,
515 // no symbol found: use addr as label
516 sym_str
= csprintf("0x%x", pc
);
517 currentFunctionStart
= pc
;
518 currentFunctionEnd
= pc
+ 1;
521 ccprintf(*functionTraceStream
, " (%d)\n%d: %s",
522 curTick() - functionEntryTick
, curTick(), sym_str
);
523 functionEntryTick
= curTick();
528 BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt
)
530 panic("BaseCPU doesn't expect recvTiming!\n");
535 BaseCPU::CpuPort::recvRetry()
537 panic("BaseCPU doesn't expect recvRetry!\n");
541 BaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt
)
543 // No internal storage to update (in the general case). A CPU with
544 // internal storage, e.g. an LSQ that should be part of the
545 // coherent memory has to check against stored data.