893b0e06b845153d2b649598b594a78db48ea9eb
2 * Copyright (c) 2011-2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
50 #include "arch/tlb.hh"
51 #include "base/loader/symtab.hh"
52 #include "base/cprintf.hh"
53 #include "base/misc.hh"
54 #include "base/output.hh"
55 #include "base/trace.hh"
56 #include "cpu/base.hh"
57 #include "cpu/checker/cpu.hh"
58 #include "cpu/cpuevent.hh"
59 #include "cpu/profile.hh"
60 #include "cpu/thread_context.hh"
61 #include "debug/SyscallVerbose.hh"
62 #include "params/BaseCPU.hh"
63 #include "sim/full_system.hh"
64 #include "sim/process.hh"
65 #include "sim/sim_events.hh"
66 #include "sim/sim_exit.hh"
67 #include "sim/system.hh"
70 #include "sim/stat_control.hh"
74 vector
<BaseCPU
*> BaseCPU::cpuList
;
76 // This variable reflects the max number of threads in any CPU. Be
77 // careful to only use it once all the CPUs that you care about have
79 int maxThreadsPerCPU
= 1;
81 CPUProgressEvent::CPUProgressEvent(BaseCPU
*_cpu
, Tick ival
)
82 : Event(Event::Progress_Event_Pri
), _interval(ival
), lastNumInst(0),
83 cpu(_cpu
), _repeatEvent(true)
86 cpu
->schedule(this, curTick() + _interval
);
90 CPUProgressEvent::process()
92 Counter temp
= cpu
->totalOps();
94 double ipc
= double(temp
- lastNumInst
) / (_interval
/ cpu
->ticks(1));
96 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
97 "%lli, IPC: %0.8d\n", cpu
->name(), temp
, temp
- lastNumInst
,
101 cprintf("%lli: %s progress event, total committed:%i, progress insts "
102 "committed: %lli\n", curTick(), cpu
->name(), temp
,
108 cpu
->schedule(this, curTick() + _interval
);
112 CPUProgressEvent::description() const
114 return "CPU Progress";
117 BaseCPU::BaseCPU(Params
*p
, bool is_checker
)
118 : MemObject(p
), clock(p
->clock
), instCnt(0), _cpuId(p
->cpu_id
),
119 _instMasterId(p
->system
->getMasterId(name() + ".inst")),
120 _dataMasterId(p
->system
->getMasterId(name() + ".data")),
121 interrupts(p
->interrupts
),
122 numThreads(p
->numThreads
), system(p
->system
),
125 // currentTick = curTick();
127 // if Python did not provide a valid ID, do it here
129 _cpuId
= cpuList
.size();
132 // add self to global list of CPUs
133 cpuList
.push_back(this);
135 DPRINTF(SyscallVerbose
, "Constructing CPU with id %d\n", _cpuId
);
137 if (numThreads
> maxThreadsPerCPU
)
138 maxThreadsPerCPU
= numThreads
;
140 // allocate per-thread instruction-based event queues
141 comInstEventQueue
= new EventQueue
*[numThreads
];
142 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
143 comInstEventQueue
[tid
] =
144 new EventQueue("instruction-based event queue");
147 // set up instruction-count-based termination events, if any
149 if (p
->max_insts_any_thread
!= 0) {
150 const char *cause
= "a thread reached the max instruction count";
151 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
152 Event
*event
= new SimLoopExitEvent(cause
, 0);
153 comInstEventQueue
[tid
]->schedule(event
, p
->max_insts_any_thread
);
157 if (p
->max_insts_all_threads
!= 0) {
158 const char *cause
= "all threads reached the max instruction count";
160 // allocate & initialize shared downcounter: each event will
161 // decrement this when triggered; simulation will terminate
162 // when counter reaches 0
163 int *counter
= new int;
164 *counter
= numThreads
;
165 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
166 Event
*event
= new CountedExitEvent(cause
, *counter
);
167 comInstEventQueue
[tid
]->schedule(event
, p
->max_insts_all_threads
);
171 // allocate per-thread load-based event queues
172 comLoadEventQueue
= new EventQueue
*[numThreads
];
173 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
174 comLoadEventQueue
[tid
] = new EventQueue("load-based event queue");
177 // set up instruction-count-based termination events, if any
179 if (p
->max_loads_any_thread
!= 0) {
180 const char *cause
= "a thread reached the max load count";
181 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
182 Event
*event
= new SimLoopExitEvent(cause
, 0);
183 comLoadEventQueue
[tid
]->schedule(event
, p
->max_loads_any_thread
);
187 if (p
->max_loads_all_threads
!= 0) {
188 const char *cause
= "all threads reached the max load count";
189 // allocate & initialize shared downcounter: each event will
190 // decrement this when triggered; simulation will terminate
191 // when counter reaches 0
192 int *counter
= new int;
193 *counter
= numThreads
;
194 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
195 Event
*event
= new CountedExitEvent(cause
, *counter
);
196 comLoadEventQueue
[tid
]->schedule(event
, p
->max_loads_all_threads
);
200 functionTracingEnabled
= false;
201 if (p
->function_trace
) {
202 const string fname
= csprintf("ftrace.%s", name());
203 functionTraceStream
= simout
.find(fname
);
204 if (!functionTraceStream
)
205 functionTraceStream
= simout
.create(fname
);
207 currentFunctionStart
= currentFunctionEnd
= 0;
208 functionEntryTick
= p
->function_trace_start
;
210 if (p
->function_trace_start
== 0) {
211 functionTracingEnabled
= true;
213 typedef EventWrapper
<BaseCPU
, &BaseCPU::enableFunctionTrace
> wrap
;
214 Event
*event
= new wrap(this, true);
215 schedule(event
, p
->function_trace_start
);
219 // The interrupts should always be present unless this CPU is
220 // switched in later or in case it is a checker CPU
221 if (!params()->defer_registration
&& !is_checker
) {
223 interrupts
->setCPU(this);
225 fatal("CPU %s has no interrupt controller.\n"
226 "Ensure createInterruptController() is called.\n", name());
232 if (params()->profile
)
233 profileEvent
= new ProfileEvent(this, params()->profile
);
235 tracer
= params()->tracer
;
239 BaseCPU::enableFunctionTrace()
241 functionTracingEnabled
= true;
247 delete[] comLoadEventQueue
;
248 delete[] comInstEventQueue
;
254 if (!params()->defer_registration
)
255 registerThreadContexts();
262 if (!params()->defer_registration
&& profileEvent
)
263 schedule(profileEvent
, curTick());
266 if (params()->progress_interval
) {
267 Tick num_ticks
= ticks(params()->progress_interval
);
269 new CPUProgressEvent(this, num_ticks
);
277 using namespace Stats
;
280 .name(name() + ".numCycles")
281 .desc("number of cpu cycles simulated")
285 .name(name() + ".numWorkItemsStarted")
286 .desc("number of work items this cpu started")
289 numWorkItemsCompleted
290 .name(name() + ".numWorkItemsCompleted")
291 .desc("number of work items this cpu completed")
294 int size
= threadContexts
.size();
296 for (int i
= 0; i
< size
; ++i
) {
297 stringstream namestr
;
298 ccprintf(namestr
, "%s.ctx%d", name(), i
);
299 threadContexts
[i
]->regStats(namestr
.str());
301 } else if (size
== 1)
302 threadContexts
[0]->regStats(name());
306 BaseCPU::getMasterPort(const string
&if_name
, int idx
)
308 // Get the right port based on name. This applies to all the
309 // subclasses of the base CPU and relies on their implementation
310 // of getDataPort and getInstPort. In all cases there methods
311 // return a CpuPort pointer.
312 if (if_name
== "dcache_port")
313 return getDataPort();
314 else if (if_name
== "icache_port")
315 return getInstPort();
317 return MemObject::getMasterPort(if_name
, idx
);
323 Tick next_tick
= curTick() - phase
+ clock
- 1;
324 next_tick
-= (next_tick
% clock
);
330 BaseCPU::nextCycle(Tick begin_tick
)
332 Tick next_tick
= begin_tick
;
333 if (next_tick
% clock
!= 0)
334 next_tick
= next_tick
- (next_tick
% clock
) + clock
;
337 assert(next_tick
>= curTick());
342 BaseCPU::registerThreadContexts()
344 ThreadID size
= threadContexts
.size();
345 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
346 ThreadContext
*tc
= threadContexts
[tid
];
348 /** This is so that contextId and cpuId match where there is a
349 * 1cpu:1context relationship. Otherwise, the order of registration
350 * could affect the assignment and cpu 1 could have context id 3, for
351 * example. We may even want to do something like this for SMT so that
352 * cpu 0 has the lowest thread contexts and cpu N has the highest, but
353 * I'll just do this for now
356 tc
->setContextId(system
->registerThreadContext(tc
, _cpuId
));
358 tc
->setContextId(system
->registerThreadContext(tc
));
361 tc
->getProcessPtr()->assignThreadContext(tc
->contextId());
367 BaseCPU::findContext(ThreadContext
*tc
)
369 ThreadID size
= threadContexts
.size();
370 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
371 if (tc
== threadContexts
[tid
])
380 if (profileEvent
&& profileEvent
->scheduled())
381 deschedule(profileEvent
);
385 BaseCPU::takeOverFrom(BaseCPU
*oldCPU
)
387 assert(threadContexts
.size() == oldCPU
->threadContexts
.size());
388 assert(_cpuId
== oldCPU
->cpuId());
390 ThreadID size
= threadContexts
.size();
391 for (ThreadID i
= 0; i
< size
; ++i
) {
392 ThreadContext
*newTC
= threadContexts
[i
];
393 ThreadContext
*oldTC
= oldCPU
->threadContexts
[i
];
395 newTC
->takeOverFrom(oldTC
);
397 CpuEvent::replaceThreadContext(oldTC
, newTC
);
399 assert(newTC
->contextId() == oldTC
->contextId());
400 assert(newTC
->threadId() == oldTC
->threadId());
401 system
->replaceThreadContext(newTC
, newTC
->contextId());
403 /* This code no longer works since the zero register (e.g.,
404 * r31 on Alpha) doesn't necessarily contain zero at this
407 ThreadContext::compare(oldTC, newTC);
410 MasterPort
*old_itb_port
= oldTC
->getITBPtr()->getMasterPort();
411 MasterPort
*old_dtb_port
= oldTC
->getDTBPtr()->getMasterPort();
412 MasterPort
*new_itb_port
= newTC
->getITBPtr()->getMasterPort();
413 MasterPort
*new_dtb_port
= newTC
->getDTBPtr()->getMasterPort();
415 // Move over any table walker ports if they exist
416 if (new_itb_port
&& !new_itb_port
->isConnected()) {
417 assert(old_itb_port
);
418 SlavePort
&slavePort
= old_itb_port
->getSlavePort();
419 new_itb_port
->bind(slavePort
);
420 old_itb_port
->unBind();
422 if (new_dtb_port
&& !new_dtb_port
->isConnected()) {
423 assert(old_dtb_port
);
424 SlavePort
&slavePort
= old_dtb_port
->getSlavePort();
425 new_dtb_port
->bind(slavePort
);
426 old_dtb_port
->unBind();
429 // Checker whether or not we have to transfer CheckerCPU
430 // objects over in the switch
431 CheckerCPU
*oldChecker
= oldTC
->getCheckerCpuPtr();
432 CheckerCPU
*newChecker
= newTC
->getCheckerCpuPtr();
433 if (oldChecker
&& newChecker
) {
434 MasterPort
*old_checker_itb_port
=
435 oldChecker
->getITBPtr()->getMasterPort();
436 MasterPort
*old_checker_dtb_port
=
437 oldChecker
->getDTBPtr()->getMasterPort();
438 MasterPort
*new_checker_itb_port
=
439 newChecker
->getITBPtr()->getMasterPort();
440 MasterPort
*new_checker_dtb_port
=
441 newChecker
->getDTBPtr()->getMasterPort();
443 // Move over any table walker ports if they exist for checker
444 if (new_checker_itb_port
&& !new_checker_itb_port
->isConnected()) {
445 assert(old_checker_itb_port
);
446 SlavePort
&slavePort
= old_checker_itb_port
->getSlavePort();;
447 new_checker_itb_port
->bind(slavePort
);
448 old_checker_itb_port
->unBind();
450 if (new_checker_dtb_port
&& !new_checker_dtb_port
->isConnected()) {
451 assert(old_checker_dtb_port
);
452 SlavePort
&slavePort
= old_checker_dtb_port
->getSlavePort();;
453 new_checker_dtb_port
->bind(slavePort
);
454 old_checker_dtb_port
->unBind();
459 interrupts
= oldCPU
->interrupts
;
460 interrupts
->setCPU(this);
461 oldCPU
->interrupts
= NULL
;
464 for (ThreadID i
= 0; i
< size
; ++i
)
465 threadContexts
[i
]->profileClear();
468 schedule(profileEvent
, curTick());
471 // Connect new CPU to old CPU's memory only if new CPU isn't
472 // connected to anything. Also connect old CPU's memory to new
474 if (!getInstPort().isConnected()) {
475 getInstPort().bind(oldCPU
->getInstPort().getSlavePort());
476 oldCPU
->getInstPort().unBind();
479 if (!getDataPort().isConnected()) {
480 getDataPort().bind(oldCPU
->getDataPort().getSlavePort());
481 oldCPU
->getDataPort().unBind();
486 BaseCPU::ProfileEvent::ProfileEvent(BaseCPU
*_cpu
, Tick _interval
)
487 : cpu(_cpu
), interval(_interval
)
491 BaseCPU::ProfileEvent::process()
493 ThreadID size
= cpu
->threadContexts
.size();
494 for (ThreadID i
= 0; i
< size
; ++i
) {
495 ThreadContext
*tc
= cpu
->threadContexts
[i
];
499 cpu
->schedule(this, curTick() + interval
);
503 BaseCPU::serialize(std::ostream
&os
)
505 SERIALIZE_SCALAR(instCnt
);
506 interrupts
->serialize(os
);
510 BaseCPU::unserialize(Checkpoint
*cp
, const std::string
§ion
)
512 UNSERIALIZE_SCALAR(instCnt
);
513 interrupts
->unserialize(cp
, section
);
517 BaseCPU::traceFunctionsInternal(Addr pc
)
519 if (!debugSymbolTable
)
522 // if pc enters different function, print new function symbol and
523 // update saved range. Otherwise do nothing.
524 if (pc
< currentFunctionStart
|| pc
>= currentFunctionEnd
) {
526 bool found
= debugSymbolTable
->findNearestSymbol(pc
, sym_str
,
527 currentFunctionStart
,
531 // no symbol found: use addr as label
532 sym_str
= csprintf("0x%x", pc
);
533 currentFunctionStart
= pc
;
534 currentFunctionEnd
= pc
+ 1;
537 ccprintf(*functionTraceStream
, " (%d)\n%d: %s",
538 curTick() - functionEntryTick
, curTick(), sym_str
);
539 functionEntryTick
= curTick();
544 BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt
)
546 panic("BaseCPU doesn't expect recvTiming!\n");
551 BaseCPU::CpuPort::recvRetry()
553 panic("BaseCPU doesn't expect recvRetry!\n");
557 BaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt
)
559 // No internal storage to update (in the general case). A CPU with
560 // internal storage, e.g. an LSQ that should be part of the
561 // coherent memory has to check against stored data.