2 * Copyright (c) 2011-2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * Copyright (c) 2013 Advanced Micro Devices, Inc.
17 * Copyright (c) 2013 Mark D. Hill and David A. Wood
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are
22 * met: redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer;
24 * redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution;
27 * neither the name of the copyright holders nor the names of its
28 * contributors may be used to endorse or promote products derived from
29 * this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * Authors: Steve Reinhardt
52 #include "arch/tlb.hh"
53 #include "base/loader/symtab.hh"
54 #include "base/cprintf.hh"
55 #include "base/misc.hh"
56 #include "base/output.hh"
57 #include "base/trace.hh"
58 #include "cpu/base.hh"
59 #include "cpu/checker/cpu.hh"
60 #include "cpu/cpuevent.hh"
61 #include "cpu/profile.hh"
62 #include "cpu/thread_context.hh"
63 #include "debug/SyscallVerbose.hh"
64 #include "params/BaseCPU.hh"
65 #include "sim/full_system.hh"
66 #include "sim/process.hh"
67 #include "sim/sim_events.hh"
68 #include "sim/sim_exit.hh"
69 #include "sim/system.hh"
72 #include "sim/stat_control.hh"
76 vector
<BaseCPU
*> BaseCPU::cpuList
;
78 // This variable reflects the max number of threads in any CPU. Be
79 // careful to only use it once all the CPUs that you care about have
81 int maxThreadsPerCPU
= 1;
83 CPUProgressEvent::CPUProgressEvent(BaseCPU
*_cpu
, Tick ival
)
84 : Event(Event::Progress_Event_Pri
), _interval(ival
), lastNumInst(0),
85 cpu(_cpu
), _repeatEvent(true)
88 cpu
->schedule(this, curTick() + _interval
);
92 CPUProgressEvent::process()
94 Counter temp
= cpu
->totalOps();
96 double ipc
= double(temp
- lastNumInst
) / (_interval
/ cpu
->clockPeriod());
98 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
99 "%lli, IPC: %0.8d\n", cpu
->name(), temp
, temp
- lastNumInst
,
103 cprintf("%lli: %s progress event, total committed:%i, progress insts "
104 "committed: %lli\n", curTick(), cpu
->name(), temp
,
110 cpu
->schedule(this, curTick() + _interval
);
114 CPUProgressEvent::description() const
116 return "CPU Progress";
119 BaseCPU::BaseCPU(Params
*p
, bool is_checker
)
120 : MemObject(p
), instCnt(0), _cpuId(p
->cpu_id
), _socketId(p
->socket_id
),
121 _instMasterId(p
->system
->getMasterId(name() + ".inst")),
122 _dataMasterId(p
->system
->getMasterId(name() + ".data")),
123 _taskId(ContextSwitchTaskId::Unknown
), _pid(Request::invldPid
),
124 _switchedOut(p
->switched_out
), _cacheLineSize(p
->system
->cacheLineSize()),
125 interrupts(p
->interrupts
), profileEvent(NULL
),
126 numThreads(p
->numThreads
), system(p
->system
)
128 // if Python did not provide a valid ID, do it here
130 _cpuId
= cpuList
.size();
133 // add self to global list of CPUs
134 cpuList
.push_back(this);
136 DPRINTF(SyscallVerbose
, "Constructing CPU with id %d, socket id %d\n",
139 if (numThreads
> maxThreadsPerCPU
)
140 maxThreadsPerCPU
= numThreads
;
142 // allocate per-thread instruction-based event queues
143 comInstEventQueue
= new EventQueue
*[numThreads
];
144 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
145 comInstEventQueue
[tid
] =
146 new EventQueue("instruction-based event queue");
149 // set up instruction-count-based termination events, if any
151 if (p
->max_insts_any_thread
!= 0) {
152 const char *cause
= "a thread reached the max instruction count";
153 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
154 scheduleInstStop(tid
, p
->max_insts_any_thread
, cause
);
157 // Set up instruction-count-based termination events for SimPoints
158 // Typically, there are more than one action points.
159 // Simulation.py is responsible to take the necessary actions upon
160 // exitting the simulation loop.
161 if (!p
->simpoint_start_insts
.empty()) {
162 const char *cause
= "simpoint starting point found";
163 for (size_t i
= 0; i
< p
->simpoint_start_insts
.size(); ++i
)
164 scheduleInstStop(0, p
->simpoint_start_insts
[i
], cause
);
167 if (p
->max_insts_all_threads
!= 0) {
168 const char *cause
= "all threads reached the max instruction count";
170 // allocate & initialize shared downcounter: each event will
171 // decrement this when triggered; simulation will terminate
172 // when counter reaches 0
173 int *counter
= new int;
174 *counter
= numThreads
;
175 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
176 Event
*event
= new CountedExitEvent(cause
, *counter
);
177 comInstEventQueue
[tid
]->schedule(event
, p
->max_insts_all_threads
);
181 // allocate per-thread load-based event queues
182 comLoadEventQueue
= new EventQueue
*[numThreads
];
183 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
184 comLoadEventQueue
[tid
] = new EventQueue("load-based event queue");
187 // set up instruction-count-based termination events, if any
189 if (p
->max_loads_any_thread
!= 0) {
190 const char *cause
= "a thread reached the max load count";
191 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
192 scheduleLoadStop(tid
, p
->max_loads_any_thread
, cause
);
195 if (p
->max_loads_all_threads
!= 0) {
196 const char *cause
= "all threads reached the max load count";
197 // allocate & initialize shared downcounter: each event will
198 // decrement this when triggered; simulation will terminate
199 // when counter reaches 0
200 int *counter
= new int;
201 *counter
= numThreads
;
202 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
203 Event
*event
= new CountedExitEvent(cause
, *counter
);
204 comLoadEventQueue
[tid
]->schedule(event
, p
->max_loads_all_threads
);
208 functionTracingEnabled
= false;
209 if (p
->function_trace
) {
210 const string fname
= csprintf("ftrace.%s", name());
211 functionTraceStream
= simout
.find(fname
);
212 if (!functionTraceStream
)
213 functionTraceStream
= simout
.create(fname
);
215 currentFunctionStart
= currentFunctionEnd
= 0;
216 functionEntryTick
= p
->function_trace_start
;
218 if (p
->function_trace_start
== 0) {
219 functionTracingEnabled
= true;
221 typedef EventWrapper
<BaseCPU
, &BaseCPU::enableFunctionTrace
> wrap
;
222 Event
*event
= new wrap(this, true);
223 schedule(event
, p
->function_trace_start
);
227 // The interrupts should always be present unless this CPU is
228 // switched in later or in case it is a checker CPU
229 if (!params()->switched_out
&& !is_checker
) {
231 interrupts
->setCPU(this);
233 fatal("CPU %s has no interrupt controller.\n"
234 "Ensure createInterruptController() is called.\n", name());
239 if (params()->profile
)
240 profileEvent
= new ProfileEvent(this, params()->profile
);
242 tracer
= params()->tracer
;
244 if (params()->isa
.size() != numThreads
) {
245 fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
246 "of threads (%i).\n", params()->isa
.size(), numThreads
);
251 BaseCPU::enableFunctionTrace()
253 functionTracingEnabled
= true;
259 delete[] comLoadEventQueue
;
260 delete[] comInstEventQueue
;
266 if (!params()->switched_out
) {
267 registerThreadContexts();
277 if (!params()->switched_out
&& profileEvent
)
278 schedule(profileEvent
, curTick());
281 if (params()->progress_interval
) {
282 new CPUProgressEvent(this, params()->progress_interval
);
290 using namespace Stats
;
293 .name(name() + ".numCycles")
294 .desc("number of cpu cycles simulated")
298 .name(name() + ".numWorkItemsStarted")
299 .desc("number of work items this cpu started")
302 numWorkItemsCompleted
303 .name(name() + ".numWorkItemsCompleted")
304 .desc("number of work items this cpu completed")
307 int size
= threadContexts
.size();
309 for (int i
= 0; i
< size
; ++i
) {
310 stringstream namestr
;
311 ccprintf(namestr
, "%s.ctx%d", name(), i
);
312 threadContexts
[i
]->regStats(namestr
.str());
314 } else if (size
== 1)
315 threadContexts
[0]->regStats(name());
319 BaseCPU::getMasterPort(const string
&if_name
, PortID idx
)
321 // Get the right port based on name. This applies to all the
322 // subclasses of the base CPU and relies on their implementation
323 // of getDataPort and getInstPort. In all cases there methods
324 // return a MasterPort pointer.
325 if (if_name
== "dcache_port")
326 return getDataPort();
327 else if (if_name
== "icache_port")
328 return getInstPort();
330 return MemObject::getMasterPort(if_name
, idx
);
334 BaseCPU::registerThreadContexts()
336 ThreadID size
= threadContexts
.size();
337 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
338 ThreadContext
*tc
= threadContexts
[tid
];
340 /** This is so that contextId and cpuId match where there is a
341 * 1cpu:1context relationship. Otherwise, the order of registration
342 * could affect the assignment and cpu 1 could have context id 3, for
343 * example. We may even want to do something like this for SMT so that
344 * cpu 0 has the lowest thread contexts and cpu N has the highest, but
345 * I'll just do this for now
348 tc
->setContextId(system
->registerThreadContext(tc
, _cpuId
));
350 tc
->setContextId(system
->registerThreadContext(tc
));
353 tc
->getProcessPtr()->assignThreadContext(tc
->contextId());
359 BaseCPU::findContext(ThreadContext
*tc
)
361 ThreadID size
= threadContexts
.size();
362 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
363 if (tc
== threadContexts
[tid
])
372 assert(!_switchedOut
);
374 if (profileEvent
&& profileEvent
->scheduled())
375 deschedule(profileEvent
);
377 // Flush all TLBs in the CPU to avoid having stale translations if
378 // it gets switched in later.
383 BaseCPU::takeOverFrom(BaseCPU
*oldCPU
)
385 assert(threadContexts
.size() == oldCPU
->threadContexts
.size());
386 assert(_cpuId
== oldCPU
->cpuId());
387 assert(_switchedOut
);
388 assert(oldCPU
!= this);
389 _pid
= oldCPU
->getPid();
390 _taskId
= oldCPU
->taskId();
391 _switchedOut
= false;
393 ThreadID size
= threadContexts
.size();
394 for (ThreadID i
= 0; i
< size
; ++i
) {
395 ThreadContext
*newTC
= threadContexts
[i
];
396 ThreadContext
*oldTC
= oldCPU
->threadContexts
[i
];
398 newTC
->takeOverFrom(oldTC
);
400 CpuEvent::replaceThreadContext(oldTC
, newTC
);
402 assert(newTC
->contextId() == oldTC
->contextId());
403 assert(newTC
->threadId() == oldTC
->threadId());
404 system
->replaceThreadContext(newTC
, newTC
->contextId());
406 /* This code no longer works since the zero register (e.g.,
407 * r31 on Alpha) doesn't necessarily contain zero at this
410 ThreadContext::compare(oldTC, newTC);
413 BaseMasterPort
*old_itb_port
= oldTC
->getITBPtr()->getMasterPort();
414 BaseMasterPort
*old_dtb_port
= oldTC
->getDTBPtr()->getMasterPort();
415 BaseMasterPort
*new_itb_port
= newTC
->getITBPtr()->getMasterPort();
416 BaseMasterPort
*new_dtb_port
= newTC
->getDTBPtr()->getMasterPort();
418 // Move over any table walker ports if they exist
420 assert(!new_itb_port
->isConnected());
421 assert(old_itb_port
);
422 assert(old_itb_port
->isConnected());
423 BaseSlavePort
&slavePort
= old_itb_port
->getSlavePort();
424 old_itb_port
->unbind();
425 new_itb_port
->bind(slavePort
);
428 assert(!new_dtb_port
->isConnected());
429 assert(old_dtb_port
);
430 assert(old_dtb_port
->isConnected());
431 BaseSlavePort
&slavePort
= old_dtb_port
->getSlavePort();
432 old_dtb_port
->unbind();
433 new_dtb_port
->bind(slavePort
);
435 newTC
->getITBPtr()->takeOverFrom(oldTC
->getITBPtr());
436 newTC
->getDTBPtr()->takeOverFrom(oldTC
->getDTBPtr());
438 // Checker whether or not we have to transfer CheckerCPU
439 // objects over in the switch
440 CheckerCPU
*oldChecker
= oldTC
->getCheckerCpuPtr();
441 CheckerCPU
*newChecker
= newTC
->getCheckerCpuPtr();
442 if (oldChecker
&& newChecker
) {
443 BaseMasterPort
*old_checker_itb_port
=
444 oldChecker
->getITBPtr()->getMasterPort();
445 BaseMasterPort
*old_checker_dtb_port
=
446 oldChecker
->getDTBPtr()->getMasterPort();
447 BaseMasterPort
*new_checker_itb_port
=
448 newChecker
->getITBPtr()->getMasterPort();
449 BaseMasterPort
*new_checker_dtb_port
=
450 newChecker
->getDTBPtr()->getMasterPort();
452 newChecker
->getITBPtr()->takeOverFrom(oldChecker
->getITBPtr());
453 newChecker
->getDTBPtr()->takeOverFrom(oldChecker
->getDTBPtr());
455 // Move over any table walker ports if they exist for checker
456 if (new_checker_itb_port
) {
457 assert(!new_checker_itb_port
->isConnected());
458 assert(old_checker_itb_port
);
459 assert(old_checker_itb_port
->isConnected());
460 BaseSlavePort
&slavePort
=
461 old_checker_itb_port
->getSlavePort();
462 old_checker_itb_port
->unbind();
463 new_checker_itb_port
->bind(slavePort
);
465 if (new_checker_dtb_port
) {
466 assert(!new_checker_dtb_port
->isConnected());
467 assert(old_checker_dtb_port
);
468 assert(old_checker_dtb_port
->isConnected());
469 BaseSlavePort
&slavePort
=
470 old_checker_dtb_port
->getSlavePort();
471 old_checker_dtb_port
->unbind();
472 new_checker_dtb_port
->bind(slavePort
);
477 interrupts
= oldCPU
->interrupts
;
478 interrupts
->setCPU(this);
479 oldCPU
->interrupts
= NULL
;
482 for (ThreadID i
= 0; i
< size
; ++i
)
483 threadContexts
[i
]->profileClear();
486 schedule(profileEvent
, curTick());
489 // All CPUs have an instruction and a data port, and the new CPU's
490 // ports are dangling while the old CPU has its ports connected
491 // already. Unbind the old CPU and then bind the ports of the one
492 // we are switching to.
493 assert(!getInstPort().isConnected());
494 assert(oldCPU
->getInstPort().isConnected());
495 BaseSlavePort
&inst_peer_port
= oldCPU
->getInstPort().getSlavePort();
496 oldCPU
->getInstPort().unbind();
497 getInstPort().bind(inst_peer_port
);
499 assert(!getDataPort().isConnected());
500 assert(oldCPU
->getDataPort().isConnected());
501 BaseSlavePort
&data_peer_port
= oldCPU
->getDataPort().getSlavePort();
502 oldCPU
->getDataPort().unbind();
503 getDataPort().bind(data_peer_port
);
509 for (ThreadID i
= 0; i
< threadContexts
.size(); ++i
) {
510 ThreadContext
&tc(*threadContexts
[i
]);
511 CheckerCPU
*checker(tc
.getCheckerCpuPtr());
513 tc
.getITBPtr()->flushAll();
514 tc
.getDTBPtr()->flushAll();
516 checker
->getITBPtr()->flushAll();
517 checker
->getDTBPtr()->flushAll();
523 BaseCPU::ProfileEvent::ProfileEvent(BaseCPU
*_cpu
, Tick _interval
)
524 : cpu(_cpu
), interval(_interval
)
528 BaseCPU::ProfileEvent::process()
530 ThreadID size
= cpu
->threadContexts
.size();
531 for (ThreadID i
= 0; i
< size
; ++i
) {
532 ThreadContext
*tc
= cpu
->threadContexts
[i
];
536 cpu
->schedule(this, curTick() + interval
);
540 BaseCPU::serialize(std::ostream
&os
)
542 SERIALIZE_SCALAR(instCnt
);
545 /* Unlike _pid, _taskId is not serialized, as they are dynamically
546 * assigned unique ids that are only meaningful for the duration of
547 * a specific run. We will need to serialize the entire taskMap in
549 SERIALIZE_SCALAR(_pid
);
551 interrupts
->serialize(os
);
553 // Serialize the threads, this is done by the CPU implementation.
554 for (ThreadID i
= 0; i
< numThreads
; ++i
) {
555 nameOut(os
, csprintf("%s.xc.%i", name(), i
));
556 serializeThread(os
, i
);
562 BaseCPU::unserialize(Checkpoint
*cp
, const std::string
§ion
)
564 UNSERIALIZE_SCALAR(instCnt
);
567 UNSERIALIZE_SCALAR(_pid
);
568 interrupts
->unserialize(cp
, section
);
570 // Unserialize the threads, this is done by the CPU implementation.
571 for (ThreadID i
= 0; i
< numThreads
; ++i
)
572 unserializeThread(cp
, csprintf("%s.xc.%i", section
, i
), i
);
577 BaseCPU::scheduleInstStop(ThreadID tid
, Counter insts
, const char *cause
)
579 const Tick
now(comInstEventQueue
[tid
]->getCurTick());
580 Event
*event(new LocalSimLoopExitEvent(cause
, 0));
582 comInstEventQueue
[tid
]->schedule(event
, now
+ insts
);
586 BaseCPU::scheduleLoadStop(ThreadID tid
, Counter loads
, const char *cause
)
588 const Tick
now(comLoadEventQueue
[tid
]->getCurTick());
589 Event
*event(new LocalSimLoopExitEvent(cause
, 0));
591 comLoadEventQueue
[tid
]->schedule(event
, now
+ loads
);
596 BaseCPU::traceFunctionsInternal(Addr pc
)
598 if (!debugSymbolTable
)
601 // if pc enters different function, print new function symbol and
602 // update saved range. Otherwise do nothing.
603 if (pc
< currentFunctionStart
|| pc
>= currentFunctionEnd
) {
605 bool found
= debugSymbolTable
->findNearestSymbol(pc
, sym_str
,
606 currentFunctionStart
,
610 // no symbol found: use addr as label
611 sym_str
= csprintf("0x%x", pc
);
612 currentFunctionStart
= pc
;
613 currentFunctionEnd
= pc
+ 1;
616 ccprintf(*functionTraceStream
, " (%d)\n%d: %s",
617 curTick() - functionEntryTick
, curTick(), sym_str
);
618 functionEntryTick
= curTick();