2 * Copyright (c) 2011-2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
50 #include "arch/tlb.hh"
51 #include "base/loader/symtab.hh"
52 #include "base/cprintf.hh"
53 #include "base/misc.hh"
54 #include "base/output.hh"
55 #include "base/trace.hh"
56 #include "cpu/base.hh"
57 #include "cpu/checker/cpu.hh"
58 #include "cpu/cpuevent.hh"
59 #include "cpu/profile.hh"
60 #include "cpu/thread_context.hh"
61 #include "debug/SyscallVerbose.hh"
62 #include "params/BaseCPU.hh"
63 #include "sim/full_system.hh"
64 #include "sim/process.hh"
65 #include "sim/sim_events.hh"
66 #include "sim/sim_exit.hh"
67 #include "sim/system.hh"
70 #include "sim/stat_control.hh"
74 vector
<BaseCPU
*> BaseCPU::cpuList
;
76 // This variable reflects the max number of threads in any CPU. Be
77 // careful to only use it once all the CPUs that you care about have
79 int maxThreadsPerCPU
= 1;
81 CPUProgressEvent::CPUProgressEvent(BaseCPU
*_cpu
, Tick ival
)
82 : Event(Event::Progress_Event_Pri
), _interval(ival
), lastNumInst(0),
83 cpu(_cpu
), _repeatEvent(true)
86 cpu
->schedule(this, curTick() + _interval
);
90 CPUProgressEvent::process()
92 Counter temp
= cpu
->totalOps();
94 double ipc
= double(temp
- lastNumInst
) / (_interval
/ cpu
->clockPeriod());
96 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
97 "%lli, IPC: %0.8d\n", cpu
->name(), temp
, temp
- lastNumInst
,
101 cprintf("%lli: %s progress event, total committed:%i, progress insts "
102 "committed: %lli\n", curTick(), cpu
->name(), temp
,
108 cpu
->schedule(this, curTick() + _interval
);
112 CPUProgressEvent::description() const
114 return "CPU Progress";
117 BaseCPU::BaseCPU(Params
*p
, bool is_checker
)
118 : MemObject(p
), instCnt(0), _cpuId(p
->cpu_id
),
119 _instMasterId(p
->system
->getMasterId(name() + ".inst")),
120 _dataMasterId(p
->system
->getMasterId(name() + ".data")),
121 _taskId(ContextSwitchTaskId::Unknown
), _pid(Request::invldPid
),
122 _switchedOut(p
->switched_out
),
123 interrupts(p
->interrupts
), profileEvent(NULL
),
124 numThreads(p
->numThreads
), system(p
->system
)
126 // if Python did not provide a valid ID, do it here
128 _cpuId
= cpuList
.size();
131 // add self to global list of CPUs
132 cpuList
.push_back(this);
134 DPRINTF(SyscallVerbose
, "Constructing CPU with id %d\n", _cpuId
);
136 if (numThreads
> maxThreadsPerCPU
)
137 maxThreadsPerCPU
= numThreads
;
139 // allocate per-thread instruction-based event queues
140 comInstEventQueue
= new EventQueue
*[numThreads
];
141 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
142 comInstEventQueue
[tid
] =
143 new EventQueue("instruction-based event queue");
146 // set up instruction-count-based termination events, if any
148 if (p
->max_insts_any_thread
!= 0) {
149 const char *cause
= "a thread reached the max instruction count";
150 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
151 Event
*event
= new SimLoopExitEvent(cause
, 0);
152 comInstEventQueue
[tid
]->schedule(event
, p
->max_insts_any_thread
);
156 // Set up instruction-count-based termination events for SimPoints
157 // Typically, there are more than one action points.
158 // Simulation.py is responsible to take the necessary actions upon
159 // exitting the simulation loop.
160 if (!p
->simpoint_start_insts
.empty()) {
161 const char *cause
= "simpoint starting point found";
162 for (size_t i
= 0; i
< p
->simpoint_start_insts
.size(); ++i
) {
163 Event
*event
= new SimLoopExitEvent(cause
, 0);
164 comInstEventQueue
[0]->schedule(event
, p
->simpoint_start_insts
[i
]);
168 if (p
->max_insts_all_threads
!= 0) {
169 const char *cause
= "all threads reached the max instruction count";
171 // allocate & initialize shared downcounter: each event will
172 // decrement this when triggered; simulation will terminate
173 // when counter reaches 0
174 int *counter
= new int;
175 *counter
= numThreads
;
176 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
177 Event
*event
= new CountedExitEvent(cause
, *counter
);
178 comInstEventQueue
[tid
]->schedule(event
, p
->max_insts_all_threads
);
182 // allocate per-thread load-based event queues
183 comLoadEventQueue
= new EventQueue
*[numThreads
];
184 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
185 comLoadEventQueue
[tid
] = new EventQueue("load-based event queue");
188 // set up instruction-count-based termination events, if any
190 if (p
->max_loads_any_thread
!= 0) {
191 const char *cause
= "a thread reached the max load count";
192 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
193 Event
*event
= new SimLoopExitEvent(cause
, 0);
194 comLoadEventQueue
[tid
]->schedule(event
, p
->max_loads_any_thread
);
198 if (p
->max_loads_all_threads
!= 0) {
199 const char *cause
= "all threads reached the max load count";
200 // allocate & initialize shared downcounter: each event will
201 // decrement this when triggered; simulation will terminate
202 // when counter reaches 0
203 int *counter
= new int;
204 *counter
= numThreads
;
205 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
206 Event
*event
= new CountedExitEvent(cause
, *counter
);
207 comLoadEventQueue
[tid
]->schedule(event
, p
->max_loads_all_threads
);
211 functionTracingEnabled
= false;
212 if (p
->function_trace
) {
213 const string fname
= csprintf("ftrace.%s", name());
214 functionTraceStream
= simout
.find(fname
);
215 if (!functionTraceStream
)
216 functionTraceStream
= simout
.create(fname
);
218 currentFunctionStart
= currentFunctionEnd
= 0;
219 functionEntryTick
= p
->function_trace_start
;
221 if (p
->function_trace_start
== 0) {
222 functionTracingEnabled
= true;
224 typedef EventWrapper
<BaseCPU
, &BaseCPU::enableFunctionTrace
> wrap
;
225 Event
*event
= new wrap(this, true);
226 schedule(event
, p
->function_trace_start
);
230 // The interrupts should always be present unless this CPU is
231 // switched in later or in case it is a checker CPU
232 if (!params()->switched_out
&& !is_checker
) {
234 interrupts
->setCPU(this);
236 fatal("CPU %s has no interrupt controller.\n"
237 "Ensure createInterruptController() is called.\n", name());
242 if (params()->profile
)
243 profileEvent
= new ProfileEvent(this, params()->profile
);
245 tracer
= params()->tracer
;
247 if (params()->isa
.size() != numThreads
) {
248 fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
249 "of threads (%i).\n", params()->isa
.size(), numThreads
);
254 BaseCPU::enableFunctionTrace()
256 functionTracingEnabled
= true;
262 delete[] comLoadEventQueue
;
263 delete[] comInstEventQueue
;
269 if (!params()->switched_out
) {
270 registerThreadContexts();
280 if (!params()->switched_out
&& profileEvent
)
281 schedule(profileEvent
, curTick());
284 if (params()->progress_interval
) {
285 new CPUProgressEvent(this, params()->progress_interval
);
293 using namespace Stats
;
296 .name(name() + ".numCycles")
297 .desc("number of cpu cycles simulated")
301 .name(name() + ".numWorkItemsStarted")
302 .desc("number of work items this cpu started")
305 numWorkItemsCompleted
306 .name(name() + ".numWorkItemsCompleted")
307 .desc("number of work items this cpu completed")
310 int size
= threadContexts
.size();
312 for (int i
= 0; i
< size
; ++i
) {
313 stringstream namestr
;
314 ccprintf(namestr
, "%s.ctx%d", name(), i
);
315 threadContexts
[i
]->regStats(namestr
.str());
317 } else if (size
== 1)
318 threadContexts
[0]->regStats(name());
322 BaseCPU::getMasterPort(const string
&if_name
, PortID idx
)
324 // Get the right port based on name. This applies to all the
325 // subclasses of the base CPU and relies on their implementation
326 // of getDataPort and getInstPort. In all cases there methods
327 // return a MasterPort pointer.
328 if (if_name
== "dcache_port")
329 return getDataPort();
330 else if (if_name
== "icache_port")
331 return getInstPort();
333 return MemObject::getMasterPort(if_name
, idx
);
337 BaseCPU::registerThreadContexts()
339 ThreadID size
= threadContexts
.size();
340 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
341 ThreadContext
*tc
= threadContexts
[tid
];
343 /** This is so that contextId and cpuId match where there is a
344 * 1cpu:1context relationship. Otherwise, the order of registration
345 * could affect the assignment and cpu 1 could have context id 3, for
346 * example. We may even want to do something like this for SMT so that
347 * cpu 0 has the lowest thread contexts and cpu N has the highest, but
348 * I'll just do this for now
351 tc
->setContextId(system
->registerThreadContext(tc
, _cpuId
));
353 tc
->setContextId(system
->registerThreadContext(tc
));
356 tc
->getProcessPtr()->assignThreadContext(tc
->contextId());
362 BaseCPU::findContext(ThreadContext
*tc
)
364 ThreadID size
= threadContexts
.size();
365 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
366 if (tc
== threadContexts
[tid
])
375 assert(!_switchedOut
);
377 if (profileEvent
&& profileEvent
->scheduled())
378 deschedule(profileEvent
);
380 // Flush all TLBs in the CPU to avoid having stale translations if
381 // it gets switched in later.
386 BaseCPU::takeOverFrom(BaseCPU
*oldCPU
)
388 assert(threadContexts
.size() == oldCPU
->threadContexts
.size());
389 assert(_cpuId
== oldCPU
->cpuId());
390 assert(_switchedOut
);
391 assert(oldCPU
!= this);
392 _pid
= oldCPU
->getPid();
393 _taskId
= oldCPU
->taskId();
394 _switchedOut
= false;
396 ThreadID size
= threadContexts
.size();
397 for (ThreadID i
= 0; i
< size
; ++i
) {
398 ThreadContext
*newTC
= threadContexts
[i
];
399 ThreadContext
*oldTC
= oldCPU
->threadContexts
[i
];
401 newTC
->takeOverFrom(oldTC
);
403 CpuEvent::replaceThreadContext(oldTC
, newTC
);
405 assert(newTC
->contextId() == oldTC
->contextId());
406 assert(newTC
->threadId() == oldTC
->threadId());
407 system
->replaceThreadContext(newTC
, newTC
->contextId());
409 /* This code no longer works since the zero register (e.g.,
410 * r31 on Alpha) doesn't necessarily contain zero at this
413 ThreadContext::compare(oldTC, newTC);
416 BaseMasterPort
*old_itb_port
= oldTC
->getITBPtr()->getMasterPort();
417 BaseMasterPort
*old_dtb_port
= oldTC
->getDTBPtr()->getMasterPort();
418 BaseMasterPort
*new_itb_port
= newTC
->getITBPtr()->getMasterPort();
419 BaseMasterPort
*new_dtb_port
= newTC
->getDTBPtr()->getMasterPort();
421 // Move over any table walker ports if they exist
423 assert(!new_itb_port
->isConnected());
424 assert(old_itb_port
);
425 assert(old_itb_port
->isConnected());
426 BaseSlavePort
&slavePort
= old_itb_port
->getSlavePort();
427 old_itb_port
->unbind();
428 new_itb_port
->bind(slavePort
);
431 assert(!new_dtb_port
->isConnected());
432 assert(old_dtb_port
);
433 assert(old_dtb_port
->isConnected());
434 BaseSlavePort
&slavePort
= old_dtb_port
->getSlavePort();
435 old_dtb_port
->unbind();
436 new_dtb_port
->bind(slavePort
);
439 // Checker whether or not we have to transfer CheckerCPU
440 // objects over in the switch
441 CheckerCPU
*oldChecker
= oldTC
->getCheckerCpuPtr();
442 CheckerCPU
*newChecker
= newTC
->getCheckerCpuPtr();
443 if (oldChecker
&& newChecker
) {
444 BaseMasterPort
*old_checker_itb_port
=
445 oldChecker
->getITBPtr()->getMasterPort();
446 BaseMasterPort
*old_checker_dtb_port
=
447 oldChecker
->getDTBPtr()->getMasterPort();
448 BaseMasterPort
*new_checker_itb_port
=
449 newChecker
->getITBPtr()->getMasterPort();
450 BaseMasterPort
*new_checker_dtb_port
=
451 newChecker
->getDTBPtr()->getMasterPort();
453 // Move over any table walker ports if they exist for checker
454 if (new_checker_itb_port
) {
455 assert(!new_checker_itb_port
->isConnected());
456 assert(old_checker_itb_port
);
457 assert(old_checker_itb_port
->isConnected());
458 BaseSlavePort
&slavePort
=
459 old_checker_itb_port
->getSlavePort();
460 old_checker_itb_port
->unbind();
461 new_checker_itb_port
->bind(slavePort
);
463 if (new_checker_dtb_port
) {
464 assert(!new_checker_dtb_port
->isConnected());
465 assert(old_checker_dtb_port
);
466 assert(old_checker_dtb_port
->isConnected());
467 BaseSlavePort
&slavePort
=
468 old_checker_dtb_port
->getSlavePort();
469 old_checker_dtb_port
->unbind();
470 new_checker_dtb_port
->bind(slavePort
);
475 interrupts
= oldCPU
->interrupts
;
476 interrupts
->setCPU(this);
477 oldCPU
->interrupts
= NULL
;
480 for (ThreadID i
= 0; i
< size
; ++i
)
481 threadContexts
[i
]->profileClear();
484 schedule(profileEvent
, curTick());
487 // All CPUs have an instruction and a data port, and the new CPU's
488 // ports are dangling while the old CPU has its ports connected
489 // already. Unbind the old CPU and then bind the ports of the one
490 // we are switching to.
491 assert(!getInstPort().isConnected());
492 assert(oldCPU
->getInstPort().isConnected());
493 BaseSlavePort
&inst_peer_port
= oldCPU
->getInstPort().getSlavePort();
494 oldCPU
->getInstPort().unbind();
495 getInstPort().bind(inst_peer_port
);
497 assert(!getDataPort().isConnected());
498 assert(oldCPU
->getDataPort().isConnected());
499 BaseSlavePort
&data_peer_port
= oldCPU
->getDataPort().getSlavePort();
500 oldCPU
->getDataPort().unbind();
501 getDataPort().bind(data_peer_port
);
507 for (ThreadID i
= 0; i
< threadContexts
.size(); ++i
) {
508 ThreadContext
&tc(*threadContexts
[i
]);
509 CheckerCPU
*checker(tc
.getCheckerCpuPtr());
511 tc
.getITBPtr()->flushAll();
512 tc
.getDTBPtr()->flushAll();
514 checker
->getITBPtr()->flushAll();
515 checker
->getDTBPtr()->flushAll();
521 BaseCPU::ProfileEvent::ProfileEvent(BaseCPU
*_cpu
, Tick _interval
)
522 : cpu(_cpu
), interval(_interval
)
526 BaseCPU::ProfileEvent::process()
528 ThreadID size
= cpu
->threadContexts
.size();
529 for (ThreadID i
= 0; i
< size
; ++i
) {
530 ThreadContext
*tc
= cpu
->threadContexts
[i
];
534 cpu
->schedule(this, curTick() + interval
);
538 BaseCPU::serialize(std::ostream
&os
)
540 SERIALIZE_SCALAR(instCnt
);
543 /* Unlike _pid, _taskId is not serialized, as they are dynamically
544 * assigned unique ids that are only meaningful for the duration of
545 * a specific run. We will need to serialize the entire taskMap in
547 SERIALIZE_SCALAR(_pid
);
549 interrupts
->serialize(os
);
551 // Serialize the threads, this is done by the CPU implementation.
552 for (ThreadID i
= 0; i
< numThreads
; ++i
) {
553 nameOut(os
, csprintf("%s.xc.%i", name(), i
));
554 serializeThread(os
, i
);
560 BaseCPU::unserialize(Checkpoint
*cp
, const std::string
§ion
)
562 UNSERIALIZE_SCALAR(instCnt
);
565 UNSERIALIZE_SCALAR(_pid
);
566 interrupts
->unserialize(cp
, section
);
568 // Unserialize the threads, this is done by the CPU implementation.
569 for (ThreadID i
= 0; i
< numThreads
; ++i
)
570 unserializeThread(cp
, csprintf("%s.xc.%i", section
, i
), i
);
575 BaseCPU::traceFunctionsInternal(Addr pc
)
577 if (!debugSymbolTable
)
580 // if pc enters different function, print new function symbol and
581 // update saved range. Otherwise do nothing.
582 if (pc
< currentFunctionStart
|| pc
>= currentFunctionEnd
) {
584 bool found
= debugSymbolTable
->findNearestSymbol(pc
, sym_str
,
585 currentFunctionStart
,
589 // no symbol found: use addr as label
590 sym_str
= csprintf("0x%x", pc
);
591 currentFunctionStart
= pc
;
592 currentFunctionEnd
= pc
+ 1;
595 ccprintf(*functionTraceStream
, " (%d)\n%d: %s",
596 curTick() - functionEntryTick
, curTick(), sym_str
);
597 functionEntryTick
= curTick();