2 * Copyright (c) 2011 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
50 #include "arch/tlb.hh"
51 #include "base/loader/symtab.hh"
52 #include "base/cprintf.hh"
53 #include "base/misc.hh"
54 #include "base/output.hh"
55 #include "base/trace.hh"
56 #include "config/use_checker.hh"
57 #include "cpu/base.hh"
58 #include "cpu/cpuevent.hh"
59 #include "cpu/profile.hh"
60 #include "cpu/thread_context.hh"
61 #include "debug/SyscallVerbose.hh"
62 #include "params/BaseCPU.hh"
63 #include "sim/full_system.hh"
64 #include "sim/process.hh"
65 #include "sim/sim_events.hh"
66 #include "sim/sim_exit.hh"
67 #include "sim/system.hh"
70 #include "cpu/checker/cpu.hh"
74 #include "sim/stat_control.hh"
78 vector
<BaseCPU
*> BaseCPU::cpuList
;
80 // This variable reflects the max number of threads in any CPU. Be
81 // careful to only use it once all the CPUs that you care about have
83 int maxThreadsPerCPU
= 1;
85 CPUProgressEvent::CPUProgressEvent(BaseCPU
*_cpu
, Tick ival
)
86 : Event(Event::Progress_Event_Pri
), _interval(ival
), lastNumInst(0),
87 cpu(_cpu
), _repeatEvent(true)
90 cpu
->schedule(this, curTick() + _interval
);
94 CPUProgressEvent::process()
96 Counter temp
= cpu
->totalOps();
98 double ipc
= double(temp
- lastNumInst
) / (_interval
/ cpu
->ticks(1));
100 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
101 "%lli, IPC: %0.8d\n", cpu
->name(), temp
, temp
- lastNumInst
,
105 cprintf("%lli: %s progress event, total committed:%i, progress insts "
106 "committed: %lli\n", curTick(), cpu
->name(), temp
,
112 cpu
->schedule(this, curTick() + _interval
);
116 CPUProgressEvent::description() const
118 return "CPU Progress";
121 BaseCPU::BaseCPU(Params
*p
, bool is_checker
)
122 : MemObject(p
), clock(p
->clock
), instCnt(0), _cpuId(p
->cpu_id
),
123 _instMasterId(p
->system
->getMasterId(name() + ".inst")),
124 _dataMasterId(p
->system
->getMasterId(name() + ".data")),
125 interrupts(p
->interrupts
),
126 numThreads(p
->numThreads
), system(p
->system
),
129 // currentTick = curTick();
131 // if Python did not provide a valid ID, do it here
133 _cpuId
= cpuList
.size();
136 // add self to global list of CPUs
137 cpuList
.push_back(this);
139 DPRINTF(SyscallVerbose
, "Constructing CPU with id %d\n", _cpuId
);
141 if (numThreads
> maxThreadsPerCPU
)
142 maxThreadsPerCPU
= numThreads
;
144 // allocate per-thread instruction-based event queues
145 comInstEventQueue
= new EventQueue
*[numThreads
];
146 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
147 comInstEventQueue
[tid
] =
148 new EventQueue("instruction-based event queue");
151 // set up instruction-count-based termination events, if any
153 if (p
->max_insts_any_thread
!= 0) {
154 const char *cause
= "a thread reached the max instruction count";
155 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
156 Event
*event
= new SimLoopExitEvent(cause
, 0);
157 comInstEventQueue
[tid
]->schedule(event
, p
->max_insts_any_thread
);
161 if (p
->max_insts_all_threads
!= 0) {
162 const char *cause
= "all threads reached the max instruction count";
164 // allocate & initialize shared downcounter: each event will
165 // decrement this when triggered; simulation will terminate
166 // when counter reaches 0
167 int *counter
= new int;
168 *counter
= numThreads
;
169 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
170 Event
*event
= new CountedExitEvent(cause
, *counter
);
171 comInstEventQueue
[tid
]->schedule(event
, p
->max_insts_all_threads
);
175 // allocate per-thread load-based event queues
176 comLoadEventQueue
= new EventQueue
*[numThreads
];
177 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
178 comLoadEventQueue
[tid
] = new EventQueue("load-based event queue");
181 // set up instruction-count-based termination events, if any
183 if (p
->max_loads_any_thread
!= 0) {
184 const char *cause
= "a thread reached the max load count";
185 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
186 Event
*event
= new SimLoopExitEvent(cause
, 0);
187 comLoadEventQueue
[tid
]->schedule(event
, p
->max_loads_any_thread
);
191 if (p
->max_loads_all_threads
!= 0) {
192 const char *cause
= "all threads reached the max load count";
193 // allocate & initialize shared downcounter: each event will
194 // decrement this when triggered; simulation will terminate
195 // when counter reaches 0
196 int *counter
= new int;
197 *counter
= numThreads
;
198 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
199 Event
*event
= new CountedExitEvent(cause
, *counter
);
200 comLoadEventQueue
[tid
]->schedule(event
, p
->max_loads_all_threads
);
204 functionTracingEnabled
= false;
205 if (p
->function_trace
) {
206 const string fname
= csprintf("ftrace.%s", name());
207 functionTraceStream
= simout
.find(fname
);
208 if (!functionTraceStream
)
209 functionTraceStream
= simout
.create(fname
);
211 currentFunctionStart
= currentFunctionEnd
= 0;
212 functionEntryTick
= p
->function_trace_start
;
214 if (p
->function_trace_start
== 0) {
215 functionTracingEnabled
= true;
217 typedef EventWrapper
<BaseCPU
, &BaseCPU::enableFunctionTrace
> wrap
;
218 Event
*event
= new wrap(this, true);
219 schedule(event
, p
->function_trace_start
);
223 // The interrupts should always be present unless this CPU is
224 // switched in later or in case it is a checker CPU
225 if (!params()->defer_registration
&& !is_checker
) {
227 interrupts
->setCPU(this);
229 fatal("CPU %s has no interrupt controller.\n"
230 "Ensure createInterruptController() is called.\n", name());
236 if (params()->profile
)
237 profileEvent
= new ProfileEvent(this, params()->profile
);
239 tracer
= params()->tracer
;
243 BaseCPU::enableFunctionTrace()
245 functionTracingEnabled
= true;
255 if (!params()->defer_registration
)
256 registerThreadContexts();
263 if (!params()->defer_registration
&& profileEvent
)
264 schedule(profileEvent
, curTick());
267 if (params()->progress_interval
) {
268 Tick num_ticks
= ticks(params()->progress_interval
);
270 new CPUProgressEvent(this, num_ticks
);
278 using namespace Stats
;
281 .name(name() + ".numCycles")
282 .desc("number of cpu cycles simulated")
286 .name(name() + ".numWorkItemsStarted")
287 .desc("number of work items this cpu started")
290 numWorkItemsCompleted
291 .name(name() + ".numWorkItemsCompleted")
292 .desc("number of work items this cpu completed")
295 int size
= threadContexts
.size();
297 for (int i
= 0; i
< size
; ++i
) {
298 stringstream namestr
;
299 ccprintf(namestr
, "%s.ctx%d", name(), i
);
300 threadContexts
[i
]->regStats(namestr
.str());
302 } else if (size
== 1)
303 threadContexts
[0]->regStats(name());
307 BaseCPU::getPort(const string
&if_name
, int idx
)
309 // Get the right port based on name. This applies to all the
310 // subclasses of the base CPU and relies on their implementation
311 // of getDataPort and getInstPort. In all cases there methods
312 // return a CpuPort pointer.
313 if (if_name
== "dcache_port")
314 return &getDataPort();
315 else if (if_name
== "icache_port")
316 return &getInstPort();
318 panic("CPU %s has no port named %s\n", name(), if_name
);
324 Tick next_tick
= curTick() - phase
+ clock
- 1;
325 next_tick
-= (next_tick
% clock
);
331 BaseCPU::nextCycle(Tick begin_tick
)
333 Tick next_tick
= begin_tick
;
334 if (next_tick
% clock
!= 0)
335 next_tick
= next_tick
- (next_tick
% clock
) + clock
;
338 assert(next_tick
>= curTick());
343 BaseCPU::registerThreadContexts()
345 ThreadID size
= threadContexts
.size();
346 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
347 ThreadContext
*tc
= threadContexts
[tid
];
349 /** This is so that contextId and cpuId match where there is a
350 * 1cpu:1context relationship. Otherwise, the order of registration
351 * could affect the assignment and cpu 1 could have context id 3, for
352 * example. We may even want to do something like this for SMT so that
353 * cpu 0 has the lowest thread contexts and cpu N has the highest, but
354 * I'll just do this for now
357 tc
->setContextId(system
->registerThreadContext(tc
, _cpuId
));
359 tc
->setContextId(system
->registerThreadContext(tc
));
362 tc
->getProcessPtr()->assignThreadContext(tc
->contextId());
368 BaseCPU::findContext(ThreadContext
*tc
)
370 ThreadID size
= threadContexts
.size();
371 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
372 if (tc
== threadContexts
[tid
])
381 if (profileEvent
&& profileEvent
->scheduled())
382 deschedule(profileEvent
);
386 BaseCPU::takeOverFrom(BaseCPU
*oldCPU
)
388 CpuPort
&ic
= getInstPort();
389 CpuPort
&dc
= getDataPort();
390 assert(threadContexts
.size() == oldCPU
->threadContexts
.size());
392 _cpuId
= oldCPU
->cpuId();
394 ThreadID size
= threadContexts
.size();
395 for (ThreadID i
= 0; i
< size
; ++i
) {
396 ThreadContext
*newTC
= threadContexts
[i
];
397 ThreadContext
*oldTC
= oldCPU
->threadContexts
[i
];
399 newTC
->takeOverFrom(oldTC
);
401 CpuEvent::replaceThreadContext(oldTC
, newTC
);
403 assert(newTC
->contextId() == oldTC
->contextId());
404 assert(newTC
->threadId() == oldTC
->threadId());
405 system
->replaceThreadContext(newTC
, newTC
->contextId());
407 /* This code no longer works since the zero register (e.g.,
408 * r31 on Alpha) doesn't necessarily contain zero at this
411 ThreadContext::compare(oldTC, newTC);
414 Port
*old_itb_port
, *old_dtb_port
, *new_itb_port
, *new_dtb_port
;
415 old_itb_port
= oldTC
->getITBPtr()->getPort();
416 old_dtb_port
= oldTC
->getDTBPtr()->getPort();
417 new_itb_port
= newTC
->getITBPtr()->getPort();
418 new_dtb_port
= newTC
->getDTBPtr()->getPort();
420 // Move over any table walker ports if they exist
421 if (new_itb_port
&& !new_itb_port
->isConnected()) {
422 assert(old_itb_port
);
423 Port
*peer
= old_itb_port
->getPeer();;
424 new_itb_port
->setPeer(peer
);
425 peer
->setPeer(new_itb_port
);
427 if (new_dtb_port
&& !new_dtb_port
->isConnected()) {
428 assert(old_dtb_port
);
429 Port
*peer
= old_dtb_port
->getPeer();;
430 new_dtb_port
->setPeer(peer
);
431 peer
->setPeer(new_dtb_port
);
435 Port
*old_checker_itb_port
, *old_checker_dtb_port
;
436 Port
*new_checker_itb_port
, *new_checker_dtb_port
;
438 CheckerCPU
*oldChecker
=
439 dynamic_cast<CheckerCPU
*>(oldTC
->getCheckerCpuPtr());
440 CheckerCPU
*newChecker
=
441 dynamic_cast<CheckerCPU
*>(newTC
->getCheckerCpuPtr());
442 old_checker_itb_port
= oldChecker
->getITBPtr()->getPort();
443 old_checker_dtb_port
= oldChecker
->getDTBPtr()->getPort();
444 new_checker_itb_port
= newChecker
->getITBPtr()->getPort();
445 new_checker_dtb_port
= newChecker
->getDTBPtr()->getPort();
447 // Move over any table walker ports if they exist for checker
448 if (new_checker_itb_port
&& !new_checker_itb_port
->isConnected()) {
449 assert(old_checker_itb_port
);
450 Port
*peer
= old_checker_itb_port
->getPeer();;
451 new_checker_itb_port
->setPeer(peer
);
452 peer
->setPeer(new_checker_itb_port
);
454 if (new_checker_dtb_port
&& !new_checker_dtb_port
->isConnected()) {
455 assert(old_checker_dtb_port
);
456 Port
*peer
= old_checker_dtb_port
->getPeer();;
457 new_checker_dtb_port
->setPeer(peer
);
458 peer
->setPeer(new_checker_dtb_port
);
464 interrupts
= oldCPU
->interrupts
;
465 interrupts
->setCPU(this);
468 for (ThreadID i
= 0; i
< size
; ++i
)
469 threadContexts
[i
]->profileClear();
472 schedule(profileEvent
, curTick());
475 // Connect new CPU to old CPU's memory only if new CPU isn't
476 // connected to anything. Also connect old CPU's memory to new
478 if (!ic
.isConnected()) {
479 Port
*peer
= oldCPU
->getInstPort().getPeer();
484 if (!dc
.isConnected()) {
485 Port
*peer
= oldCPU
->getDataPort().getPeer();
492 BaseCPU::ProfileEvent::ProfileEvent(BaseCPU
*_cpu
, Tick _interval
)
493 : cpu(_cpu
), interval(_interval
)
497 BaseCPU::ProfileEvent::process()
499 ThreadID size
= cpu
->threadContexts
.size();
500 for (ThreadID i
= 0; i
< size
; ++i
) {
501 ThreadContext
*tc
= cpu
->threadContexts
[i
];
505 cpu
->schedule(this, curTick() + interval
);
509 BaseCPU::serialize(std::ostream
&os
)
511 SERIALIZE_SCALAR(instCnt
);
512 interrupts
->serialize(os
);
516 BaseCPU::unserialize(Checkpoint
*cp
, const std::string
§ion
)
518 UNSERIALIZE_SCALAR(instCnt
);
519 interrupts
->unserialize(cp
, section
);
523 BaseCPU::traceFunctionsInternal(Addr pc
)
525 if (!debugSymbolTable
)
528 // if pc enters different function, print new function symbol and
529 // update saved range. Otherwise do nothing.
530 if (pc
< currentFunctionStart
|| pc
>= currentFunctionEnd
) {
532 bool found
= debugSymbolTable
->findNearestSymbol(pc
, sym_str
,
533 currentFunctionStart
,
537 // no symbol found: use addr as label
538 sym_str
= csprintf("0x%x", pc
);
539 currentFunctionStart
= pc
;
540 currentFunctionEnd
= pc
+ 1;
543 ccprintf(*functionTraceStream
, " (%d)\n%d: %s",
544 curTick() - functionEntryTick
, curTick(), sym_str
);
545 functionEntryTick
= curTick();
550 BaseCPU::CpuPort::recvTiming(PacketPtr pkt
)
552 panic("BaseCPU doesn't expect recvTiming callback!");
557 BaseCPU::CpuPort::recvRetry()
559 panic("BaseCPU doesn't expect recvRetry callback!");
563 BaseCPU::CpuPort::recvAtomic(PacketPtr pkt
)
565 panic("BaseCPU doesn't expect recvAtomic callback!");
570 BaseCPU::CpuPort::recvFunctional(PacketPtr pkt
)
572 // No internal storage to update (in the general case). In the
573 // long term this should never be called, but that assumed a split
574 // into master/slave and request/response.
578 BaseCPU::CpuPort::recvRangeChange()