2 * Copyright (c) 2011-2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * Copyright (c) 2013 Advanced Micro Devices, Inc.
17 * Copyright (c) 2013 Mark D. Hill and David A. Wood
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are
22 * met: redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer;
24 * redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution;
27 * neither the name of the copyright holders nor the names of its
28 * contributors may be used to endorse or promote products derived from
29 * this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * Authors: Steve Reinhardt
52 #include "arch/tlb.hh"
53 #include "base/loader/symtab.hh"
54 #include "base/cprintf.hh"
55 #include "base/misc.hh"
56 #include "base/output.hh"
57 #include "base/trace.hh"
58 #include "cpu/checker/cpu.hh"
59 #include "cpu/base.hh"
60 #include "cpu/cpuevent.hh"
61 #include "cpu/profile.hh"
62 #include "cpu/thread_context.hh"
63 #include "debug/Mwait.hh"
64 #include "debug/SyscallVerbose.hh"
65 #include "mem/page_table.hh"
66 #include "params/BaseCPU.hh"
67 #include "sim/full_system.hh"
68 #include "sim/process.hh"
69 #include "sim/sim_events.hh"
70 #include "sim/sim_exit.hh"
71 #include "sim/system.hh"
74 #include "sim/stat_control.hh"
78 vector
<BaseCPU
*> BaseCPU::cpuList
;
80 // This variable reflects the max number of threads in any CPU. Be
81 // careful to only use it once all the CPUs that you care about have
83 int maxThreadsPerCPU
= 1;
85 CPUProgressEvent::CPUProgressEvent(BaseCPU
*_cpu
, Tick ival
)
86 : Event(Event::Progress_Event_Pri
), _interval(ival
), lastNumInst(0),
87 cpu(_cpu
), _repeatEvent(true)
90 cpu
->schedule(this, curTick() + _interval
);
94 CPUProgressEvent::process()
96 Counter temp
= cpu
->totalOps();
99 cpu
->schedule(this, curTick() + _interval
);
101 if(cpu
->switchedOut()) {
106 double ipc
= double(temp
- lastNumInst
) / (_interval
/ cpu
->clockPeriod());
108 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
109 "%lli, IPC: %0.8d\n", cpu
->name(), temp
, temp
- lastNumInst
,
113 cprintf("%lli: %s progress event, total committed:%i, progress insts "
114 "committed: %lli\n", curTick(), cpu
->name(), temp
,
121 CPUProgressEvent::description() const
123 return "CPU Progress";
126 BaseCPU::BaseCPU(Params
*p
, bool is_checker
)
127 : MemObject(p
), instCnt(0), _cpuId(p
->cpu_id
), _socketId(p
->socket_id
),
128 _instMasterId(p
->system
->getMasterId(name() + ".inst")),
129 _dataMasterId(p
->system
->getMasterId(name() + ".data")),
130 _taskId(ContextSwitchTaskId::Unknown
), _pid(Request::invldPid
),
131 _switchedOut(p
->switched_out
), _cacheLineSize(p
->system
->cacheLineSize()),
132 interrupts(p
->interrupts
), profileEvent(NULL
),
133 numThreads(p
->numThreads
), system(p
->system
),
134 functionTraceStream(nullptr), currentFunctionStart(0),
135 currentFunctionEnd(0), functionEntryTick(0),
138 // if Python did not provide a valid ID, do it here
140 _cpuId
= cpuList
.size();
143 // add self to global list of CPUs
144 cpuList
.push_back(this);
146 DPRINTF(SyscallVerbose
, "Constructing CPU with id %d, socket id %d\n",
149 if (numThreads
> maxThreadsPerCPU
)
150 maxThreadsPerCPU
= numThreads
;
152 // allocate per-thread instruction-based event queues
153 comInstEventQueue
= new EventQueue
*[numThreads
];
154 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
155 comInstEventQueue
[tid
] =
156 new EventQueue("instruction-based event queue");
159 // set up instruction-count-based termination events, if any
161 if (p
->max_insts_any_thread
!= 0) {
162 const char *cause
= "a thread reached the max instruction count";
163 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
164 scheduleInstStop(tid
, p
->max_insts_any_thread
, cause
);
167 // Set up instruction-count-based termination events for SimPoints
168 // Typically, there are more than one action points.
169 // Simulation.py is responsible to take the necessary actions upon
170 // exitting the simulation loop.
171 if (!p
->simpoint_start_insts
.empty()) {
172 const char *cause
= "simpoint starting point found";
173 for (size_t i
= 0; i
< p
->simpoint_start_insts
.size(); ++i
)
174 scheduleInstStop(0, p
->simpoint_start_insts
[i
], cause
);
177 if (p
->max_insts_all_threads
!= 0) {
178 const char *cause
= "all threads reached the max instruction count";
180 // allocate & initialize shared downcounter: each event will
181 // decrement this when triggered; simulation will terminate
182 // when counter reaches 0
183 int *counter
= new int;
184 *counter
= numThreads
;
185 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
186 Event
*event
= new CountedExitEvent(cause
, *counter
);
187 comInstEventQueue
[tid
]->schedule(event
, p
->max_insts_all_threads
);
191 // allocate per-thread load-based event queues
192 comLoadEventQueue
= new EventQueue
*[numThreads
];
193 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
194 comLoadEventQueue
[tid
] = new EventQueue("load-based event queue");
197 // set up instruction-count-based termination events, if any
199 if (p
->max_loads_any_thread
!= 0) {
200 const char *cause
= "a thread reached the max load count";
201 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
202 scheduleLoadStop(tid
, p
->max_loads_any_thread
, cause
);
205 if (p
->max_loads_all_threads
!= 0) {
206 const char *cause
= "all threads reached the max load count";
207 // allocate & initialize shared downcounter: each event will
208 // decrement this when triggered; simulation will terminate
209 // when counter reaches 0
210 int *counter
= new int;
211 *counter
= numThreads
;
212 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
213 Event
*event
= new CountedExitEvent(cause
, *counter
);
214 comLoadEventQueue
[tid
]->schedule(event
, p
->max_loads_all_threads
);
218 functionTracingEnabled
= false;
219 if (p
->function_trace
) {
220 const string fname
= csprintf("ftrace.%s", name());
221 functionTraceStream
= simout
.find(fname
);
222 if (!functionTraceStream
)
223 functionTraceStream
= simout
.create(fname
);
225 currentFunctionStart
= currentFunctionEnd
= 0;
226 functionEntryTick
= p
->function_trace_start
;
228 if (p
->function_trace_start
== 0) {
229 functionTracingEnabled
= true;
231 typedef EventWrapper
<BaseCPU
, &BaseCPU::enableFunctionTrace
> wrap
;
232 Event
*event
= new wrap(this, true);
233 schedule(event
, p
->function_trace_start
);
237 // The interrupts should always be present unless this CPU is
238 // switched in later or in case it is a checker CPU
239 if (!params()->switched_out
&& !is_checker
) {
241 interrupts
->setCPU(this);
243 fatal("CPU %s has no interrupt controller.\n"
244 "Ensure createInterruptController() is called.\n", name());
249 if (params()->profile
)
250 profileEvent
= new ProfileEvent(this, params()->profile
);
252 tracer
= params()->tracer
;
254 if (params()->isa
.size() != numThreads
) {
255 fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
256 "of threads (%i).\n", params()->isa
.size(), numThreads
);
261 BaseCPU::enableFunctionTrace()
263 functionTracingEnabled
= true;
269 delete[] comLoadEventQueue
;
270 delete[] comInstEventQueue
;
274 BaseCPU::armMonitor(Addr address
)
276 addressMonitor
.armed
= true;
277 addressMonitor
.vAddr
= address
;
278 addressMonitor
.pAddr
= 0x0;
279 DPRINTF(Mwait
,"Armed monitor (vAddr=0x%lx)\n", address
);
283 BaseCPU::mwait(PacketPtr pkt
)
285 if(addressMonitor
.gotWakeup
== false) {
286 int block_size
= cacheLineSize();
287 uint64_t mask
= ~((uint64_t)(block_size
- 1));
289 assert(pkt
->req
->hasPaddr());
290 addressMonitor
.pAddr
= pkt
->getAddr() & mask
;
291 addressMonitor
.waiting
= true;
293 DPRINTF(Mwait
,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
294 addressMonitor
.vAddr
, addressMonitor
.pAddr
);
297 addressMonitor
.gotWakeup
= false;
303 BaseCPU::mwaitAtomic(ThreadContext
*tc
, TheISA::TLB
*dtb
)
306 Addr addr
= addressMonitor
.vAddr
;
307 int block_size
= cacheLineSize();
308 uint64_t mask
= ~((uint64_t)(block_size
- 1));
309 int size
= block_size
;
311 //The address of the next line if it crosses a cache line boundary.
312 Addr secondAddr
= roundDown(addr
+ size
- 1, block_size
);
314 if (secondAddr
> addr
)
315 size
= secondAddr
- addr
;
317 req
.setVirt(0, addr
, size
, 0x0, dataMasterId(), tc
->instAddr());
319 // translate to physical address
320 Fault fault
= dtb
->translateAtomic(&req
, tc
, BaseTLB::Read
);
321 assert(fault
== NoFault
);
323 addressMonitor
.pAddr
= req
.getPaddr() & mask
;
324 addressMonitor
.waiting
= true;
326 DPRINTF(Mwait
,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
327 addressMonitor
.vAddr
, addressMonitor
.pAddr
);
333 if (!params()->switched_out
) {
334 registerThreadContexts();
344 if (!params()->switched_out
&& profileEvent
)
345 schedule(profileEvent
, curTick());
348 if (params()->progress_interval
) {
349 new CPUProgressEvent(this, params()->progress_interval
);
354 BaseCPU::pmuProbePoint(const char *name
)
356 ProbePoints::PMUUPtr ptr
;
357 ptr
.reset(new ProbePoints::PMU(getProbeManager(), name
));
363 BaseCPU::regProbePoints()
365 ppCycles
= pmuProbePoint("Cycles");
367 ppRetiredInsts
= pmuProbePoint("RetiredInsts");
368 ppRetiredLoads
= pmuProbePoint("RetiredLoads");
369 ppRetiredStores
= pmuProbePoint("RetiredStores");
370 ppRetiredBranches
= pmuProbePoint("RetiredBranches");
374 BaseCPU::probeInstCommit(const StaticInstPtr
&inst
)
376 if (!inst
->isMicroop() || inst
->isLastMicroop())
377 ppRetiredInsts
->notify(1);
381 ppRetiredLoads
->notify(1);
384 ppRetiredStores
->notify(1);
386 if (inst
->isControl())
387 ppRetiredBranches
->notify(1);
393 using namespace Stats
;
396 .name(name() + ".numCycles")
397 .desc("number of cpu cycles simulated")
401 .name(name() + ".numWorkItemsStarted")
402 .desc("number of work items this cpu started")
405 numWorkItemsCompleted
406 .name(name() + ".numWorkItemsCompleted")
407 .desc("number of work items this cpu completed")
410 int size
= threadContexts
.size();
412 for (int i
= 0; i
< size
; ++i
) {
413 stringstream namestr
;
414 ccprintf(namestr
, "%s.ctx%d", name(), i
);
415 threadContexts
[i
]->regStats(namestr
.str());
417 } else if (size
== 1)
418 threadContexts
[0]->regStats(name());
422 BaseCPU::getMasterPort(const string
&if_name
, PortID idx
)
424 // Get the right port based on name. This applies to all the
425 // subclasses of the base CPU and relies on their implementation
426 // of getDataPort and getInstPort. In all cases there methods
427 // return a MasterPort pointer.
428 if (if_name
== "dcache_port")
429 return getDataPort();
430 else if (if_name
== "icache_port")
431 return getInstPort();
433 return MemObject::getMasterPort(if_name
, idx
);
437 BaseCPU::registerThreadContexts()
439 ThreadID size
= threadContexts
.size();
440 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
441 ThreadContext
*tc
= threadContexts
[tid
];
443 /** This is so that contextId and cpuId match where there is a
444 * 1cpu:1context relationship. Otherwise, the order of registration
445 * could affect the assignment and cpu 1 could have context id 3, for
446 * example. We may even want to do something like this for SMT so that
447 * cpu 0 has the lowest thread contexts and cpu N has the highest, but
448 * I'll just do this for now
451 tc
->setContextId(system
->registerThreadContext(tc
, _cpuId
));
453 tc
->setContextId(system
->registerThreadContext(tc
));
456 tc
->getProcessPtr()->assignThreadContext(tc
->contextId());
462 BaseCPU::findContext(ThreadContext
*tc
)
464 ThreadID size
= threadContexts
.size();
465 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
466 if (tc
== threadContexts
[tid
])
475 assert(!_switchedOut
);
477 if (profileEvent
&& profileEvent
->scheduled())
478 deschedule(profileEvent
);
480 // Flush all TLBs in the CPU to avoid having stale translations if
481 // it gets switched in later.
486 BaseCPU::takeOverFrom(BaseCPU
*oldCPU
)
488 assert(threadContexts
.size() == oldCPU
->threadContexts
.size());
489 assert(_cpuId
== oldCPU
->cpuId());
490 assert(_switchedOut
);
491 assert(oldCPU
!= this);
492 _pid
= oldCPU
->getPid();
493 _taskId
= oldCPU
->taskId();
494 _switchedOut
= false;
496 ThreadID size
= threadContexts
.size();
497 for (ThreadID i
= 0; i
< size
; ++i
) {
498 ThreadContext
*newTC
= threadContexts
[i
];
499 ThreadContext
*oldTC
= oldCPU
->threadContexts
[i
];
501 newTC
->takeOverFrom(oldTC
);
503 CpuEvent::replaceThreadContext(oldTC
, newTC
);
505 assert(newTC
->contextId() == oldTC
->contextId());
506 assert(newTC
->threadId() == oldTC
->threadId());
507 system
->replaceThreadContext(newTC
, newTC
->contextId());
509 /* This code no longer works since the zero register (e.g.,
510 * r31 on Alpha) doesn't necessarily contain zero at this
513 ThreadContext::compare(oldTC, newTC);
516 BaseMasterPort
*old_itb_port
= oldTC
->getITBPtr()->getMasterPort();
517 BaseMasterPort
*old_dtb_port
= oldTC
->getDTBPtr()->getMasterPort();
518 BaseMasterPort
*new_itb_port
= newTC
->getITBPtr()->getMasterPort();
519 BaseMasterPort
*new_dtb_port
= newTC
->getDTBPtr()->getMasterPort();
521 // Move over any table walker ports if they exist
523 assert(!new_itb_port
->isConnected());
524 assert(old_itb_port
);
525 assert(old_itb_port
->isConnected());
526 BaseSlavePort
&slavePort
= old_itb_port
->getSlavePort();
527 old_itb_port
->unbind();
528 new_itb_port
->bind(slavePort
);
531 assert(!new_dtb_port
->isConnected());
532 assert(old_dtb_port
);
533 assert(old_dtb_port
->isConnected());
534 BaseSlavePort
&slavePort
= old_dtb_port
->getSlavePort();
535 old_dtb_port
->unbind();
536 new_dtb_port
->bind(slavePort
);
538 newTC
->getITBPtr()->takeOverFrom(oldTC
->getITBPtr());
539 newTC
->getDTBPtr()->takeOverFrom(oldTC
->getDTBPtr());
541 // Checker whether or not we have to transfer CheckerCPU
542 // objects over in the switch
543 CheckerCPU
*oldChecker
= oldTC
->getCheckerCpuPtr();
544 CheckerCPU
*newChecker
= newTC
->getCheckerCpuPtr();
545 if (oldChecker
&& newChecker
) {
546 BaseMasterPort
*old_checker_itb_port
=
547 oldChecker
->getITBPtr()->getMasterPort();
548 BaseMasterPort
*old_checker_dtb_port
=
549 oldChecker
->getDTBPtr()->getMasterPort();
550 BaseMasterPort
*new_checker_itb_port
=
551 newChecker
->getITBPtr()->getMasterPort();
552 BaseMasterPort
*new_checker_dtb_port
=
553 newChecker
->getDTBPtr()->getMasterPort();
555 newChecker
->getITBPtr()->takeOverFrom(oldChecker
->getITBPtr());
556 newChecker
->getDTBPtr()->takeOverFrom(oldChecker
->getDTBPtr());
558 // Move over any table walker ports if they exist for checker
559 if (new_checker_itb_port
) {
560 assert(!new_checker_itb_port
->isConnected());
561 assert(old_checker_itb_port
);
562 assert(old_checker_itb_port
->isConnected());
563 BaseSlavePort
&slavePort
=
564 old_checker_itb_port
->getSlavePort();
565 old_checker_itb_port
->unbind();
566 new_checker_itb_port
->bind(slavePort
);
568 if (new_checker_dtb_port
) {
569 assert(!new_checker_dtb_port
->isConnected());
570 assert(old_checker_dtb_port
);
571 assert(old_checker_dtb_port
->isConnected());
572 BaseSlavePort
&slavePort
=
573 old_checker_dtb_port
->getSlavePort();
574 old_checker_dtb_port
->unbind();
575 new_checker_dtb_port
->bind(slavePort
);
580 interrupts
= oldCPU
->interrupts
;
581 interrupts
->setCPU(this);
582 oldCPU
->interrupts
= NULL
;
585 for (ThreadID i
= 0; i
< size
; ++i
)
586 threadContexts
[i
]->profileClear();
589 schedule(profileEvent
, curTick());
592 // All CPUs have an instruction and a data port, and the new CPU's
593 // ports are dangling while the old CPU has its ports connected
594 // already. Unbind the old CPU and then bind the ports of the one
595 // we are switching to.
596 assert(!getInstPort().isConnected());
597 assert(oldCPU
->getInstPort().isConnected());
598 BaseSlavePort
&inst_peer_port
= oldCPU
->getInstPort().getSlavePort();
599 oldCPU
->getInstPort().unbind();
600 getInstPort().bind(inst_peer_port
);
602 assert(!getDataPort().isConnected());
603 assert(oldCPU
->getDataPort().isConnected());
604 BaseSlavePort
&data_peer_port
= oldCPU
->getDataPort().getSlavePort();
605 oldCPU
->getDataPort().unbind();
606 getDataPort().bind(data_peer_port
);
612 for (ThreadID i
= 0; i
< threadContexts
.size(); ++i
) {
613 ThreadContext
&tc(*threadContexts
[i
]);
614 CheckerCPU
*checker(tc
.getCheckerCpuPtr());
616 tc
.getITBPtr()->flushAll();
617 tc
.getDTBPtr()->flushAll();
619 checker
->getITBPtr()->flushAll();
620 checker
->getDTBPtr()->flushAll();
626 BaseCPU::ProfileEvent::ProfileEvent(BaseCPU
*_cpu
, Tick _interval
)
627 : cpu(_cpu
), interval(_interval
)
631 BaseCPU::ProfileEvent::process()
633 ThreadID size
= cpu
->threadContexts
.size();
634 for (ThreadID i
= 0; i
< size
; ++i
) {
635 ThreadContext
*tc
= cpu
->threadContexts
[i
];
639 cpu
->schedule(this, curTick() + interval
);
643 BaseCPU::serialize(CheckpointOut
&cp
) const
645 SERIALIZE_SCALAR(instCnt
);
648 /* Unlike _pid, _taskId is not serialized, as they are dynamically
649 * assigned unique ids that are only meaningful for the duration of
650 * a specific run. We will need to serialize the entire taskMap in
652 SERIALIZE_SCALAR(_pid
);
654 interrupts
->serialize(cp
);
656 // Serialize the threads, this is done by the CPU implementation.
657 for (ThreadID i
= 0; i
< numThreads
; ++i
) {
658 ScopedCheckpointSection
sec(cp
, csprintf("xc.%i", i
));
659 serializeThread(cp
, i
);
665 BaseCPU::unserialize(CheckpointIn
&cp
)
667 UNSERIALIZE_SCALAR(instCnt
);
670 UNSERIALIZE_SCALAR(_pid
);
671 interrupts
->unserialize(cp
);
673 // Unserialize the threads, this is done by the CPU implementation.
674 for (ThreadID i
= 0; i
< numThreads
; ++i
) {
675 ScopedCheckpointSection
sec(cp
, csprintf("xc.%i", i
));
676 unserializeThread(cp
, i
);
682 BaseCPU::scheduleInstStop(ThreadID tid
, Counter insts
, const char *cause
)
684 const Tick
now(comInstEventQueue
[tid
]->getCurTick());
685 Event
*event(new LocalSimLoopExitEvent(cause
, 0));
687 comInstEventQueue
[tid
]->schedule(event
, now
+ insts
);
690 AddressMonitor::AddressMonitor() {
696 bool AddressMonitor::doMonitor(PacketPtr pkt
) {
697 assert(pkt
->req
->hasPaddr());
698 if(armed
&& waiting
) {
699 if(pAddr
== pkt
->getAddr()) {
700 DPRINTF(Mwait
,"pAddr=0x%lx invalidated: waking up core\n",
710 BaseCPU::scheduleLoadStop(ThreadID tid
, Counter loads
, const char *cause
)
712 const Tick
now(comLoadEventQueue
[tid
]->getCurTick());
713 Event
*event(new LocalSimLoopExitEvent(cause
, 0));
715 comLoadEventQueue
[tid
]->schedule(event
, now
+ loads
);
720 BaseCPU::traceFunctionsInternal(Addr pc
)
722 if (!debugSymbolTable
)
725 // if pc enters different function, print new function symbol and
726 // update saved range. Otherwise do nothing.
727 if (pc
< currentFunctionStart
|| pc
>= currentFunctionEnd
) {
729 bool found
= debugSymbolTable
->findNearestSymbol(pc
, sym_str
,
730 currentFunctionStart
,
734 // no symbol found: use addr as label
735 sym_str
= csprintf("0x%x", pc
);
736 currentFunctionStart
= pc
;
737 currentFunctionEnd
= pc
+ 1;
740 ccprintf(*functionTraceStream
, " (%d)\n%d: %s",
741 curTick() - functionEntryTick
, curTick(), sym_str
);
742 functionEntryTick
= curTick();