2 * Copyright (c) 2011-2012,2016-2017 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * Copyright (c) 2013 Advanced Micro Devices, Inc.
17 * Copyright (c) 2013 Mark D. Hill and David A. Wood
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are
22 * met: redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer;
24 * redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution;
27 * neither the name of the copyright holders nor the names of its
28 * contributors may be used to endorse or promote products derived from
29 * this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * Authors: Steve Reinhardt
48 #include "cpu/base.hh"
54 #include "arch/generic/tlb.hh"
55 #include "base/cprintf.hh"
56 #include "base/loader/symtab.hh"
57 #include "base/logging.hh"
58 #include "base/output.hh"
59 #include "base/trace.hh"
60 #include "cpu/checker/cpu.hh"
61 #include "cpu/cpuevent.hh"
62 #include "cpu/profile.hh"
63 #include "cpu/thread_context.hh"
64 #include "debug/Mwait.hh"
65 #include "debug/SyscallVerbose.hh"
66 #include "mem/page_table.hh"
67 #include "params/BaseCPU.hh"
68 #include "sim/clocked_object.hh"
69 #include "sim/full_system.hh"
70 #include "sim/process.hh"
71 #include "sim/sim_events.hh"
72 #include "sim/sim_exit.hh"
73 #include "sim/system.hh"
76 #include "sim/stat_control.hh"
80 vector
<BaseCPU
*> BaseCPU::cpuList
;
82 // This variable reflects the max number of threads in any CPU. Be
83 // careful to only use it once all the CPUs that you care about have
85 int maxThreadsPerCPU
= 1;
87 CPUProgressEvent::CPUProgressEvent(BaseCPU
*_cpu
, Tick ival
)
88 : Event(Event::Progress_Event_Pri
), _interval(ival
), lastNumInst(0),
89 cpu(_cpu
), _repeatEvent(true)
92 cpu
->schedule(this, curTick() + _interval
);
96 CPUProgressEvent::process()
98 Counter temp
= cpu
->totalOps();
101 cpu
->schedule(this, curTick() + _interval
);
103 if (cpu
->switchedOut()) {
108 double ipc
= double(temp
- lastNumInst
) / (_interval
/ cpu
->clockPeriod());
110 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
111 "%lli, IPC: %0.8d\n", cpu
->name(), temp
, temp
- lastNumInst
,
115 cprintf("%lli: %s progress event, total committed:%i, progress insts "
116 "committed: %lli\n", curTick(), cpu
->name(), temp
,
123 CPUProgressEvent::description() const
125 return "CPU Progress";
128 BaseCPU::BaseCPU(Params
*p
, bool is_checker
)
129 : MemObject(p
), instCnt(0), _cpuId(p
->cpu_id
), _socketId(p
->socket_id
),
130 _instMasterId(p
->system
->getMasterId(name() + ".inst")),
131 _dataMasterId(p
->system
->getMasterId(name() + ".data")),
132 _taskId(ContextSwitchTaskId::Unknown
), _pid(invldPid
),
133 _switchedOut(p
->switched_out
), _cacheLineSize(p
->system
->cacheLineSize()),
134 interrupts(p
->interrupts
), profileEvent(NULL
),
135 numThreads(p
->numThreads
), system(p
->system
),
136 previousCycle(0), previousState(CPU_STATE_SLEEP
),
137 functionTraceStream(nullptr), currentFunctionStart(0),
138 currentFunctionEnd(0), functionEntryTick(0),
139 addressMonitor(p
->numThreads
),
140 syscallRetryLatency(p
->syscallRetryLatency
),
141 pwrGatingLatency(p
->pwr_gating_latency
),
142 powerGatingOnIdle(p
->power_gating_on_idle
),
143 enterPwrGatingEvent([this]{ enterPwrGating(); }, name())
145 // if Python did not provide a valid ID, do it here
147 _cpuId
= cpuList
.size();
150 // add self to global list of CPUs
151 cpuList
.push_back(this);
153 DPRINTF(SyscallVerbose
, "Constructing CPU with id %d, socket id %d\n",
156 if (numThreads
> maxThreadsPerCPU
)
157 maxThreadsPerCPU
= numThreads
;
159 // allocate per-thread instruction-based event queues
160 comInstEventQueue
= new EventQueue
*[numThreads
];
161 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
162 comInstEventQueue
[tid
] =
163 new EventQueue("instruction-based event queue");
166 // set up instruction-count-based termination events, if any
168 if (p
->max_insts_any_thread
!= 0) {
169 const char *cause
= "a thread reached the max instruction count";
170 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
171 scheduleInstStop(tid
, p
->max_insts_any_thread
, cause
);
174 // Set up instruction-count-based termination events for SimPoints
175 // Typically, there are more than one action points.
176 // Simulation.py is responsible to take the necessary actions upon
177 // exitting the simulation loop.
178 if (!p
->simpoint_start_insts
.empty()) {
179 const char *cause
= "simpoint starting point found";
180 for (size_t i
= 0; i
< p
->simpoint_start_insts
.size(); ++i
)
181 scheduleInstStop(0, p
->simpoint_start_insts
[i
], cause
);
184 if (p
->max_insts_all_threads
!= 0) {
185 const char *cause
= "all threads reached the max instruction count";
187 // allocate & initialize shared downcounter: each event will
188 // decrement this when triggered; simulation will terminate
189 // when counter reaches 0
190 int *counter
= new int;
191 *counter
= numThreads
;
192 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
193 Event
*event
= new CountedExitEvent(cause
, *counter
);
194 comInstEventQueue
[tid
]->schedule(event
, p
->max_insts_all_threads
);
198 // allocate per-thread load-based event queues
199 comLoadEventQueue
= new EventQueue
*[numThreads
];
200 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
201 comLoadEventQueue
[tid
] = new EventQueue("load-based event queue");
204 // set up instruction-count-based termination events, if any
206 if (p
->max_loads_any_thread
!= 0) {
207 const char *cause
= "a thread reached the max load count";
208 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
)
209 scheduleLoadStop(tid
, p
->max_loads_any_thread
, cause
);
212 if (p
->max_loads_all_threads
!= 0) {
213 const char *cause
= "all threads reached the max load count";
214 // allocate & initialize shared downcounter: each event will
215 // decrement this when triggered; simulation will terminate
216 // when counter reaches 0
217 int *counter
= new int;
218 *counter
= numThreads
;
219 for (ThreadID tid
= 0; tid
< numThreads
; ++tid
) {
220 Event
*event
= new CountedExitEvent(cause
, *counter
);
221 comLoadEventQueue
[tid
]->schedule(event
, p
->max_loads_all_threads
);
225 functionTracingEnabled
= false;
226 if (p
->function_trace
) {
227 const string fname
= csprintf("ftrace.%s", name());
228 functionTraceStream
= simout
.findOrCreate(fname
)->stream();
230 currentFunctionStart
= currentFunctionEnd
= 0;
231 functionEntryTick
= p
->function_trace_start
;
233 if (p
->function_trace_start
== 0) {
234 functionTracingEnabled
= true;
236 Event
*event
= new EventFunctionWrapper(
237 [this]{ enableFunctionTrace(); }, name(), true);
238 schedule(event
, p
->function_trace_start
);
242 // The interrupts should always be present unless this CPU is
243 // switched in later or in case it is a checker CPU
244 if (!params()->switched_out
&& !is_checker
) {
245 fatal_if(interrupts
.size() != numThreads
,
246 "CPU %s has %i interrupt controllers, but is expecting one "
248 name(), interrupts
.size(), numThreads
);
249 for (ThreadID tid
= 0; tid
< numThreads
; tid
++)
250 interrupts
[tid
]->setCPU(this);
254 if (params()->profile
)
255 profileEvent
= new EventFunctionWrapper(
256 [this]{ processProfileEvent(); },
259 tracer
= params()->tracer
;
261 if (params()->isa
.size() != numThreads
) {
262 fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
263 "of threads (%i).\n", params()->isa
.size(), numThreads
);
268 BaseCPU::enableFunctionTrace()
270 functionTracingEnabled
= true;
276 delete[] comLoadEventQueue
;
277 delete[] comInstEventQueue
;
281 BaseCPU::armMonitor(ThreadID tid
, Addr address
)
283 assert(tid
< numThreads
);
284 AddressMonitor
&monitor
= addressMonitor
[tid
];
286 monitor
.armed
= true;
287 monitor
.vAddr
= address
;
289 DPRINTF(Mwait
,"[tid:%d] Armed monitor (vAddr=0x%lx)\n", tid
, address
);
293 BaseCPU::mwait(ThreadID tid
, PacketPtr pkt
)
295 assert(tid
< numThreads
);
296 AddressMonitor
&monitor
= addressMonitor
[tid
];
298 if (!monitor
.gotWakeup
) {
299 int block_size
= cacheLineSize();
300 uint64_t mask
= ~((uint64_t)(block_size
- 1));
302 assert(pkt
->req
->hasPaddr());
303 monitor
.pAddr
= pkt
->getAddr() & mask
;
304 monitor
.waiting
= true;
306 DPRINTF(Mwait
,"[tid:%d] mwait called (vAddr=0x%lx, "
307 "line's paddr=0x%lx)\n", tid
, monitor
.vAddr
, monitor
.pAddr
);
310 monitor
.gotWakeup
= false;
316 BaseCPU::mwaitAtomic(ThreadID tid
, ThreadContext
*tc
, BaseTLB
*dtb
)
318 assert(tid
< numThreads
);
319 AddressMonitor
&monitor
= addressMonitor
[tid
];
322 Addr addr
= monitor
.vAddr
;
323 int block_size
= cacheLineSize();
324 uint64_t mask
= ~((uint64_t)(block_size
- 1));
325 int size
= block_size
;
327 //The address of the next line if it crosses a cache line boundary.
328 Addr secondAddr
= roundDown(addr
+ size
- 1, block_size
);
330 if (secondAddr
> addr
)
331 size
= secondAddr
- addr
;
333 req
.setVirt(0, addr
, size
, 0x0, dataMasterId(), tc
->instAddr());
335 // translate to physical address
336 Fault fault
= dtb
->translateAtomic(&req
, tc
, BaseTLB::Read
);
337 assert(fault
== NoFault
);
339 monitor
.pAddr
= req
.getPaddr() & mask
;
340 monitor
.waiting
= true;
342 DPRINTF(Mwait
,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
343 tid
, monitor
.vAddr
, monitor
.pAddr
);
349 if (!params()->switched_out
) {
350 registerThreadContexts();
360 if (!params()->switched_out
&& profileEvent
)
361 schedule(profileEvent
, curTick());
364 if (params()->progress_interval
) {
365 new CPUProgressEvent(this, params()->progress_interval
);
369 ClockedObject::pwrState(Enums::PwrState::OFF
);
371 // Assumption CPU start to operate instantaneously without any latency
372 if (ClockedObject::pwrState() == Enums::PwrState::UNDEFINED
)
373 ClockedObject::pwrState(Enums::PwrState::ON
);
378 BaseCPU::pmuProbePoint(const char *name
)
380 ProbePoints::PMUUPtr ptr
;
381 ptr
.reset(new ProbePoints::PMU(getProbeManager(), name
));
387 BaseCPU::regProbePoints()
389 ppAllCycles
= pmuProbePoint("Cycles");
390 ppActiveCycles
= pmuProbePoint("ActiveCycles");
392 ppRetiredInsts
= pmuProbePoint("RetiredInsts");
393 ppRetiredLoads
= pmuProbePoint("RetiredLoads");
394 ppRetiredStores
= pmuProbePoint("RetiredStores");
395 ppRetiredBranches
= pmuProbePoint("RetiredBranches");
397 ppSleeping
= new ProbePointArg
<bool>(this->getProbeManager(),
402 BaseCPU::probeInstCommit(const StaticInstPtr
&inst
)
404 if (!inst
->isMicroop() || inst
->isLastMicroop())
405 ppRetiredInsts
->notify(1);
409 ppRetiredLoads
->notify(1);
412 ppRetiredStores
->notify(1);
414 if (inst
->isControl())
415 ppRetiredBranches
->notify(1);
421 MemObject::regStats();
423 using namespace Stats
;
426 .name(name() + ".numCycles")
427 .desc("number of cpu cycles simulated")
431 .name(name() + ".numWorkItemsStarted")
432 .desc("number of work items this cpu started")
435 numWorkItemsCompleted
436 .name(name() + ".numWorkItemsCompleted")
437 .desc("number of work items this cpu completed")
440 int size
= threadContexts
.size();
442 for (int i
= 0; i
< size
; ++i
) {
443 stringstream namestr
;
444 ccprintf(namestr
, "%s.ctx%d", name(), i
);
445 threadContexts
[i
]->regStats(namestr
.str());
447 } else if (size
== 1)
448 threadContexts
[0]->regStats(name());
452 BaseCPU::getMasterPort(const string
&if_name
, PortID idx
)
454 // Get the right port based on name. This applies to all the
455 // subclasses of the base CPU and relies on their implementation
456 // of getDataPort and getInstPort. In all cases there methods
457 // return a MasterPort pointer.
458 if (if_name
== "dcache_port")
459 return getDataPort();
460 else if (if_name
== "icache_port")
461 return getInstPort();
463 return MemObject::getMasterPort(if_name
, idx
);
467 BaseCPU::registerThreadContexts()
469 assert(system
->multiThread
|| numThreads
== 1);
471 ThreadID size
= threadContexts
.size();
472 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
473 ThreadContext
*tc
= threadContexts
[tid
];
475 if (system
->multiThread
) {
476 tc
->setContextId(system
->registerThreadContext(tc
));
478 tc
->setContextId(system
->registerThreadContext(tc
, _cpuId
));
482 tc
->getProcessPtr()->assignThreadContext(tc
->contextId());
487 BaseCPU::deschedulePowerGatingEvent()
489 if (enterPwrGatingEvent
.scheduled()){
490 deschedule(enterPwrGatingEvent
);
495 BaseCPU::schedulePowerGatingEvent()
497 for (auto tc
: threadContexts
) {
498 if (tc
->status() == ThreadContext::Active
)
502 if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED
&&
504 assert(!enterPwrGatingEvent
.scheduled());
505 // Schedule a power gating event when clock gated for the specified
507 schedule(enterPwrGatingEvent
, clockEdge(pwrGatingLatency
));
512 BaseCPU::findContext(ThreadContext
*tc
)
514 ThreadID size
= threadContexts
.size();
515 for (ThreadID tid
= 0; tid
< size
; ++tid
) {
516 if (tc
== threadContexts
[tid
])
523 BaseCPU::activateContext(ThreadID thread_num
)
525 // Squash enter power gating event while cpu gets activated
526 if (enterPwrGatingEvent
.scheduled())
527 deschedule(enterPwrGatingEvent
);
528 // For any active thread running, update CPU power state to active (ON)
529 ClockedObject::pwrState(Enums::PwrState::ON
);
531 updateCycleCounters(CPU_STATE_WAKEUP
);
535 BaseCPU::suspendContext(ThreadID thread_num
)
537 // Check if all threads are suspended
538 for (auto t
: threadContexts
) {
539 if (t
->status() != ThreadContext::Suspended
) {
544 // All CPU thread are suspended, update cycle count
545 updateCycleCounters(CPU_STATE_SLEEP
);
547 // All CPU threads suspended, enter lower power state for the CPU
548 ClockedObject::pwrState(Enums::PwrState::CLK_GATED
);
550 // If pwrGatingLatency is set to 0 then this mechanism is disabled
551 if (powerGatingOnIdle
) {
552 // Schedule power gating event when clock gated for pwrGatingLatency
554 schedule(enterPwrGatingEvent
, clockEdge(pwrGatingLatency
));
559 BaseCPU::haltContext(ThreadID thread_num
)
561 updateCycleCounters(BaseCPU::CPU_STATE_SLEEP
);
565 BaseCPU::enterPwrGating(void)
567 ClockedObject::pwrState(Enums::PwrState::OFF
);
573 assert(!_switchedOut
);
575 if (profileEvent
&& profileEvent
->scheduled())
576 deschedule(profileEvent
);
578 // Flush all TLBs in the CPU to avoid having stale translations if
579 // it gets switched in later.
582 // Go to the power gating state
583 ClockedObject::pwrState(Enums::PwrState::OFF
);
587 BaseCPU::takeOverFrom(BaseCPU
*oldCPU
)
589 assert(threadContexts
.size() == oldCPU
->threadContexts
.size());
590 assert(_cpuId
== oldCPU
->cpuId());
591 assert(_switchedOut
);
592 assert(oldCPU
!= this);
593 _pid
= oldCPU
->getPid();
594 _taskId
= oldCPU
->taskId();
595 // Take over the power state of the switchedOut CPU
596 ClockedObject::pwrState(oldCPU
->pwrState());
598 previousState
= oldCPU
->previousState
;
599 previousCycle
= oldCPU
->previousCycle
;
601 _switchedOut
= false;
603 ThreadID size
= threadContexts
.size();
604 for (ThreadID i
= 0; i
< size
; ++i
) {
605 ThreadContext
*newTC
= threadContexts
[i
];
606 ThreadContext
*oldTC
= oldCPU
->threadContexts
[i
];
608 newTC
->takeOverFrom(oldTC
);
610 CpuEvent::replaceThreadContext(oldTC
, newTC
);
612 assert(newTC
->contextId() == oldTC
->contextId());
613 assert(newTC
->threadId() == oldTC
->threadId());
614 system
->replaceThreadContext(newTC
, newTC
->contextId());
616 /* This code no longer works since the zero register (e.g.,
617 * r31 on Alpha) doesn't necessarily contain zero at this
620 ThreadContext::compare(oldTC, newTC);
623 BaseMasterPort
*old_itb_port
= oldTC
->getITBPtr()->getMasterPort();
624 BaseMasterPort
*old_dtb_port
= oldTC
->getDTBPtr()->getMasterPort();
625 BaseMasterPort
*new_itb_port
= newTC
->getITBPtr()->getMasterPort();
626 BaseMasterPort
*new_dtb_port
= newTC
->getDTBPtr()->getMasterPort();
628 // Move over any table walker ports if they exist
630 assert(!new_itb_port
->isConnected());
631 assert(old_itb_port
);
632 assert(old_itb_port
->isConnected());
633 BaseSlavePort
&slavePort
= old_itb_port
->getSlavePort();
634 old_itb_port
->unbind();
635 new_itb_port
->bind(slavePort
);
638 assert(!new_dtb_port
->isConnected());
639 assert(old_dtb_port
);
640 assert(old_dtb_port
->isConnected());
641 BaseSlavePort
&slavePort
= old_dtb_port
->getSlavePort();
642 old_dtb_port
->unbind();
643 new_dtb_port
->bind(slavePort
);
645 newTC
->getITBPtr()->takeOverFrom(oldTC
->getITBPtr());
646 newTC
->getDTBPtr()->takeOverFrom(oldTC
->getDTBPtr());
648 // Checker whether or not we have to transfer CheckerCPU
649 // objects over in the switch
650 CheckerCPU
*oldChecker
= oldTC
->getCheckerCpuPtr();
651 CheckerCPU
*newChecker
= newTC
->getCheckerCpuPtr();
652 if (oldChecker
&& newChecker
) {
653 BaseMasterPort
*old_checker_itb_port
=
654 oldChecker
->getITBPtr()->getMasterPort();
655 BaseMasterPort
*old_checker_dtb_port
=
656 oldChecker
->getDTBPtr()->getMasterPort();
657 BaseMasterPort
*new_checker_itb_port
=
658 newChecker
->getITBPtr()->getMasterPort();
659 BaseMasterPort
*new_checker_dtb_port
=
660 newChecker
->getDTBPtr()->getMasterPort();
662 newChecker
->getITBPtr()->takeOverFrom(oldChecker
->getITBPtr());
663 newChecker
->getDTBPtr()->takeOverFrom(oldChecker
->getDTBPtr());
665 // Move over any table walker ports if they exist for checker
666 if (new_checker_itb_port
) {
667 assert(!new_checker_itb_port
->isConnected());
668 assert(old_checker_itb_port
);
669 assert(old_checker_itb_port
->isConnected());
670 BaseSlavePort
&slavePort
=
671 old_checker_itb_port
->getSlavePort();
672 old_checker_itb_port
->unbind();
673 new_checker_itb_port
->bind(slavePort
);
675 if (new_checker_dtb_port
) {
676 assert(!new_checker_dtb_port
->isConnected());
677 assert(old_checker_dtb_port
);
678 assert(old_checker_dtb_port
->isConnected());
679 BaseSlavePort
&slavePort
=
680 old_checker_dtb_port
->getSlavePort();
681 old_checker_dtb_port
->unbind();
682 new_checker_dtb_port
->bind(slavePort
);
687 interrupts
= oldCPU
->interrupts
;
688 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
689 interrupts
[tid
]->setCPU(this);
691 oldCPU
->interrupts
.clear();
694 for (ThreadID i
= 0; i
< size
; ++i
)
695 threadContexts
[i
]->profileClear();
698 schedule(profileEvent
, curTick());
701 // All CPUs have an instruction and a data port, and the new CPU's
702 // ports are dangling while the old CPU has its ports connected
703 // already. Unbind the old CPU and then bind the ports of the one
704 // we are switching to.
705 assert(!getInstPort().isConnected());
706 assert(oldCPU
->getInstPort().isConnected());
707 BaseSlavePort
&inst_peer_port
= oldCPU
->getInstPort().getSlavePort();
708 oldCPU
->getInstPort().unbind();
709 getInstPort().bind(inst_peer_port
);
711 assert(!getDataPort().isConnected());
712 assert(oldCPU
->getDataPort().isConnected());
713 BaseSlavePort
&data_peer_port
= oldCPU
->getDataPort().getSlavePort();
714 oldCPU
->getDataPort().unbind();
715 getDataPort().bind(data_peer_port
);
721 for (ThreadID i
= 0; i
< threadContexts
.size(); ++i
) {
722 ThreadContext
&tc(*threadContexts
[i
]);
723 CheckerCPU
*checker(tc
.getCheckerCpuPtr());
725 tc
.getITBPtr()->flushAll();
726 tc
.getDTBPtr()->flushAll();
728 checker
->getITBPtr()->flushAll();
729 checker
->getDTBPtr()->flushAll();
735 BaseCPU::processProfileEvent()
737 ThreadID size
= threadContexts
.size();
739 for (ThreadID i
= 0; i
< size
; ++i
)
740 threadContexts
[i
]->profileSample();
742 schedule(profileEvent
, curTick() + params()->profile
);
746 BaseCPU::serialize(CheckpointOut
&cp
) const
748 SERIALIZE_SCALAR(instCnt
);
751 /* Unlike _pid, _taskId is not serialized, as they are dynamically
752 * assigned unique ids that are only meaningful for the duration of
753 * a specific run. We will need to serialize the entire taskMap in
755 SERIALIZE_SCALAR(_pid
);
757 // Serialize the threads, this is done by the CPU implementation.
758 for (ThreadID i
= 0; i
< numThreads
; ++i
) {
759 ScopedCheckpointSection
sec(cp
, csprintf("xc.%i", i
));
760 interrupts
[i
]->serialize(cp
);
761 serializeThread(cp
, i
);
767 BaseCPU::unserialize(CheckpointIn
&cp
)
769 UNSERIALIZE_SCALAR(instCnt
);
772 UNSERIALIZE_SCALAR(_pid
);
774 // Unserialize the threads, this is done by the CPU implementation.
775 for (ThreadID i
= 0; i
< numThreads
; ++i
) {
776 ScopedCheckpointSection
sec(cp
, csprintf("xc.%i", i
));
777 interrupts
[i
]->unserialize(cp
);
778 unserializeThread(cp
, i
);
784 BaseCPU::scheduleInstStop(ThreadID tid
, Counter insts
, const char *cause
)
786 const Tick
now(comInstEventQueue
[tid
]->getCurTick());
787 Event
*event(new LocalSimLoopExitEvent(cause
, 0));
789 comInstEventQueue
[tid
]->schedule(event
, now
+ insts
);
793 BaseCPU::getCurrentInstCount(ThreadID tid
)
795 return Tick(comInstEventQueue
[tid
]->getCurTick());
798 AddressMonitor::AddressMonitor() {
804 bool AddressMonitor::doMonitor(PacketPtr pkt
) {
805 assert(pkt
->req
->hasPaddr());
806 if (armed
&& waiting
) {
807 if (pAddr
== pkt
->getAddr()) {
808 DPRINTF(Mwait
,"pAddr=0x%lx invalidated: waking up core\n",
818 BaseCPU::scheduleLoadStop(ThreadID tid
, Counter loads
, const char *cause
)
820 const Tick
now(comLoadEventQueue
[tid
]->getCurTick());
821 Event
*event(new LocalSimLoopExitEvent(cause
, 0));
823 comLoadEventQueue
[tid
]->schedule(event
, now
+ loads
);
828 BaseCPU::traceFunctionsInternal(Addr pc
)
830 if (!debugSymbolTable
)
833 // if pc enters different function, print new function symbol and
834 // update saved range. Otherwise do nothing.
835 if (pc
< currentFunctionStart
|| pc
>= currentFunctionEnd
) {
837 bool found
= debugSymbolTable
->findNearestSymbol(pc
, sym_str
,
838 currentFunctionStart
,
842 // no symbol found: use addr as label
843 sym_str
= csprintf("0x%x", pc
);
844 currentFunctionStart
= pc
;
845 currentFunctionEnd
= pc
+ 1;
848 ccprintf(*functionTraceStream
, " (%d)\n%d: %s",
849 curTick() - functionEntryTick
, curTick(), sym_str
);
850 functionEntryTick
= curTick();
855 BaseCPU::waitForRemoteGDB() const
857 return params()->wait_for_remote_gdb
;