2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
36 #include "base/cprintf.hh"
37 #include "base/loader/symtab.hh"
38 #include "base/misc.hh"
39 #include "base/output.hh"
40 #include "cpu/base.hh"
41 #include "cpu/cpuevent.hh"
42 #include "cpu/thread_context.hh"
43 #include "cpu/profile.hh"
44 #include "cpu/sampler/sampler.hh"
45 #include "sim/param.hh"
46 #include "sim/process.hh"
47 #include "sim/sim_events.hh"
48 #include "sim/system.hh"
50 #include "base/trace.hh"
54 vector
<BaseCPU
*> BaseCPU::cpuList
;
56 // This variable reflects the max number of threads in any CPU. Be
57 // careful to only use it once all the CPUs that you care about have
59 int maxThreadsPerCPU
= 1;
62 BaseCPU::BaseCPU(Params
*p
)
63 : SimObject(p
->name
), clock(p
->clock
), checkInterrupts(true),
64 params(p
), number_of_threads(p
->numberOfThreads
), system(p
->system
)
66 BaseCPU::BaseCPU(Params
*p
)
67 : SimObject(p
->name
), clock(p
->clock
), params(p
),
68 number_of_threads(p
->numberOfThreads
), system(p
->system
)
71 DPRINTF(FullCPU
, "BaseCPU: Creating object, mem address %#x.\n", this);
73 // add self to global list of CPUs
74 cpuList
.push_back(this);
76 DPRINTF(FullCPU
, "BaseCPU: CPU added to cpuList, mem address %#x.\n",
79 if (number_of_threads
> maxThreadsPerCPU
)
80 maxThreadsPerCPU
= number_of_threads
;
82 // allocate per-thread instruction-based event queues
83 comInstEventQueue
= new EventQueue
*[number_of_threads
];
84 for (int i
= 0; i
< number_of_threads
; ++i
)
85 comInstEventQueue
[i
] = new EventQueue("instruction-based event queue");
88 // set up instruction-count-based termination events, if any
90 if (p
->max_insts_any_thread
!= 0)
91 for (int i
= 0; i
< number_of_threads
; ++i
)
92 new SimLoopExitEvent(comInstEventQueue
[i
], p
->max_insts_any_thread
,
93 "a thread reached the max instruction count");
95 if (p
->max_insts_all_threads
!= 0) {
96 // allocate & initialize shared downcounter: each event will
97 // decrement this when triggered; simulation will terminate
98 // when counter reaches 0
99 int *counter
= new int;
100 *counter
= number_of_threads
;
101 for (int i
= 0; i
< number_of_threads
; ++i
)
102 new CountedExitEvent(comInstEventQueue
[i
],
103 "all threads reached the max instruction count",
104 p
->max_insts_all_threads
, *counter
);
107 // allocate per-thread load-based event queues
108 comLoadEventQueue
= new EventQueue
*[number_of_threads
];
109 for (int i
= 0; i
< number_of_threads
; ++i
)
110 comLoadEventQueue
[i
] = new EventQueue("load-based event queue");
113 // set up instruction-count-based termination events, if any
115 if (p
->max_loads_any_thread
!= 0)
116 for (int i
= 0; i
< number_of_threads
; ++i
)
117 new SimLoopExitEvent(comLoadEventQueue
[i
], p
->max_loads_any_thread
,
118 "a thread reached the max load count");
120 if (p
->max_loads_all_threads
!= 0) {
121 // allocate & initialize shared downcounter: each event will
122 // decrement this when triggered; simulation will terminate
123 // when counter reaches 0
124 int *counter
= new int;
125 *counter
= number_of_threads
;
126 for (int i
= 0; i
< number_of_threads
; ++i
)
127 new CountedExitEvent(comLoadEventQueue
[i
],
128 "all threads reached the max load count",
129 p
->max_loads_all_threads
, *counter
);
133 memset(interrupts
, 0, sizeof(interrupts
));
137 functionTracingEnabled
= false;
138 if (p
->functionTrace
) {
139 functionTraceStream
= simout
.find(csprintf("ftrace.%s", name()));
140 currentFunctionStart
= currentFunctionEnd
= 0;
141 functionEntryTick
= p
->functionTraceStart
;
143 if (p
->functionTraceStart
== 0) {
144 functionTracingEnabled
= true;
147 new EventWrapper
<BaseCPU
, &BaseCPU::enableFunctionTrace
>(this,
149 e
->schedule(p
->functionTraceStart
);
155 profileEvent
= new ProfileEvent(this, params
->profile
);
160 BaseCPU::Params::Params()
169 BaseCPU::enableFunctionTrace()
171 functionTracingEnabled
= true;
181 if (!params
->deferRegistration
)
182 registerThreadContexts();
189 if (!params
->deferRegistration
&& profileEvent
)
190 profileEvent
->schedule(curTick
);
198 using namespace Stats
;
201 .name(name() + ".numCycles")
202 .desc("number of cpu cycles simulated")
205 int size
= threadContexts
.size();
207 for (int i
= 0; i
< size
; ++i
) {
208 stringstream namestr
;
209 ccprintf(namestr
, "%s.ctx%d", name(), i
);
210 threadContexts
[i
]->regStats(namestr
.str());
212 } else if (size
== 1)
213 threadContexts
[0]->regStats(name());
221 BaseCPU::registerThreadContexts()
223 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
224 ThreadContext
*tc
= threadContexts
[i
];
227 int id
= params
->cpu_id
;
231 tc
->setCpuId(system
->registerThreadContext(tc
, id
));
233 tc
->setCpuId(tc
->getProcessPtr()->registerThreadContext(tc
));
242 panic("This CPU doesn't support sampling!");
246 BaseCPU::takeOverFrom(BaseCPU
*oldCPU
)
248 assert(threadContexts
.size() == oldCPU
->threadContexts
.size());
250 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
251 ThreadContext
*newTC
= threadContexts
[i
];
252 ThreadContext
*oldTC
= oldCPU
->threadContexts
[i
];
254 newTC
->takeOverFrom(oldTC
);
256 CpuEvent::replaceThreadContext(oldTC
, newTC
);
258 assert(newTC
->readCpuId() == oldTC
->readCpuId());
260 system
->replaceThreadContext(newTC
, newTC
->readCpuId());
262 assert(newTC
->getProcessPtr() == oldTC
->getProcessPtr());
263 newTC
->getProcessPtr()->replaceThreadContext(newTC
, newTC
->readCpuId());
268 for (int i
= 0; i
< TheISA::NumInterruptLevels
; ++i
)
269 interrupts
[i
] = oldCPU
->interrupts
[i
];
270 intstatus
= oldCPU
->intstatus
;
272 for (int i
= 0; i
< threadContexts
.size(); ++i
)
273 threadContexts
[i
]->profileClear();
276 profileEvent
->schedule(curTick
);
282 BaseCPU::ProfileEvent::ProfileEvent(BaseCPU
*_cpu
, int _interval
)
283 : Event(&mainEventQueue
), cpu(_cpu
), interval(_interval
)
287 BaseCPU::ProfileEvent::process()
289 for (int i
= 0, size
= cpu
->threadContexts
.size(); i
< size
; ++i
) {
290 ThreadContext
*tc
= cpu
->threadContexts
[i
];
294 schedule(curTick
+ interval
);
298 BaseCPU::post_interrupt(int int_num
, int index
)
300 DPRINTF(Interrupt
, "Interrupt %d:%d posted\n", int_num
, index
);
302 if (int_num
< 0 || int_num
>= TheISA::NumInterruptLevels
)
303 panic("int_num out of bounds\n");
305 if (index
< 0 || index
>= sizeof(uint64_t) * 8)
306 panic("int_num out of bounds\n");
308 checkInterrupts
= true;
309 interrupts
[int_num
] |= 1 << index
;
310 intstatus
|= (ULL(1) << int_num
);
314 BaseCPU::clear_interrupt(int int_num
, int index
)
316 DPRINTF(Interrupt
, "Interrupt %d:%d cleared\n", int_num
, index
);
318 if (int_num
< 0 || int_num
>= TheISA::NumInterruptLevels
)
319 panic("int_num out of bounds\n");
321 if (index
< 0 || index
>= sizeof(uint64_t) * 8)
322 panic("int_num out of bounds\n");
324 interrupts
[int_num
] &= ~(1 << index
);
325 if (interrupts
[int_num
] == 0)
326 intstatus
&= ~(ULL(1) << int_num
);
330 BaseCPU::clear_interrupts()
332 DPRINTF(Interrupt
, "Interrupts all cleared\n");
334 memset(interrupts
, 0, sizeof(interrupts
));
340 BaseCPU::serialize(std::ostream
&os
)
342 SERIALIZE_ARRAY(interrupts
, TheISA::NumInterruptLevels
);
343 SERIALIZE_SCALAR(intstatus
);
347 BaseCPU::unserialize(Checkpoint
*cp
, const std::string
§ion
)
349 UNSERIALIZE_ARRAY(interrupts
, TheISA::NumInterruptLevels
);
350 UNSERIALIZE_SCALAR(intstatus
);
353 #endif // FULL_SYSTEM
356 BaseCPU::traceFunctionsInternal(Addr pc
)
358 if (!debugSymbolTable
)
361 // if pc enters different function, print new function symbol and
362 // update saved range. Otherwise do nothing.
363 if (pc
< currentFunctionStart
|| pc
>= currentFunctionEnd
) {
365 bool found
= debugSymbolTable
->findNearestSymbol(pc
, sym_str
,
366 currentFunctionStart
,
370 // no symbol found: use addr as label
371 sym_str
= csprintf("0x%x", pc
);
372 currentFunctionStart
= pc
;
373 currentFunctionEnd
= pc
+ 1;
376 ccprintf(*functionTraceStream
, " (%d)\n%d: %s",
377 curTick
- functionEntryTick
, curTick
, sym_str
);
378 functionEntryTick
= curTick
;
383 DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU
)