src/cpu/base.hh

   1 /*
   2  * Copyright (c) 2011-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2011 Regents of the University of California
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Steve Reinhardt
  42  *          Nathan Binkert
  43  *          Rick Strong
  44  */
  45
  46 #ifndef __CPU_BASE_HH__
  47 #define __CPU_BASE_HH__
  48
  49 #include <vector>
  50
  51 // Before we do anything else, check if this build is the NULL ISA,
  52 // and if so stop here
  53 #include "config/the_isa.hh"
  54 #if THE_ISA == NULL_ISA
  55 #include "arch/null/cpu_dummy.hh"
  56 #else
  57 #include "arch/interrupts.hh"
  58 #include "arch/isa_traits.hh"
  59 #include "arch/microcode_rom.hh"
  60 #include "base/statistics.hh"
  61 #include "mem/mem_object.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/full_system.hh"
  64 #include "sim/insttracer.hh"
  65 #include "sim/probe/pmu.hh"
  66 #include "sim/system.hh"
  67 #include "debug/Mwait.hh"
  68
  69 class BaseCPU;
  70 struct BaseCPUParams;
  71 class CheckerCPU;
  72 class ThreadContext;
  73
  74 struct AddressMonitor
  75 {
  76     AddressMonitor();
  77     bool doMonitor(PacketPtr pkt);
  78
  79     bool armed;
  80     Addr vAddr;
  81     Addr pAddr;
  82     uint64_t val;
  83     bool waiting;   // 0=normal, 1=mwaiting
  84     bool gotWakeup;
  85 };
  86
  87 class CPUProgressEvent : public Event
  88 {
  89   protected:
  90     Tick _interval;
  91     Counter lastNumInst;
  92     BaseCPU *cpu;
  93     bool _repeatEvent;
  94
  95   public:
  96     CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
  97
  98     void process();
  99
 100     void interval(Tick ival) { _interval = ival; }
 101     Tick interval() { return _interval; }
 102
 103     void repeatEvent(bool repeat) { _repeatEvent = repeat; }
 104
 105     virtual const char *description() const;
 106 };
 107
 108 class BaseCPU : public MemObject
 109 {
 110   protected:
 111
 112     /// Instruction count used for SPARC misc register
 113     /// @todo unify this with the counters that cpus individually keep
 114     Tick instCnt;
 115
 116     // every cpu has an id, put it in the base cpu
 117     // Set at initialization, only time a cpuId might change is during a
 118     // takeover (which should be done from within the BaseCPU anyway,
 119     // therefore no setCpuId() method is provided
 120     int _cpuId;
 121
 122     /** Each cpu will have a socket ID that corresponds to its physical location
 123      * in the system. This is usually used to bucket cpu cores under single DVFS
 124      * domain. This information may also be required by the OS to identify the
 125      * cpu core grouping (as in the case of ARM via MPIDR register)
 126      */
 127     const uint32_t _socketId;
 128
 129     /** instruction side request id that must be placed in all requests */
 130     MasterID _instMasterId;
 131
 132     /** data side request id that must be placed in all requests */
 133     MasterID _dataMasterId;
 134
 135     /** An intrenal representation of a task identifier within gem5. This is
 136      * used so the CPU can add which taskId (which is an internal representation
 137      * of the OS process ID) to each request so components in the memory system
 138      * can track which process IDs are ultimately interacting with them
 139      */
 140     uint32_t _taskId;
 141
 142     /** The current OS process ID that is executing on this processor. This is
 143      * used to generate a taskId */
 144     uint32_t _pid;
 145
 146     /** Is the CPU switched out or active? */
 147     bool _switchedOut;
 148
 149     /** Cache the cache line size that we get from the system */
 150     const unsigned int _cacheLineSize;
 151
 152   public:
 153
 154     /**
 155      * Purely virtual method that returns a reference to the data
 156      * port. All subclasses must implement this method.
 157      *
 158      * @return a reference to the data port
 159      */
 160     virtual MasterPort &getDataPort() = 0;
 161
 162     /**
 163      * Purely virtual method that returns a reference to the instruction
 164      * port. All subclasses must implement this method.
 165      *
 166      * @return a reference to the instruction port
 167      */
 168     virtual MasterPort &getInstPort() = 0;
 169
 170     /** Reads this CPU's ID. */
 171     int cpuId() const { return _cpuId; }
 172
 173     /** Reads this CPU's Socket ID. */
 174     uint32_t socketId() const { return _socketId; }
 175
 176     /** Reads this CPU's unique data requestor ID */
 177     MasterID dataMasterId() { return _dataMasterId; }
 178     /** Reads this CPU's unique instruction requestor ID */
 179     MasterID instMasterId() { return _instMasterId; }
 180
 181     /**
 182      * Get a master port on this CPU. All CPUs have a data and
 183      * instruction port, and this method uses getDataPort and
 184      * getInstPort of the subclasses to resolve the two ports.
 185      *
 186      * @param if_name the port name
 187      * @param idx ignored index
 188      *
 189      * @return a reference to the port with the given name
 190      */
 191     BaseMasterPort &getMasterPort(const std::string &if_name,
 192                                   PortID idx = InvalidPortID) override;
 193
 194     /** Get cpu task id */
 195     uint32_t taskId() const { return _taskId; }
 196     /** Set cpu task id */
 197     void taskId(uint32_t id) { _taskId = id; }
 198
 199     uint32_t getPid() const { return _pid; }
 200     void setPid(uint32_t pid) { _pid = pid; }
 201
 202     inline void workItemBegin() { numWorkItemsStarted++; }
 203     inline void workItemEnd() { numWorkItemsCompleted++; }
 204     // @todo remove me after debugging with legion done
 205     Tick instCount() { return instCnt; }
 206
 207     TheISA::MicrocodeRom microcodeRom;
 208
 209   protected:
 210     std::vector<TheISA::Interrupts*> interrupts;
 211
 212   public:
 213     TheISA::Interrupts *
 214     getInterruptController(ThreadID tid)
 215     {
 216         if (interrupts.empty())
 217             return NULL;
 218
 219         assert(interrupts.size() > tid);
 220         return interrupts[tid];
 221     }
 222
 223     virtual void wakeup(ThreadID tid) = 0;
 224
 225     void
 226     postInterrupt(ThreadID tid, int int_num, int index)
 227     {
 228         interrupts[tid]->post(int_num, index);
 229         if (FullSystem)
 230             wakeup(tid);
 231     }
 232
 233     void
 234     clearInterrupt(ThreadID tid, int int_num, int index)
 235     {
 236         interrupts[tid]->clear(int_num, index);
 237     }
 238
 239     void
 240     clearInterrupts(ThreadID tid)
 241     {
 242         interrupts[tid]->clearAll();
 243     }
 244
 245     bool
 246     checkInterrupts(ThreadContext *tc) const
 247     {
 248         return FullSystem && interrupts[tc->threadId()]->checkInterrupts(tc);
 249     }
 250
 251     class ProfileEvent : public Event
 252     {
 253       private:
 254         BaseCPU *cpu;
 255         Tick interval;
 256
 257       public:
 258         ProfileEvent(BaseCPU *cpu, Tick interval);
 259         void process();
 260     };
 261     ProfileEvent *profileEvent;
 262
 263   protected:
 264     std::vector<ThreadContext *> threadContexts;
 265
 266     Trace::InstTracer * tracer;
 267
 268   public:
 269
 270
 271     /** Invalid or unknown Pid. Possible when operating system is not present
 272      *  or has not assigned a pid yet */
 273     static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
 274
 275     // Mask to align PCs to MachInst sized boundaries
 276     static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
 277
 278     /// Provide access to the tracer pointer
 279     Trace::InstTracer * getTracer() { return tracer; }
 280
 281     /// Notify the CPU that the indicated context is now active.
 282     virtual void activateContext(ThreadID thread_num);
 283
 284     /// Notify the CPU that the indicated context is now suspended.
 285     /// Check if possible to enter a lower power state
 286     virtual void suspendContext(ThreadID thread_num);
 287
 288     /// Notify the CPU that the indicated context is now halted.
 289     virtual void haltContext(ThreadID thread_num) {}
 290
 291    /// Given a Thread Context pointer return the thread num
 292    int findContext(ThreadContext *tc);
 293
 294    /// Given a thread num get tho thread context for it
 295    virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; }
 296
 297    /// Get the number of thread contexts available
 298    unsigned numContexts() { return threadContexts.size(); }
 299
 300     /// Convert ContextID to threadID
 301     ThreadID contextToThread(ContextID cid)
 302     { return static_cast<ThreadID>(cid - threadContexts[0]->contextId()); }
 303
 304   public:
 305     typedef BaseCPUParams Params;
 306     const Params *params() const
 307     { return reinterpret_cast<const Params *>(_params); }
 308     BaseCPU(Params *params, bool is_checker = false);
 309     virtual ~BaseCPU();
 310
 311     void init() override;
 312     void startup() override;
 313     void regStats() override;
 314
 315     void regProbePoints() override;
 316
 317     void registerThreadContexts();
 318
 319     /**
 320      * Prepare for another CPU to take over execution.
 321      *
 322      * When this method exits, all internal state should have been
 323      * flushed. After the method returns, the simulator calls
 324      * takeOverFrom() on the new CPU with this CPU as its parameter.
 325      */
 326     virtual void switchOut();
 327
 328     /**
 329      * Load the state of a CPU from the previous CPU object, invoked
 330      * on all new CPUs that are about to be switched in.
 331      *
 332      * A CPU model implementing this method is expected to initialize
 333      * its state from the old CPU and connect its memory (unless they
 334      * are already connected) to the memories connected to the old
 335      * CPU.
 336      *
 337      * @param cpu CPU to initialize read state from.
 338      */
 339     virtual void takeOverFrom(BaseCPU *cpu);
 340
 341     /**
 342      * Flush all TLBs in the CPU.
 343      *
 344      * This method is mainly used to flush stale translations when
 345      * switching CPUs. It is also exported to the Python world to
 346      * allow it to request a TLB flush after draining the CPU to make
 347      * it easier to compare traces when debugging
 348      * handover/checkpointing.
 349      */
 350     void flushTLBs();
 351
 352     /**
 353      * Determine if the CPU is switched out.
 354      *
 355      * @return True if the CPU is switched out, false otherwise.
 356      */
 357     bool switchedOut() const { return _switchedOut; }
 358
 359     /**
 360      * Verify that the system is in a memory mode supported by the
 361      * CPU.
 362      *
 363      * Implementations are expected to query the system for the
 364      * current memory mode and ensure that it is what the CPU model
 365      * expects. If the check fails, the implementation should
 366      * terminate the simulation using fatal().
 367      */
 368     virtual void verifyMemoryMode() const { };
 369
 370     /**
 371      *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
 372      * This is a constant for the duration of the simulation.
 373      */
 374     ThreadID numThreads;
 375
 376     /**
 377      * Vector of per-thread instruction-based event queues.  Used for
 378      * scheduling events based on number of instructions committed by
 379      * a particular thread.
 380      */
 381     EventQueue **comInstEventQueue;
 382
 383     /**
 384      * Vector of per-thread load-based event queues.  Used for
 385      * scheduling events based on number of loads committed by
 386      *a particular thread.
 387      */
 388     EventQueue **comLoadEventQueue;
 389
 390     System *system;
 391
 392     /**
 393      * Get the cache line size of the system.
 394      */
 395     inline unsigned int cacheLineSize() const { return _cacheLineSize; }
 396
 397     /**
 398      * Serialize this object to the given output stream.
 399      *
 400      * @note CPU models should normally overload the serializeThread()
 401      * method instead of the serialize() method as this provides a
 402      * uniform data format for all CPU models and promotes better code
 403      * reuse.
 404      *
 405      * @param os The stream to serialize to.
 406      */
 407     void serialize(CheckpointOut &cp) const override;
 408
 409     /**
 410      * Reconstruct the state of this object from a checkpoint.
 411      *
 412      * @note CPU models should normally overload the
 413      * unserializeThread() method instead of the unserialize() method
 414      * as this provides a uniform data format for all CPU models and
 415      * promotes better code reuse.
 416
 417      * @param cp The checkpoint use.
 418      * @param section The section name of this object.
 419      */
 420     void unserialize(CheckpointIn &cp) override;
 421
 422     /**
 423      * Serialize a single thread.
 424      *
 425      * @param os The stream to serialize to.
 426      * @param tid ID of the current thread.
 427      */
 428     virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {};
 429
 430     /**
 431      * Unserialize one thread.
 432      *
 433      * @param cp The checkpoint use.
 434      * @param section The section name of this thread.
 435      * @param tid ID of the current thread.
 436      */
 437     virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {};
 438
 439     virtual Counter totalInsts() const = 0;
 440
 441     virtual Counter totalOps() const = 0;
 442
 443     /**
 444      * Schedule an event that exits the simulation loops after a
 445      * predefined number of instructions.
 446      *
 447      * This method is usually called from the configuration script to
 448      * get an exit event some time in the future. It is typically used
 449      * when the script wants to simulate for a specific number of
 450      * instructions rather than ticks.
 451      *
 452      * @param tid Thread monitor.
 453      * @param insts Number of instructions into the future.
 454      * @param cause Cause to signal in the exit event.
 455      */
 456     void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
 457
 458     /**
 459      * Schedule an event that exits the simulation loops after a
 460      * predefined number of load operations.
 461      *
 462      * This method is usually called from the configuration script to
 463      * get an exit event some time in the future. It is typically used
 464      * when the script wants to simulate for a specific number of
 465      * loads rather than ticks.
 466      *
 467      * @param tid Thread monitor.
 468      * @param loads Number of load instructions into the future.
 469      * @param cause Cause to signal in the exit event.
 470      */
 471     void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
 472
 473     /**
 474      * Get the number of instructions executed by the specified thread
 475      * on this CPU. Used by Python to control simulation.
 476      *
 477      * @param tid Thread monitor
 478      * @return Number of instructions executed
 479      */
 480     uint64_t getCurrentInstCount(ThreadID tid);
 481
 482   public:
 483     /**
 484      * @{
 485      * @name PMU Probe points.
 486      */
 487
 488     /**
 489      * Helper method to trigger PMU probes for a committed
 490      * instruction.
 491      *
 492      * @param inst Instruction that just committed
 493      */
 494     virtual void probeInstCommit(const StaticInstPtr &inst);
 495
 496     /**
 497      * Helper method to instantiate probe points belonging to this
 498      * object.
 499      *
 500      * @param name Name of the probe point.
 501      * @return A unique_ptr to the new probe point.
 502      */
 503     ProbePoints::PMUUPtr pmuProbePoint(const char *name);
 504
 505     /** CPU cycle counter */
 506     ProbePoints::PMUUPtr ppCycles;
 507
 508     /**
 509      * Instruction commit probe point.
 510      *
 511      * This probe point is triggered whenever one or more instructions
 512      * are committed. It is normally triggered once for every
 513      * instruction. However, CPU models committing bundles of
 514      * instructions may call notify once for the entire bundle.
 515      */
 516     ProbePoints::PMUUPtr ppRetiredInsts;
 517
 518     /** Retired load instructions */
 519     ProbePoints::PMUUPtr ppRetiredLoads;
 520     /** Retired store instructions */
 521     ProbePoints::PMUUPtr ppRetiredStores;
 522
 523     /** Retired branches (any type) */
 524     ProbePoints::PMUUPtr ppRetiredBranches;
 525
 526     /** @} */
 527
 528
 529
 530     // Function tracing
 531   private:
 532     bool functionTracingEnabled;
 533     std::ostream *functionTraceStream;
 534     Addr currentFunctionStart;
 535     Addr currentFunctionEnd;
 536     Tick functionEntryTick;
 537     void enableFunctionTrace();
 538     void traceFunctionsInternal(Addr pc);
 539
 540   private:
 541     static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
 542
 543   public:
 544     void traceFunctions(Addr pc)
 545     {
 546         if (functionTracingEnabled)
 547             traceFunctionsInternal(pc);
 548     }
 549
 550     static int numSimulatedCPUs() { return cpuList.size(); }
 551     static Counter numSimulatedInsts()
 552     {
 553         Counter total = 0;
 554
 555         int size = cpuList.size();
 556         for (int i = 0; i < size; ++i)
 557             total += cpuList[i]->totalInsts();
 558
 559         return total;
 560     }
 561
 562     static Counter numSimulatedOps()
 563     {
 564         Counter total = 0;
 565
 566         int size = cpuList.size();
 567         for (int i = 0; i < size; ++i)
 568             total += cpuList[i]->totalOps();
 569
 570         return total;
 571     }
 572
 573   public:
 574     // Number of CPU cycles simulated
 575     Stats::Scalar numCycles;
 576     Stats::Scalar numWorkItemsStarted;
 577     Stats::Scalar numWorkItemsCompleted;
 578
 579   private:
 580     std::vector<AddressMonitor> addressMonitor;
 581
 582   public:
 583     void armMonitor(ThreadID tid, Addr address);
 584     bool mwait(ThreadID tid, PacketPtr pkt);
 585     void mwaitAtomic(ThreadID tid, ThreadContext *tc, TheISA::TLB *dtb);
 586     AddressMonitor *getCpuAddrMonitor(ThreadID tid)
 587     {
 588         assert(tid < numThreads);
 589         return &addressMonitor[tid];
 590     }
 591
 592     Cycles syscallRetryLatency;
 593 };
 594
 595 #endif // THE_ISA == NULL_ISA
 596
 597 #endif // __CPU_BASE_HH__