src/cpu/base.hh

   1 /*
   2  * Copyright (c) 2011-2013, 2017, 2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2011 Regents of the University of California
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_BASE_HH__
  43 #define __CPU_BASE_HH__
  44
  45 #include <vector>
  46
  47 // Before we do anything else, check if this build is the NULL ISA,
  48 // and if so stop here
  49 #include "config/the_isa.hh"
  50 #if THE_ISA == NULL_ISA
  51 #error Including BaseCPU in a system without CPU support
  52 #else
  53 #include "arch/generic/interrupts.hh"
  54 #include "base/statistics.hh"
  55 #include "mem/port_proxy.hh"
  56 #include "sim/clocked_object.hh"
  57 #include "sim/eventq.hh"
  58 #include "sim/full_system.hh"
  59 #include "sim/insttracer.hh"
  60 #include "sim/probe/pmu.hh"
  61 #include "sim/probe/probe.hh"
  62 #include "sim/system.hh"
  63 #include "debug/Mwait.hh"
  64
  65 class BaseCPU;
  66 struct BaseCPUParams;
  67 class CheckerCPU;
  68 class ThreadContext;
  69
  70 struct AddressMonitor
  71 {
  72     AddressMonitor();
  73     bool doMonitor(PacketPtr pkt);
  74
  75     bool armed;
  76     Addr vAddr;
  77     Addr pAddr;
  78     uint64_t val;
  79     bool waiting;   // 0=normal, 1=mwaiting
  80     bool gotWakeup;
  81 };
  82
  83 class CPUProgressEvent : public Event
  84 {
  85   protected:
  86     Tick _interval;
  87     Counter lastNumInst;
  88     BaseCPU *cpu;
  89     bool _repeatEvent;
  90
  91   public:
  92     CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
  93
  94     void process();
  95
  96     void interval(Tick ival) { _interval = ival; }
  97     Tick interval() { return _interval; }
  98
  99     void repeatEvent(bool repeat) { _repeatEvent = repeat; }
 100
 101     virtual const char *description() const;
 102 };
 103
 104 class BaseCPU : public ClockedObject
 105 {
 106   protected:
 107
 108     /// Instruction count used for SPARC misc register
 109     /// @todo unify this with the counters that cpus individually keep
 110     Tick instCnt;
 111
 112     // every cpu has an id, put it in the base cpu
 113     // Set at initialization, only time a cpuId might change is during a
 114     // takeover (which should be done from within the BaseCPU anyway,
 115     // therefore no setCpuId() method is provided
 116     int _cpuId;
 117
 118     /** Each cpu will have a socket ID that corresponds to its physical location
 119      * in the system. This is usually used to bucket cpu cores under single DVFS
 120      * domain. This information may also be required by the OS to identify the
 121      * cpu core grouping (as in the case of ARM via MPIDR register)
 122      */
 123     const uint32_t _socketId;
 124
 125     /** instruction side request id that must be placed in all requests */
 126     RequestorID _instRequestorId;
 127
 128     /** data side request id that must be placed in all requests */
 129     RequestorID _dataRequestorId;
 130
 131     /** An intrenal representation of a task identifier within gem5. This is
 132      * used so the CPU can add which taskId (which is an internal representation
 133      * of the OS process ID) to each request so components in the memory system
 134      * can track which process IDs are ultimately interacting with them
 135      */
 136     uint32_t _taskId;
 137
 138     /** The current OS process ID that is executing on this processor. This is
 139      * used to generate a taskId */
 140     uint32_t _pid;
 141
 142     /** Is the CPU switched out or active? */
 143     bool _switchedOut;
 144
 145     /** Cache the cache line size that we get from the system */
 146     const unsigned int _cacheLineSize;
 147
 148     /** Global CPU statistics that are merged into the Root object. */
 149     struct GlobalStats : public Stats::Group {
 150         GlobalStats(::Stats::Group *parent);
 151
 152         ::Stats::Value simInsts;
 153         ::Stats::Value simOps;
 154
 155         ::Stats::Formula hostInstRate;
 156         ::Stats::Formula hostOpRate;
 157     };
 158
 159     /**
 160      * Pointer to the global stat structure. This needs to be
 161      * constructed from regStats since we merge it into the root
 162      * group. */
 163     static std::unique_ptr<GlobalStats> globalStats;
 164
 165   public:
 166
 167     /**
 168      * Purely virtual method that returns a reference to the data
 169      * port. All subclasses must implement this method.
 170      *
 171      * @return a reference to the data port
 172      */
 173     virtual Port &getDataPort() = 0;
 174
 175     /**
 176      * Returns a sendFunctional delegate for use with port proxies.
 177      */
 178     virtual PortProxy::SendFunctionalFunc
 179     getSendFunctional()
 180     {
 181         auto port = dynamic_cast<RequestPort *>(&getDataPort());
 182         assert(port);
 183         return [port](PacketPtr pkt)->void { port->sendFunctional(pkt); };
 184     }
 185
 186     /**
 187      * Purely virtual method that returns a reference to the instruction
 188      * port. All subclasses must implement this method.
 189      *
 190      * @return a reference to the instruction port
 191      */
 192     virtual Port &getInstPort() = 0;
 193
 194     /** Reads this CPU's ID. */
 195     int cpuId() const { return _cpuId; }
 196
 197     /** Reads this CPU's Socket ID. */
 198     uint32_t socketId() const { return _socketId; }
 199
 200     /** Reads this CPU's unique data requestor ID */
 201     RequestorID dataRequestorId() const { return _dataRequestorId; }
 202     /** Reads this CPU's unique instruction requestor ID */
 203     RequestorID instRequestorId() const { return _instRequestorId; }
 204
 205     /**
 206      * Get a port on this CPU. All CPUs have a data and
 207      * instruction port, and this method uses getDataPort and
 208      * getInstPort of the subclasses to resolve the two ports.
 209      *
 210      * @param if_name the port name
 211      * @param idx ignored index
 212      *
 213      * @return a reference to the port with the given name
 214      */
 215     Port &getPort(const std::string &if_name,
 216                   PortID idx=InvalidPortID) override;
 217
 218     /** Get cpu task id */
 219     uint32_t taskId() const { return _taskId; }
 220     /** Set cpu task id */
 221     void taskId(uint32_t id) { _taskId = id; }
 222
 223     uint32_t getPid() const { return _pid; }
 224     void setPid(uint32_t pid) { _pid = pid; }
 225
 226     inline void workItemBegin() { baseStats.numWorkItemsStarted++; }
 227     inline void workItemEnd() { baseStats.numWorkItemsCompleted++; }
 228     // @todo remove me after debugging with legion done
 229     Tick instCount() { return instCnt; }
 230
 231   protected:
 232     std::vector<BaseInterrupts*> interrupts;
 233
 234   public:
 235     BaseInterrupts *
 236     getInterruptController(ThreadID tid)
 237     {
 238         if (interrupts.empty())
 239             return NULL;
 240
 241         assert(interrupts.size() > tid);
 242         return interrupts[tid];
 243     }
 244
 245     virtual void wakeup(ThreadID tid) = 0;
 246
 247     void
 248     postInterrupt(ThreadID tid, int int_num, int index);
 249
 250     void
 251     clearInterrupt(ThreadID tid, int int_num, int index)
 252     {
 253         interrupts[tid]->clear(int_num, index);
 254     }
 255
 256     void
 257     clearInterrupts(ThreadID tid)
 258     {
 259         interrupts[tid]->clearAll();
 260     }
 261
 262     bool
 263     checkInterrupts(ThreadID tid) const
 264     {
 265         return FullSystem && interrupts[tid]->checkInterrupts();
 266     }
 267
 268   protected:
 269     std::vector<ThreadContext *> threadContexts;
 270
 271     Trace::InstTracer * tracer;
 272
 273   public:
 274
 275
 276     /** Invalid or unknown Pid. Possible when operating system is not present
 277      *  or has not assigned a pid yet */
 278     static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
 279
 280     // Mask to align PCs to MachInst sized boundaries
 281     static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
 282
 283     /// Provide access to the tracer pointer
 284     Trace::InstTracer * getTracer() { return tracer; }
 285
 286     /// Notify the CPU that the indicated context is now active.
 287     virtual void activateContext(ThreadID thread_num);
 288
 289     /// Notify the CPU that the indicated context is now suspended.
 290     /// Check if possible to enter a lower power state
 291     virtual void suspendContext(ThreadID thread_num);
 292
 293     /// Notify the CPU that the indicated context is now halted.
 294     virtual void haltContext(ThreadID thread_num);
 295
 296    /// Given a Thread Context pointer return the thread num
 297    int findContext(ThreadContext *tc);
 298
 299    /// Given a thread num get tho thread context for it
 300    virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; }
 301
 302    /// Get the number of thread contexts available
 303    unsigned numContexts() {
 304        return static_cast<unsigned>(threadContexts.size());
 305    }
 306
 307     /// Convert ContextID to threadID
 308     ThreadID contextToThread(ContextID cid)
 309     { return static_cast<ThreadID>(cid - threadContexts[0]->contextId()); }
 310
 311   public:
 312     typedef BaseCPUParams Params;
 313     const Params &
 314     params() const
 315     {
 316         return reinterpret_cast<const Params &>(_params);
 317     }
 318     BaseCPU(const Params &params, bool is_checker = false);
 319     virtual ~BaseCPU();
 320
 321     void init() override;
 322     void startup() override;
 323     void regStats() override;
 324
 325     void regProbePoints() override;
 326
 327     void registerThreadContexts();
 328
 329     // Functions to deschedule and reschedule the events to enter the
 330     // power gating sleep before and after checkpoiting respectively.
 331     void deschedulePowerGatingEvent();
 332     void schedulePowerGatingEvent();
 333
 334     /**
 335      * Prepare for another CPU to take over execution.
 336      *
 337      * When this method exits, all internal state should have been
 338      * flushed. After the method returns, the simulator calls
 339      * takeOverFrom() on the new CPU with this CPU as its parameter.
 340      */
 341     virtual void switchOut();
 342
 343     /**
 344      * Load the state of a CPU from the previous CPU object, invoked
 345      * on all new CPUs that are about to be switched in.
 346      *
 347      * A CPU model implementing this method is expected to initialize
 348      * its state from the old CPU and connect its memory (unless they
 349      * are already connected) to the memories connected to the old
 350      * CPU.
 351      *
 352      * @param cpu CPU to initialize read state from.
 353      */
 354     virtual void takeOverFrom(BaseCPU *cpu);
 355
 356     /**
 357      * Flush all TLBs in the CPU.
 358      *
 359      * This method is mainly used to flush stale translations when
 360      * switching CPUs. It is also exported to the Python world to
 361      * allow it to request a TLB flush after draining the CPU to make
 362      * it easier to compare traces when debugging
 363      * handover/checkpointing.
 364      */
 365     void flushTLBs();
 366
 367     /**
 368      * Determine if the CPU is switched out.
 369      *
 370      * @return True if the CPU is switched out, false otherwise.
 371      */
 372     bool switchedOut() const { return _switchedOut; }
 373
 374     /**
 375      * Verify that the system is in a memory mode supported by the
 376      * CPU.
 377      *
 378      * Implementations are expected to query the system for the
 379      * current memory mode and ensure that it is what the CPU model
 380      * expects. If the check fails, the implementation should
 381      * terminate the simulation using fatal().
 382      */
 383     virtual void verifyMemoryMode() const { };
 384
 385     /**
 386      *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
 387      * This is a constant for the duration of the simulation.
 388      */
 389     ThreadID numThreads;
 390
 391     System *system;
 392
 393     /**
 394      * Get the cache line size of the system.
 395      */
 396     inline unsigned int cacheLineSize() const { return _cacheLineSize; }
 397
 398     /**
 399      * Serialize this object to the given output stream.
 400      *
 401      * @note CPU models should normally overload the serializeThread()
 402      * method instead of the serialize() method as this provides a
 403      * uniform data format for all CPU models and promotes better code
 404      * reuse.
 405      *
 406      * @param cp The stream to serialize to.
 407      */
 408     void serialize(CheckpointOut &cp) const override;
 409
 410     /**
 411      * Reconstruct the state of this object from a checkpoint.
 412      *
 413      * @note CPU models should normally overload the
 414      * unserializeThread() method instead of the unserialize() method
 415      * as this provides a uniform data format for all CPU models and
 416      * promotes better code reuse.
 417
 418      * @param cp The checkpoint use.
 419      */
 420     void unserialize(CheckpointIn &cp) override;
 421
 422     /**
 423      * Serialize a single thread.
 424      *
 425      * @param cp The stream to serialize to.
 426      * @param tid ID of the current thread.
 427      */
 428     virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {};
 429
 430     /**
 431      * Unserialize one thread.
 432      *
 433      * @param cp The checkpoint use.
 434      * @param tid ID of the current thread.
 435      */
 436     virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {};
 437
 438     virtual Counter totalInsts() const = 0;
 439
 440     virtual Counter totalOps() const = 0;
 441
 442     /**
 443      * Schedule an event that exits the simulation loops after a
 444      * predefined number of instructions.
 445      *
 446      * This method is usually called from the configuration script to
 447      * get an exit event some time in the future. It is typically used
 448      * when the script wants to simulate for a specific number of
 449      * instructions rather than ticks.
 450      *
 451      * @param tid Thread monitor.
 452      * @param insts Number of instructions into the future.
 453      * @param cause Cause to signal in the exit event.
 454      */
 455     void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
 456
 457     /**
 458      * Get the number of instructions executed by the specified thread
 459      * on this CPU. Used by Python to control simulation.
 460      *
 461      * @param tid Thread monitor
 462      * @return Number of instructions executed
 463      */
 464     uint64_t getCurrentInstCount(ThreadID tid);
 465
 466   public:
 467     /**
 468      * @{
 469      * @name PMU Probe points.
 470      */
 471
 472     /**
 473      * Helper method to trigger PMU probes for a committed
 474      * instruction.
 475      *
 476      * @param inst Instruction that just committed
 477      * @param pc PC of the instruction that just committed
 478      */
 479     virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc);
 480
 481    protected:
 482     /**
 483      * Helper method to instantiate probe points belonging to this
 484      * object.
 485      *
 486      * @param name Name of the probe point.
 487      * @return A unique_ptr to the new probe point.
 488      */
 489     ProbePoints::PMUUPtr pmuProbePoint(const char *name);
 490
 491     /**
 492      * Instruction commit probe point.
 493      *
 494      * This probe point is triggered whenever one or more instructions
 495      * are committed. It is normally triggered once for every
 496      * instruction. However, CPU models committing bundles of
 497      * instructions may call notify once for the entire bundle.
 498      */
 499     ProbePoints::PMUUPtr ppRetiredInsts;
 500     ProbePoints::PMUUPtr ppRetiredInstsPC;
 501
 502     /** Retired load instructions */
 503     ProbePoints::PMUUPtr ppRetiredLoads;
 504     /** Retired store instructions */
 505     ProbePoints::PMUUPtr ppRetiredStores;
 506
 507     /** Retired branches (any type) */
 508     ProbePoints::PMUUPtr ppRetiredBranches;
 509
 510     /** CPU cycle counter even if any thread Context is suspended*/
 511     ProbePoints::PMUUPtr ppAllCycles;
 512
 513     /** CPU cycle counter, only counts if any thread contexts is active **/
 514     ProbePoints::PMUUPtr ppActiveCycles;
 515
 516     /**
 517      * ProbePoint that signals transitions of threadContexts sets.
 518      * The ProbePoint reports information through it bool parameter.
 519      * - If the parameter is true then the last enabled threadContext of the
 520      * CPU object was disabled.
 521      * - If the parameter is false then a threadContext was enabled, all the
 522      * remaining threadContexts are disabled.
 523      */
 524     ProbePointArg<bool> *ppSleeping;
 525     /** @} */
 526
 527     enum CPUState {
 528         CPU_STATE_ON,
 529         CPU_STATE_SLEEP,
 530         CPU_STATE_WAKEUP
 531     };
 532
 533     Cycles previousCycle;
 534     CPUState previousState;
 535
 536     /** base method keeping track of cycle progression **/
 537     inline void updateCycleCounters(CPUState state)
 538     {
 539         uint32_t delta = curCycle() - previousCycle;
 540
 541         if (previousState == CPU_STATE_ON) {
 542             ppActiveCycles->notify(delta);
 543         }
 544
 545         switch (state)
 546         {
 547           case CPU_STATE_WAKEUP:
 548             ppSleeping->notify(false);
 549             break;
 550           case CPU_STATE_SLEEP:
 551             ppSleeping->notify(true);
 552             break;
 553           default:
 554             break;
 555         }
 556
 557         ppAllCycles->notify(delta);
 558
 559         previousCycle = curCycle();
 560         previousState = state;
 561     }
 562
 563     // Function tracing
 564   private:
 565     bool functionTracingEnabled;
 566     std::ostream *functionTraceStream;
 567     Addr currentFunctionStart;
 568     Addr currentFunctionEnd;
 569     Tick functionEntryTick;
 570     void enableFunctionTrace();
 571     void traceFunctionsInternal(Addr pc);
 572
 573   private:
 574     static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
 575
 576   public:
 577     void traceFunctions(Addr pc)
 578     {
 579         if (functionTracingEnabled)
 580             traceFunctionsInternal(pc);
 581     }
 582
 583     static int numSimulatedCPUs() { return cpuList.size(); }
 584     static Counter numSimulatedInsts()
 585     {
 586         Counter total = 0;
 587
 588         int size = cpuList.size();
 589         for (int i = 0; i < size; ++i)
 590             total += cpuList[i]->totalInsts();
 591
 592         return total;
 593     }
 594
 595     static Counter numSimulatedOps()
 596     {
 597         Counter total = 0;
 598
 599         int size = cpuList.size();
 600         for (int i = 0; i < size; ++i)
 601             total += cpuList[i]->totalOps();
 602
 603         return total;
 604     }
 605
 606   public:
 607     struct BaseCPUStats : public Stats::Group
 608     {
 609         BaseCPUStats(Stats::Group *parent);
 610         // Number of CPU cycles simulated
 611         Stats::Scalar numCycles;
 612         Stats::Scalar numWorkItemsStarted;
 613         Stats::Scalar numWorkItemsCompleted;
 614     } baseStats;
 615
 616   private:
 617     std::vector<AddressMonitor> addressMonitor;
 618
 619   public:
 620     void armMonitor(ThreadID tid, Addr address);
 621     bool mwait(ThreadID tid, PacketPtr pkt);
 622     void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu);
 623     AddressMonitor *getCpuAddrMonitor(ThreadID tid)
 624     {
 625         assert(tid < numThreads);
 626         return &addressMonitor[tid];
 627     }
 628
 629     bool waitForRemoteGDB() const;
 630
 631     Cycles syscallRetryLatency;
 632
 633   // Enables CPU to enter power gating on a configurable cycle count
 634   protected:
 635     void enterPwrGating();
 636
 637     const Cycles pwrGatingLatency;
 638     const bool powerGatingOnIdle;
 639     EventFunctionWrapper enterPwrGatingEvent;
 640 };
 641
 642 #endif // THE_ISA == NULL_ISA
 643
 644 #endif // __CPU_BASE_HH__