src/cpu/base.hh

   1 /*
   2  * Copyright (c) 2011-2013, 2017, 2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2011 Regents of the University of California
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
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  24  * documentation and/or other materials provided with the distribution;
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  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_BASE_HH__
  43 #define __CPU_BASE_HH__
  44
  45 #include <vector>
  46
  47 // Before we do anything else, check if this build is the NULL ISA,
  48 // and if so stop here
  49 #include "config/the_isa.hh"
  50 #if THE_ISA == NULL_ISA
  51 #include "arch/null/cpu_dummy.hh"
  52 #else
  53 #include "arch/generic/interrupts.hh"
  54 #include "base/statistics.hh"
  55 #include "mem/port_proxy.hh"
  56 #include "sim/clocked_object.hh"
  57 #include "sim/eventq.hh"
  58 #include "sim/full_system.hh"
  59 #include "sim/insttracer.hh"
  60 #include "sim/probe/pmu.hh"
  61 #include "sim/probe/probe.hh"
  62 #include "sim/system.hh"
  63 #include "debug/Mwait.hh"
  64
  65 class BaseCPU;
  66 struct BaseCPUParams;
  67 class CheckerCPU;
  68 class ThreadContext;
  69
  70 struct AddressMonitor
  71 {
  72     AddressMonitor();
  73     bool doMonitor(PacketPtr pkt);
  74
  75     bool armed;
  76     Addr vAddr;
  77     Addr pAddr;
  78     uint64_t val;
  79     bool waiting;   // 0=normal, 1=mwaiting
  80     bool gotWakeup;
  81 };
  82
  83 class CPUProgressEvent : public Event
  84 {
  85   protected:
  86     Tick _interval;
  87     Counter lastNumInst;
  88     BaseCPU *cpu;
  89     bool _repeatEvent;
  90
  91   public:
  92     CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
  93
  94     void process();
  95
  96     void interval(Tick ival) { _interval = ival; }
  97     Tick interval() { return _interval; }
  98
  99     void repeatEvent(bool repeat) { _repeatEvent = repeat; }
 100
 101     virtual const char *description() const;
 102 };
 103
 104 class BaseCPU : public ClockedObject
 105 {
 106   protected:
 107
 108     /// Instruction count used for SPARC misc register
 109     /// @todo unify this with the counters that cpus individually keep
 110     Tick instCnt;
 111
 112     // every cpu has an id, put it in the base cpu
 113     // Set at initialization, only time a cpuId might change is during a
 114     // takeover (which should be done from within the BaseCPU anyway,
 115     // therefore no setCpuId() method is provided
 116     int _cpuId;
 117
 118     /** Each cpu will have a socket ID that corresponds to its physical location
 119      * in the system. This is usually used to bucket cpu cores under single DVFS
 120      * domain. This information may also be required by the OS to identify the
 121      * cpu core grouping (as in the case of ARM via MPIDR register)
 122      */
 123     const uint32_t _socketId;
 124
 125     /** instruction side request id that must be placed in all requests */
 126     MasterID _instMasterId;
 127
 128     /** data side request id that must be placed in all requests */
 129     MasterID _dataMasterId;
 130
 131     /** An intrenal representation of a task identifier within gem5. This is
 132      * used so the CPU can add which taskId (which is an internal representation
 133      * of the OS process ID) to each request so components in the memory system
 134      * can track which process IDs are ultimately interacting with them
 135      */
 136     uint32_t _taskId;
 137
 138     /** The current OS process ID that is executing on this processor. This is
 139      * used to generate a taskId */
 140     uint32_t _pid;
 141
 142     /** Is the CPU switched out or active? */
 143     bool _switchedOut;
 144
 145     /** Cache the cache line size that we get from the system */
 146     const unsigned int _cacheLineSize;
 147
 148   public:
 149
 150     /**
 151      * Purely virtual method that returns a reference to the data
 152      * port. All subclasses must implement this method.
 153      *
 154      * @return a reference to the data port
 155      */
 156     virtual Port &getDataPort() = 0;
 157
 158     /**
 159      * Returns a sendFunctional delegate for use with port proxies.
 160      */
 161     virtual PortProxy::SendFunctionalFunc
 162     getSendFunctional()
 163     {
 164         auto port = dynamic_cast<RequestPort *>(&getDataPort());
 165         assert(port);
 166         return [port](PacketPtr pkt)->void { port->sendFunctional(pkt); };
 167     }
 168
 169     /**
 170      * Purely virtual method that returns a reference to the instruction
 171      * port. All subclasses must implement this method.
 172      *
 173      * @return a reference to the instruction port
 174      */
 175     virtual Port &getInstPort() = 0;
 176
 177     /** Reads this CPU's ID. */
 178     int cpuId() const { return _cpuId; }
 179
 180     /** Reads this CPU's Socket ID. */
 181     uint32_t socketId() const { return _socketId; }
 182
 183     /** Reads this CPU's unique data requestor ID */
 184     MasterID dataMasterId() const { return _dataMasterId; }
 185     /** Reads this CPU's unique instruction requestor ID */
 186     MasterID instMasterId() const { return _instMasterId; }
 187
 188     /**
 189      * Get a port on this CPU. All CPUs have a data and
 190      * instruction port, and this method uses getDataPort and
 191      * getInstPort of the subclasses to resolve the two ports.
 192      *
 193      * @param if_name the port name
 194      * @param idx ignored index
 195      *
 196      * @return a reference to the port with the given name
 197      */
 198     Port &getPort(const std::string &if_name,
 199                   PortID idx=InvalidPortID) override;
 200
 201     /** Get cpu task id */
 202     uint32_t taskId() const { return _taskId; }
 203     /** Set cpu task id */
 204     void taskId(uint32_t id) { _taskId = id; }
 205
 206     uint32_t getPid() const { return _pid; }
 207     void setPid(uint32_t pid) { _pid = pid; }
 208
 209     inline void workItemBegin() { numWorkItemsStarted++; }
 210     inline void workItemEnd() { numWorkItemsCompleted++; }
 211     // @todo remove me after debugging with legion done
 212     Tick instCount() { return instCnt; }
 213
 214   protected:
 215     std::vector<BaseInterrupts*> interrupts;
 216
 217   public:
 218     BaseInterrupts *
 219     getInterruptController(ThreadID tid)
 220     {
 221         if (interrupts.empty())
 222             return NULL;
 223
 224         assert(interrupts.size() > tid);
 225         return interrupts[tid];
 226     }
 227
 228     virtual void wakeup(ThreadID tid) = 0;
 229
 230     void
 231     postInterrupt(ThreadID tid, int int_num, int index);
 232
 233     void
 234     clearInterrupt(ThreadID tid, int int_num, int index)
 235     {
 236         interrupts[tid]->clear(int_num, index);
 237     }
 238
 239     void
 240     clearInterrupts(ThreadID tid)
 241     {
 242         interrupts[tid]->clearAll();
 243     }
 244
 245     bool
 246     checkInterrupts(ThreadID tid) const
 247     {
 248         return FullSystem && interrupts[tid]->checkInterrupts();
 249     }
 250
 251   protected:
 252     std::vector<ThreadContext *> threadContexts;
 253
 254     Trace::InstTracer * tracer;
 255
 256   public:
 257
 258
 259     /** Invalid or unknown Pid. Possible when operating system is not present
 260      *  or has not assigned a pid yet */
 261     static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
 262
 263     // Mask to align PCs to MachInst sized boundaries
 264     static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
 265
 266     /// Provide access to the tracer pointer
 267     Trace::InstTracer * getTracer() { return tracer; }
 268
 269     /// Notify the CPU that the indicated context is now active.
 270     virtual void activateContext(ThreadID thread_num);
 271
 272     /// Notify the CPU that the indicated context is now suspended.
 273     /// Check if possible to enter a lower power state
 274     virtual void suspendContext(ThreadID thread_num);
 275
 276     /// Notify the CPU that the indicated context is now halted.
 277     virtual void haltContext(ThreadID thread_num);
 278
 279    /// Given a Thread Context pointer return the thread num
 280    int findContext(ThreadContext *tc);
 281
 282    /// Given a thread num get tho thread context for it
 283    virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; }
 284
 285    /// Get the number of thread contexts available
 286    unsigned numContexts() {
 287        return static_cast<unsigned>(threadContexts.size());
 288    }
 289
 290     /// Convert ContextID to threadID
 291     ThreadID contextToThread(ContextID cid)
 292     { return static_cast<ThreadID>(cid - threadContexts[0]->contextId()); }
 293
 294   public:
 295     typedef BaseCPUParams Params;
 296     const Params *params() const
 297     { return reinterpret_cast<const Params *>(_params); }
 298     BaseCPU(Params *params, bool is_checker = false);
 299     virtual ~BaseCPU();
 300
 301     void init() override;
 302     void startup() override;
 303     void regStats() override;
 304
 305     void regProbePoints() override;
 306
 307     void registerThreadContexts();
 308
 309     // Functions to deschedule and reschedule the events to enter the
 310     // power gating sleep before and after checkpoiting respectively.
 311     void deschedulePowerGatingEvent();
 312     void schedulePowerGatingEvent();
 313
 314     /**
 315      * Prepare for another CPU to take over execution.
 316      *
 317      * When this method exits, all internal state should have been
 318      * flushed. After the method returns, the simulator calls
 319      * takeOverFrom() on the new CPU with this CPU as its parameter.
 320      */
 321     virtual void switchOut();
 322
 323     /**
 324      * Load the state of a CPU from the previous CPU object, invoked
 325      * on all new CPUs that are about to be switched in.
 326      *
 327      * A CPU model implementing this method is expected to initialize
 328      * its state from the old CPU and connect its memory (unless they
 329      * are already connected) to the memories connected to the old
 330      * CPU.
 331      *
 332      * @param cpu CPU to initialize read state from.
 333      */
 334     virtual void takeOverFrom(BaseCPU *cpu);
 335
 336     /**
 337      * Flush all TLBs in the CPU.
 338      *
 339      * This method is mainly used to flush stale translations when
 340      * switching CPUs. It is also exported to the Python world to
 341      * allow it to request a TLB flush after draining the CPU to make
 342      * it easier to compare traces when debugging
 343      * handover/checkpointing.
 344      */
 345     void flushTLBs();
 346
 347     /**
 348      * Determine if the CPU is switched out.
 349      *
 350      * @return True if the CPU is switched out, false otherwise.
 351      */
 352     bool switchedOut() const { return _switchedOut; }
 353
 354     /**
 355      * Verify that the system is in a memory mode supported by the
 356      * CPU.
 357      *
 358      * Implementations are expected to query the system for the
 359      * current memory mode and ensure that it is what the CPU model
 360      * expects. If the check fails, the implementation should
 361      * terminate the simulation using fatal().
 362      */
 363     virtual void verifyMemoryMode() const { };
 364
 365     /**
 366      *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
 367      * This is a constant for the duration of the simulation.
 368      */
 369     ThreadID numThreads;
 370
 371     System *system;
 372
 373     /**
 374      * Get the cache line size of the system.
 375      */
 376     inline unsigned int cacheLineSize() const { return _cacheLineSize; }
 377
 378     /**
 379      * Serialize this object to the given output stream.
 380      *
 381      * @note CPU models should normally overload the serializeThread()
 382      * method instead of the serialize() method as this provides a
 383      * uniform data format for all CPU models and promotes better code
 384      * reuse.
 385      *
 386      * @param cp The stream to serialize to.
 387      */
 388     void serialize(CheckpointOut &cp) const override;
 389
 390     /**
 391      * Reconstruct the state of this object from a checkpoint.
 392      *
 393      * @note CPU models should normally overload the
 394      * unserializeThread() method instead of the unserialize() method
 395      * as this provides a uniform data format for all CPU models and
 396      * promotes better code reuse.
 397
 398      * @param cp The checkpoint use.
 399      */
 400     void unserialize(CheckpointIn &cp) override;
 401
 402     /**
 403      * Serialize a single thread.
 404      *
 405      * @param cp The stream to serialize to.
 406      * @param tid ID of the current thread.
 407      */
 408     virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {};
 409
 410     /**
 411      * Unserialize one thread.
 412      *
 413      * @param cp The checkpoint use.
 414      * @param tid ID of the current thread.
 415      */
 416     virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {};
 417
 418     virtual Counter totalInsts() const = 0;
 419
 420     virtual Counter totalOps() const = 0;
 421
 422     /**
 423      * Schedule an event that exits the simulation loops after a
 424      * predefined number of instructions.
 425      *
 426      * This method is usually called from the configuration script to
 427      * get an exit event some time in the future. It is typically used
 428      * when the script wants to simulate for a specific number of
 429      * instructions rather than ticks.
 430      *
 431      * @param tid Thread monitor.
 432      * @param insts Number of instructions into the future.
 433      * @param cause Cause to signal in the exit event.
 434      */
 435     void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
 436
 437     /**
 438      * Get the number of instructions executed by the specified thread
 439      * on this CPU. Used by Python to control simulation.
 440      *
 441      * @param tid Thread monitor
 442      * @return Number of instructions executed
 443      */
 444     uint64_t getCurrentInstCount(ThreadID tid);
 445
 446   public:
 447     /**
 448      * @{
 449      * @name PMU Probe points.
 450      */
 451
 452     /**
 453      * Helper method to trigger PMU probes for a committed
 454      * instruction.
 455      *
 456      * @param inst Instruction that just committed
 457      * @param pc PC of the instruction that just committed
 458      */
 459     virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc);
 460
 461    protected:
 462     /**
 463      * Helper method to instantiate probe points belonging to this
 464      * object.
 465      *
 466      * @param name Name of the probe point.
 467      * @return A unique_ptr to the new probe point.
 468      */
 469     ProbePoints::PMUUPtr pmuProbePoint(const char *name);
 470
 471     /**
 472      * Instruction commit probe point.
 473      *
 474      * This probe point is triggered whenever one or more instructions
 475      * are committed. It is normally triggered once for every
 476      * instruction. However, CPU models committing bundles of
 477      * instructions may call notify once for the entire bundle.
 478      */
 479     ProbePoints::PMUUPtr ppRetiredInsts;
 480     ProbePoints::PMUUPtr ppRetiredInstsPC;
 481
 482     /** Retired load instructions */
 483     ProbePoints::PMUUPtr ppRetiredLoads;
 484     /** Retired store instructions */
 485     ProbePoints::PMUUPtr ppRetiredStores;
 486
 487     /** Retired branches (any type) */
 488     ProbePoints::PMUUPtr ppRetiredBranches;
 489
 490     /** CPU cycle counter even if any thread Context is suspended*/
 491     ProbePoints::PMUUPtr ppAllCycles;
 492
 493     /** CPU cycle counter, only counts if any thread contexts is active **/
 494     ProbePoints::PMUUPtr ppActiveCycles;
 495
 496     /**
 497      * ProbePoint that signals transitions of threadContexts sets.
 498      * The ProbePoint reports information through it bool parameter.
 499      * - If the parameter is true then the last enabled threadContext of the
 500      * CPU object was disabled.
 501      * - If the parameter is false then a threadContext was enabled, all the
 502      * remaining threadContexts are disabled.
 503      */
 504     ProbePointArg<bool> *ppSleeping;
 505     /** @} */
 506
 507     enum CPUState {
 508         CPU_STATE_ON,
 509         CPU_STATE_SLEEP,
 510         CPU_STATE_WAKEUP
 511     };
 512
 513     Cycles previousCycle;
 514     CPUState previousState;
 515
 516     /** base method keeping track of cycle progression **/
 517     inline void updateCycleCounters(CPUState state)
 518     {
 519         uint32_t delta = curCycle() - previousCycle;
 520
 521         if (previousState == CPU_STATE_ON) {
 522             ppActiveCycles->notify(delta);
 523         }
 524
 525         switch (state)
 526         {
 527           case CPU_STATE_WAKEUP:
 528             ppSleeping->notify(false);
 529             break;
 530           case CPU_STATE_SLEEP:
 531             ppSleeping->notify(true);
 532             break;
 533           default:
 534             break;
 535         }
 536
 537         ppAllCycles->notify(delta);
 538
 539         previousCycle = curCycle();
 540         previousState = state;
 541     }
 542
 543     // Function tracing
 544   private:
 545     bool functionTracingEnabled;
 546     std::ostream *functionTraceStream;
 547     Addr currentFunctionStart;
 548     Addr currentFunctionEnd;
 549     Tick functionEntryTick;
 550     void enableFunctionTrace();
 551     void traceFunctionsInternal(Addr pc);
 552
 553   private:
 554     static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
 555
 556   public:
 557     void traceFunctions(Addr pc)
 558     {
 559         if (functionTracingEnabled)
 560             traceFunctionsInternal(pc);
 561     }
 562
 563     static int numSimulatedCPUs() { return cpuList.size(); }
 564     static Counter numSimulatedInsts()
 565     {
 566         Counter total = 0;
 567
 568         int size = cpuList.size();
 569         for (int i = 0; i < size; ++i)
 570             total += cpuList[i]->totalInsts();
 571
 572         return total;
 573     }
 574
 575     static Counter numSimulatedOps()
 576     {
 577         Counter total = 0;
 578
 579         int size = cpuList.size();
 580         for (int i = 0; i < size; ++i)
 581             total += cpuList[i]->totalOps();
 582
 583         return total;
 584     }
 585
 586   public:
 587     // Number of CPU cycles simulated
 588     Stats::Scalar numCycles;
 589     Stats::Scalar numWorkItemsStarted;
 590     Stats::Scalar numWorkItemsCompleted;
 591
 592   private:
 593     std::vector<AddressMonitor> addressMonitor;
 594
 595   public:
 596     void armMonitor(ThreadID tid, Addr address);
 597     bool mwait(ThreadID tid, PacketPtr pkt);
 598     void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb);
 599     AddressMonitor *getCpuAddrMonitor(ThreadID tid)
 600     {
 601         assert(tid < numThreads);
 602         return &addressMonitor[tid];
 603     }
 604
 605     bool waitForRemoteGDB() const;
 606
 607     Cycles syscallRetryLatency;
 608
 609   // Enables CPU to enter power gating on a configurable cycle count
 610   protected:
 611     void enterPwrGating();
 612
 613     const Cycles pwrGatingLatency;
 614     const bool powerGatingOnIdle;
 615     EventFunctionWrapper enterPwrGatingEvent;
 616 };
 617
 618 #endif // THE_ISA == NULL_ISA
 619
 620 #endif // __CPU_BASE_HH__